API tools faq
paste
Advertisement
Guest User

Untitled

a guest
Oct 16th, 2019
75
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 6.37 KB | None | 0 0
raw download clone embed print report
  1. ASTEBINnew paste
  2. search...
  3.  
  4.  
  5. Guest User
  6. -
  7. SHARE
  8. TWEET
  9.  
  10. Untitled
  11. OHGODAPET OCT 16TH, 2019 3 NEVER
  12.  
  13. Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  14. rawdownloadcloneembedreportprintSystemVerilog 5.78 KB
  15. `timescale 1ns / 1ps
  16.  
  17. `define IDX64(x) ((x) << 6)+:64
  18. `define ROTL64(x, y) {x[63 - y : 0], x[63: 63 - y + 1]}
  19.  
  20. module KeccakF1600Perm(output wire [1599:0] OutState, input wire [1599:0] InState, input wire[63:0] RndConst);
  21.  
  22. // It probably seems odd - why the wires used are structured like this,
  23. // as well as why the input/output states are 1600-bit vectors. The
  24. // less important reasoning is maintaining compatibility with Verilog at
  25. // least as far back as its 2001 spec (in contrast to SystemVerilog),
  26. // as it will not allow passing arrays to modules. The more important
  27. // is that it seems to produce my *intended* HW design over a large
  28. // variety of settings with Vivado - even over different versions of it.
  29. // It often will repeat work - instead of having the 5-input XOR values
  30. // done, then their XOR with one another only once (Theta) - it'll
  31. // instead re-do them as needed through Rho, Pi, and even occasionally
  32. // during Chi as well. The area becomes the relative size of Texas.
  33.  
  34. wire [63:0] RoundMid[24:0];
  35. wire [63:0] Mid0, Mid1, Mid2, Mid3, Mid4, Mid5, Mid6, Mid7, Mid8;
  36. wire [63:0] Mid9, Mid10, Mid11, Mid12, Mid13, Mid14, Mid15, Mid16;
  37. wire [63:0] Mid17, Mid18, Mid19, Mid20, Mid21, Mid22, Mid23, Mid24;
  38. wire [63:0] InitXORVals0, InitXORVals1, InitXORVals2, InitXORVals3, InitXORVals4;
  39. wire [63:0] MainXORVals0, MainXORVals1, MainXORVals2, MainXORVals3, MainXORVals4;
  40.  
  41. genvar x;
  42.  
  43. // Theta
  44. assign InitXORVals0 = InState[`IDX64(0)] ^ InState[`IDX64(5)] ^ InState[`IDX64(10)] ^ InState[`IDX64(15)] ^ InState[`IDX64(20)];
  45. assign InitXORVals1 = InState[`IDX64(0 + 1)] ^ InState[`IDX64(5 + 1)] ^ InState[`IDX64(10 + 1)] ^ InState[`IDX64(15 + 1)] ^ InState[`IDX64(20 + 1)];
  46. assign InitXORVals2 = InState[`IDX64(0 + 2)] ^ InState[`IDX64(5 + 2)] ^ InState[`IDX64(10 + 2)] ^ InState[`IDX64(15 + 2)] ^ InState[`IDX64(20 + 2)];
  47. assign InitXORVals3 = InState[`IDX64(0 + 3)] ^ InState[`IDX64(5 + 3)] ^ InState[`IDX64(10 + 3)] ^ InState[`IDX64(15 + 3)] ^ InState[`IDX64(20 + 3)];
  48. assign InitXORVals4 = InState[`IDX64(0 + 4)] ^ InState[`IDX64(5 + 4)] ^ InState[`IDX64(10 + 4)] ^ InState[`IDX64(15 + 4)] ^ InState[`IDX64(20 + 4)];
  49.  
  50. assign MainXORVals0 = InitXORVals0 ^ `ROTL64(InitXORVals2, 1);
  51. assign MainXORVals1 = InitXORVals1 ^ `ROTL64(InitXORVals3, 1);
  52. assign MainXORVals2 = InitXORVals2 ^ `ROTL64(InitXORVals4, 1);
  53. assign MainXORVals3 = InitXORVals3 ^ `ROTL64(InitXORVals0, 1);
  54. assign MainXORVals4 = InitXORVals4 ^ `ROTL64(InitXORVals1, 1);
  55.  
  56. assign Mid1 = InState[`IDX64(6)] ^ MainXORVals0;
  57. assign RoundMid[1] = `ROTL64(Mid1, 44);
  58. assign Mid8 = InState[`IDX64(16)] ^ MainXORVals0;
  59. assign RoundMid[8] = `ROTL64(Mid8, 45);
  60. assign Mid10 = InState[`IDX64(1)] ^ MainXORVals0;
  61. assign RoundMid[10] = `ROTL64(Mid10, 1);
  62. assign Mid17 = InState[`IDX64(11)] ^ MainXORVals0;
  63. assign RoundMid[17] = `ROTL64(Mid17, 10);
  64. assign Mid24 = InState[`IDX64(21)] ^ MainXORVals0;
  65. assign RoundMid[24] = `ROTL64(Mid24, 2);
  66.  
  67. assign Mid2 = InState[`IDX64(12)] ^ MainXORVals1;
  68. assign RoundMid[2] = `ROTL64(Mid2, 43);
  69. assign Mid9 = InState[`IDX64(22)] ^ MainXORVals1;
  70. assign RoundMid[9] = `ROTL64(Mid9, 61);
  71. assign Mid11 = InState[`IDX64(7)] ^ MainXORVals1;
  72. assign RoundMid[11] = `ROTL64(Mid11, 6);
  73. assign Mid18 = InState[`IDX64(17)] ^ MainXORVals1;
  74. assign RoundMid[18] = `ROTL64(Mid18, 15);
  75. assign Mid20 = InState[`IDX64(2)] ^ MainXORVals1;
  76. assign RoundMid[20] = `ROTL64(Mid20, 62);
  77.  
  78. assign Mid3 = InState[`IDX64(18)] ^ MainXORVals2;
  79. assign RoundMid[3] = `ROTL64(Mid3, 21);
  80. assign Mid5 = InState[`IDX64(3)] ^ MainXORVals2;
  81. assign RoundMid[5] = `ROTL64(Mid5, 28);
  82. assign Mid12 = InState[`IDX64(13)] ^ MainXORVals2;
  83. assign RoundMid[12] = `ROTL64(Mid12, 25);
  84. assign Mid19 = InState[`IDX64(23)] ^ MainXORVals2;
  85. assign RoundMid[19] = `ROTL64(Mid19, 56);
  86. assign Mid21 = InState[`IDX64(8)] ^ MainXORVals2;
  87. assign RoundMid[21] = `ROTL64(Mid21, 55);
  88.  
  89. assign Mid4 = InState[`IDX64(24)] ^ MainXORVals3;
  90. assign RoundMid[4] = `ROTL64(Mid4, 14);
  91. assign Mid6 = InState[`IDX64(9)] ^ MainXORVals3;
  92. assign RoundMid[6] = `ROTL64(Mid6, 20);
  93. assign Mid13 = InState[`IDX64(19)] ^ MainXORVals3;
  94. assign RoundMid[13] = `ROTL64(Mid13, 8);
  95. assign Mid15 = InState[`IDX64(4)] ^ MainXORVals3;
  96. assign RoundMid[15] = `ROTL64(Mid15, 27);
  97. assign Mid22 = InState[`IDX64(14)] ^ MainXORVals3;
  98. assign RoundMid[22] = `ROTL64(Mid22, 39);
  99.  
  100. assign Mid0 = InState[`IDX64(0)] ^ MainXORVals4;
  101. assign RoundMid[0] = Mid0;
  102. assign Mid7 = InState[`IDX64(10)] ^ MainXORVals4;
  103. assign RoundMid[7] = `ROTL64(Mid7, 3);
  104. assign Mid14 = InState[`IDX64(20)] ^ MainXORVals4;
  105. assign RoundMid[14] = `ROTL64(Mid14, 18);
  106. assign Mid16 = InState[`IDX64(5)] ^ MainXORVals4;
  107. assign RoundMid[16] = `ROTL64(Mid16, 36);
  108. assign Mid23 = InState[`IDX64(15)] ^ MainXORVals4;
  109. assign RoundMid[23] = `ROTL64(Mid23, 41);
  110.  
  111. // Chi / Iota
  112. assign OutState[`IDX64(0)] = RoundMid[0] ^ ((~RoundMid[1]) & RoundMid[2]) ^ RndConst;
  113. assign OutState[`IDX64(1)] = RoundMid[1] ^ ((~RoundMid[2]) & RoundMid[3]);
  114. assign OutState[`IDX64(2)] = RoundMid[2] ^ ((~RoundMid[3]) & RoundMid[4]);
  115. assign OutState[`IDX64(3)] = RoundMid[3] ^ ((~RoundMid[4]) & RoundMid[0]);
  116. assign OutState[`IDX64(4)] = RoundMid[4] ^ ((~RoundMid[0]) & RoundMid[1]);
  117.  
  118. generate
  119.  
  120. for(x = 5; x < 25; x = x + 5)
  121. begin : CHILOOP0
  122. assign OutState[`IDX64(0 + x)] = RoundMid[0 + x] ^ ((~RoundMid[1 + x]) & RoundMid[2 + x]);
  123. assign OutState[`IDX64(1 + x)] = RoundMid[1 + x] ^ ((~RoundMid[2 + x]) & RoundMid[3 + x]);
  124. assign OutState[`IDX64(2 + x)] = RoundMid[2 + x] ^ ((~RoundMid[3 + x]) & RoundMid[4 + x]);
  125. assign OutState[`IDX64(3 + x)] = RoundMid[3 + x] ^ ((~RoundMid[4 + x]) & RoundMid[0 + x]);
  126. assign OutState[`IDX64(4 + x)] = RoundMid[4 + x] ^ ((~RoundMid[0 + x]) & RoundMid[1 + x]);
  127. end
  128.  
  129. endgenerate
  130.  
  131. endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!