`define DEBUG

module dbl(
		input clk,rst,
		input logic [N-1:0] alpha,Xn,Zn,
		output logic [N-1:0] X2n,Z2n
`ifdef DEBUG
		,output wire [3:0] o_count,
		output wire [2:0] o_in_sel0,o_in_sel1,o_in_sel2,
		output wire [N-1:0] o_calc_out0,o_calc_out1,o_calc_out2,
		output wire [N-1:0] o_memory_out0,o_memory_out1,o_memory_out2,o_memory_out3,o_memory_out4,o_memory_out5
`endif
	);

	parameter N = 16;

	logic inf;
	logic [N-1:0] calc_out[2:0];
	logic [N-1:0] memory_out[5:0];
	logic [2:0] in_sel[2:0];
	logic [2:0] out_sel[5:0];
	logic [3:0] count;

	adder adder1(memory_out[0],memory_out[1],calc_out[0]);
	subtractor subtractor1(memory_out[2],memory_out[3],calc_out[1]);
	multiplier multiplier3(memory_out[4],memory_out[5],calc_out[2]);
	memory_d memory_d1(clk,rst,in_sel,out_sel,alpha,Xn,Zn,calc_out,memory_out);

	initial begin
		count=4'b0000;
		in_sel='{3'b101,3'b101,3'b101};
		out_sel='{3'b000,3'b000,3'b010,3'b001,3'b010,3'b001};
	end

`ifdef DEBUG
	assign o_count=count;
	assign o_in_sel0=in_sel[0];
	assign o_in_sel1=in_sel[1];
	assign o_in_sel2=in_sel[2];
	assign o_calc_out0=calc_out[0];
	assign o_calc_out1=calc_out[1];
	assign o_calc_out2=calc_out[2];
	assign o_memory_out0=memory_out[0];
	assign o_memory_out1=memory_out[1];
	assign o_memory_out2=memory_out[2];
	assign o_memory_out3=memory_out[3];
	assign o_memory_out4=memory_out[4];
	assign o_memory_out5=memory_out[5];
`endif

	always @(posedge clk or negedge rst) begin
		if(rst==0) begin
			count=4'b0000;
			in_sel='{3'b101,3'b101,3'b101};
			out_sel='{3'b000,3'b000,3'b010,3'b001,3'b010,3'b001};
		end else begin
			case(count)
				4'b0000:begin
					if(Zn==0)begin
						inf=1;
						X2n=Xn;
						Z2n=Zn;
					end else begin
						inf=0;
					end
					in_sel='{3'b101,3'b010,3'b001};
					out_sel='{3'b001,3'b001,3'b000,3'b000,3'b000,3'b000};
					count=4'b0001;
				end
				4'b0001:begin
					in_sel='{3'b011,3'b101,3'b101};
					out_sel='{3'b010,3'b010,3'b000,3'b000,3'b000,3'b000};
					count=4'b0010;
				end
				4'b0010:begin
					in_sel='{3'b100,3'b101,3'b101};
					out_sel='{3'b100,3'b011,3'b100,3'b011,3'b000,3'b000};
					count=4'b0011;
				end
				4'b0011:begin
					in_sel='{3'b011,3'b010,3'b101};
					out_sel='{3'b010,3'b000,3'b000,3'b000,3'b000,3'b000};
					count=4'b0100;
				end
				4'b0100:begin
					if(inf==0)begin
						X2n=calc_out[2];
					end
					in_sel='{3'b001,3'b101,3'b101};
					out_sel='{3'b000,3'b000,3'b000,3'b000,3'b001,3'b100};
					count=4'b0101;
				end
				4'b0101:begin
					in_sel='{3'b101,3'b101,3'b001};
					out_sel='{3'b001,3'b010,3'b000,3'b000,3'b000,3'b000};
					count=4'b0110;
				end
				4'b0110:begin
					in_sel='{3'b100,3'b101,3'b101};
					out_sel='{3'b000,3'b000,3'b010,3'b001,3'b010,3'b001};
					count=4'b0111;
				end
				4'b0111:begin
					if(inf==0)begin
						Z2n=calc_out[2];
					end
					in_sel='{3'b101,3'b010,3'b001};
					out_sel='{3'b000,3'b000,3'b010,3'b001,3'b010,3'b001};
					count=4'b1111;
				end
				default:begin
				end
			endcase
		end
	end

endmodule