-------------------------------------------------------------
-- authors: Tom Davidson and Peter Bertels
-- date: 2009-10-07
-------------------------------------------------------------
-- Complex Systems Design Methodology
-- Calculator - implementation of a stack
-------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity stack is
    generic (
        width: integer :=8;
        depth: integer :=3
    );
	port (
		clk: in std_ulogic;
		rst: in std_ulogic;
		push: in std_ulogic;
		pop: in std_ulogic;
		error: out std_ulogic;
		data_valid: out std_ulogic;
		data_in: in std_ulogic_vector(width-1 downto 0);
		data_out: out std_ulogic_vector(width-1 downto 0)
	);
end stack;


architecture behaviour of stack is
	type STATE_TYPE is (STATE_WAIT, STATE_POP, STATE_PUSH);
	signal state: STATE_TYPE;

	type mem is array(natural range <>) of std_ulogic_vector(width-1 downto 0);
begin

	stack: process (clk, rst) is

    variable memory: mem(0 to depth-1);
    variable pointer: integer range 0 to 2**depth-1;

	begin
	    if rst = '1' then
	        data_valid <= '1';
	    	state <= STATE_WAIT;
	    	pointer := 0;
	    	memory(0) := (others => '0');
	    elsif rising_edge(clk) then
			if state = STATE_WAIT and push = '1' then
	            data_valid <= '0';
				state <= STATE_PUSH;
				if pointer < 2**depth-1 then
				    pointer := pointer+1;
				    memory(pointer) := data_in;
				else
				    error <= '1';
				end if;
			elsif state = STATE_PUSH and push = '0' then
			    error <= '0';
	            data_valid <= '1';
				state <= STATE_WAIT;
			elsif state = STATE_WAIT and pop = '1' then
	            data_valid <= '0';
				state <= STATE_POP;
				if pointer > 0 then
				    pointer := pointer-1;
				else
				    error <= '1';
				end if;
			elsif state = STATE_POP and pop = '0' then
			    error <= '0';
	            data_valid <= '1';
				state <= STATE_WAIT;
			else
			    state <= state;
			end if;
			data_out <= memory(pointer);
	    end if;
	end process stack;

end architecture behaviour;