`timescale 1ns/1ps
module test_cnt;
logic clk, clrn;

initial
begin
    clk=0;
    forever #10 clk = ~clk;
end
initial
begin
    clrn = 1;
    #50 clrn = ~clrn;
    #60 clrn = ~clrn;
    #70 clrn = ~clrn;
    #80 clrn = ~clrn;
    #100 clrn = ~clrn;
    #300 $stop;
end
cnt uut_inst(clk, clrn, q);
endmodule