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sun50i-a64-pine64-lts.dts

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  1. /dts-v1/;
  2.  
  3. / {
  4. interrupt-parent = <0x1>;
  5. #address-cells = <0x1>;
  6. #size-cells = <0x1>;
  7. model = "Pine64+";
  8. compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
  9.  
  10. chosen {
  11. #address-cells = <0x1>;
  12. #size-cells = <0x1>;
  13. ranges;
  14. stdout-path = "serial0:115200n8";
  15.  
  16. framebuffer-lcd {
  17. compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  18. allwinner,pipeline = "mixer0-lcd0";
  19. clocks = <0x2 0x64 0x3 0x6>;
  20. status = "disabled";
  21. phandle = <0x50>;
  22. };
  23.  
  24. framebuffer-hdmi {
  25. compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  26. allwinner,pipeline = "mixer1-lcd1-hdmi";
  27. clocks = <0x3 0x7 0x2 0x65 0x2 0x6e>;
  28. status = "disabled";
  29. vcc-hdmi-supply = <0x4>;
  30. phandle = <0x51>;
  31. };
  32. };
  33.  
  34. cpus {
  35. #address-cells = <0x1>;
  36. #size-cells = <0x0>;
  37.  
  38. cpu@0 {
  39. compatible = "arm,cortex-a53";
  40. device_type = "cpu";
  41. reg = <0x0>;
  42. enable-method = "psci";
  43. next-level-cache = <0x5>;
  44. clocks = <0x2 0x15>;
  45. clock-names = "cpu";
  46. #cooling-cells = <0x2>;
  47. operating-points-v2 = <0x6>;
  48. cpu-supply = <0x7>;
  49. phandle = <0xa>;
  50. };
  51.  
  52. cpu@1 {
  53. compatible = "arm,cortex-a53";
  54. device_type = "cpu";
  55. reg = <0x1>;
  56. enable-method = "psci";
  57. next-level-cache = <0x5>;
  58. clocks = <0x2 0x15>;
  59. clock-names = "cpu";
  60. #cooling-cells = <0x2>;
  61. operating-points-v2 = <0x6>;
  62. cpu-supply = <0x7>;
  63. phandle = <0xb>;
  64. };
  65.  
  66. cpu@2 {
  67. compatible = "arm,cortex-a53";
  68. device_type = "cpu";
  69. reg = <0x2>;
  70. enable-method = "psci";
  71. next-level-cache = <0x5>;
  72. clocks = <0x2 0x15>;
  73. clock-names = "cpu";
  74. #cooling-cells = <0x2>;
  75. operating-points-v2 = <0x6>;
  76. cpu-supply = <0x7>;
  77. phandle = <0xc>;
  78. };
  79.  
  80. cpu@3 {
  81. compatible = "arm,cortex-a53";
  82. device_type = "cpu";
  83. reg = <0x3>;
  84. enable-method = "psci";
  85. next-level-cache = <0x5>;
  86. clocks = <0x2 0x15>;
  87. clock-names = "cpu";
  88. #cooling-cells = <0x2>;
  89. operating-points-v2 = <0x6>;
  90. cpu-supply = <0x7>;
  91. phandle = <0xd>;
  92. };
  93.  
  94. l2-cache {
  95. compatible = "cache";
  96. cache-level = <0x2>;
  97. phandle = <0x5>;
  98. };
  99. };
  100.  
  101. display-engine {
  102. compatible = "allwinner,sun50i-a64-display-engine";
  103. allwinner,pipelines = <0x8 0x9>;
  104. status = "okay";
  105. phandle = <0x52>;
  106. };
  107.  
  108. osc24M_clk {
  109. #clock-cells = <0x0>;
  110. compatible = "fixed-clock";
  111. clock-frequency = <0x16e3600>;
  112. clock-output-names = "osc24M";
  113. phandle = <0x2b>;
  114. };
  115.  
  116. osc32k_clk {
  117. #clock-cells = <0x0>;
  118. compatible = "fixed-clock";
  119. clock-frequency = <0x8000>;
  120. clock-output-names = "ext-osc32k";
  121. phandle = <0x49>;
  122. };
  123.  
  124. pmu {
  125. compatible = "arm,cortex-a53-pmu";
  126. interrupts = <0x0 0x74 0x4 0x0 0x75 0x4 0x0 0x76 0x4 0x0 0x77 0x4>;
  127. interrupt-affinity = <0xa 0xb 0xc 0xd>;
  128. };
  129.  
  130. psci {
  131. compatible = "arm,psci-0.2";
  132. method = "smc";
  133. };
  134.  
  135. sound {
  136. #address-cells = <0x1>;
  137. #size-cells = <0x0>;
  138. compatible = "simple-audio-card";
  139. simple-audio-card,name = "sun50i-a64-audio";
  140. simple-audio-card,aux-devs = <0xe>;
  141. simple-audio-card,routing = "Headphone Jack", "HP", "Left DAC", "DAC Left", "Right DAC", "DAC Right", "ADC Left", "Left ADC", "ADC Right", "Right ADC", "MIC2", "Microphone Jack";
  142. status = "okay";
  143. simple-audio-card,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack";
  144. phandle = <0x53>;
  145.  
  146. simple-audio-card,dai-link@0 {
  147. format = "i2s";
  148. frame-master = <0xf>;
  149. bitclock-master = <0xf>;
  150. mclk-fs = <0x80>;
  151.  
  152. cpu {
  153. sound-dai = <0x10>;
  154. phandle = <0xf>;
  155. };
  156.  
  157. codec {
  158. sound-dai = <0x11 0x0>;
  159. phandle = <0x54>;
  160. };
  161. };
  162. };
  163.  
  164. sound_spdif {
  165. compatible = "simple-audio-card";
  166. simple-audio-card,name = "On-board SPDIF";
  167.  
  168. simple-audio-card,cpu {
  169. sound-dai = <0x12>;
  170. };
  171.  
  172. simple-audio-card,codec {
  173. sound-dai = <0x13>;
  174. };
  175. };
  176.  
  177. spdif-out {
  178. #sound-dai-cells = <0x0>;
  179. compatible = "linux,spdif-dit";
  180. phandle = <0x13>;
  181. };
  182.  
  183. timer {
  184. compatible = "arm,armv8-timer";
  185. allwinner,erratum-unknown1;
  186. interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>;
  187. };
  188.  
  189. thermal-zones {
  190.  
  191. cpu0-thermal {
  192. polling-delay-passive = <0x0>;
  193. polling-delay = <0x0>;
  194. thermal-sensors = <0x14 0x0>;
  195. phandle = <0x55>;
  196.  
  197. cooling-maps {
  198.  
  199. map0 {
  200. trip = <0x15>;
  201. cooling-device = <0xa 0xffffffff 0xffffffff 0xb 0xffffffff 0xffffffff 0xc 0xffffffff 0xffffffff 0xd 0xffffffff 0xffffffff>;
  202. };
  203.  
  204. map1 {
  205. trip = <0x16>;
  206. cooling-device = <0xa 0xffffffff 0xffffffff 0xb 0xffffffff 0xffffffff 0xc 0xffffffff 0xffffffff 0xd 0xffffffff 0xffffffff>;
  207. };
  208. };
  209.  
  210. trips {
  211.  
  212. cpu_alert0 {
  213. temperature = <0x124f8>;
  214. hysteresis = <0x7d0>;
  215. type = "passive";
  216. phandle = <0x15>;
  217. };
  218.  
  219. cpu_alert1 {
  220. temperature = <0x15f90>;
  221. hysteresis = <0x7d0>;
  222. type = "hot";
  223. phandle = <0x16>;
  224. };
  225.  
  226. cpu_crit {
  227. temperature = <0x1adb0>;
  228. hysteresis = <0x7d0>;
  229. type = "critical";
  230. phandle = <0x56>;
  231. };
  232. };
  233. };
  234.  
  235. gpu0-thermal {
  236. polling-delay-passive = <0x0>;
  237. polling-delay = <0x0>;
  238. thermal-sensors = <0x14 0x1>;
  239. phandle = <0x57>;
  240. };
  241.  
  242. gpu1-thermal {
  243. polling-delay-passive = <0x0>;
  244. polling-delay = <0x0>;
  245. thermal-sensors = <0x14 0x2>;
  246. phandle = <0x58>;
  247. };
  248. };
  249.  
  250. soc {
  251. compatible = "simple-bus";
  252. #address-cells = <0x1>;
  253. #size-cells = <0x1>;
  254. ranges;
  255.  
  256. bus@1000000 {
  257. compatible = "allwinner,sun50i-a64-de2";
  258. reg = <0x1000000 0x400000>;
  259. allwinner,sram = <0x17 0x1>;
  260. #address-cells = <0x1>;
  261. #size-cells = <0x1>;
  262. ranges = <0x0 0x1000000 0x400000>;
  263.  
  264. clock@0 {
  265. compatible = "allwinner,sun50i-a64-de2-clk";
  266. reg = <0x0 0x10000>;
  267. clocks = <0x2 0x34 0x2 0x63>;
  268. clock-names = "bus", "mod";
  269. resets = <0x2 0x1e>;
  270. #clock-cells = <0x1>;
  271. #reset-cells = <0x1>;
  272. phandle = <0x3>;
  273. };
  274.  
  275. rotate@20000 {
  276. compatible = "allwinner,sun50i-a64-de2-rotate", "allwinner,sun8i-a83t-de2-rotate";
  277. reg = <0x20000 0x10000>;
  278. interrupts = <0x0 0x60 0x4>;
  279. clocks = <0x3 0x9 0x3 0xa>;
  280. clock-names = "bus", "mod";
  281. resets = <0x3 0x3>;
  282. phandle = <0x59>;
  283. };
  284.  
  285. mixer@100000 {
  286. compatible = "allwinner,sun50i-a64-de2-mixer-0";
  287. reg = <0x100000 0x100000>;
  288. clocks = <0x3 0x0 0x3 0x6>;
  289. clock-names = "bus", "mod";
  290. resets = <0x3 0x0>;
  291. phandle = <0x8>;
  292.  
  293. ports {
  294. #address-cells = <0x1>;
  295. #size-cells = <0x0>;
  296.  
  297. port@1 {
  298. #address-cells = <0x1>;
  299. #size-cells = <0x0>;
  300. reg = <0x1>;
  301. phandle = <0x5a>;
  302.  
  303. endpoint@0 {
  304. reg = <0x0>;
  305. remote-endpoint = <0x18>;
  306. phandle = <0x1c>;
  307. };
  308.  
  309. endpoint@1 {
  310. reg = <0x1>;
  311. remote-endpoint = <0x19>;
  312. phandle = <0x1f>;
  313. };
  314. };
  315. };
  316. };
  317.  
  318. mixer@200000 {
  319. compatible = "allwinner,sun50i-a64-de2-mixer-1";
  320. reg = <0x200000 0x100000>;
  321. clocks = <0x3 0x1 0x3 0x7>;
  322. clock-names = "bus", "mod";
  323. resets = <0x3 0x1>;
  324. phandle = <0x9>;
  325.  
  326. ports {
  327. #address-cells = <0x1>;
  328. #size-cells = <0x0>;
  329.  
  330. port@1 {
  331. #address-cells = <0x1>;
  332. #size-cells = <0x0>;
  333. reg = <0x1>;
  334. phandle = <0x5b>;
  335.  
  336. endpoint@0 {
  337. reg = <0x0>;
  338. remote-endpoint = <0x1a>;
  339. phandle = <0x1d>;
  340. };
  341.  
  342. endpoint@1 {
  343. reg = <0x1>;
  344. remote-endpoint = <0x1b>;
  345. phandle = <0x20>;
  346. };
  347. };
  348. };
  349. };
  350. };
  351.  
  352. syscon@1c00000 {
  353. compatible = "allwinner,sun50i-a64-system-control";
  354. reg = <0x1c00000 0x1000>;
  355. #address-cells = <0x1>;
  356. #size-cells = <0x1>;
  357. ranges;
  358. phandle = <0x3c>;
  359.  
  360. sram@18000 {
  361. compatible = "mmio-sram";
  362. reg = <0x18000 0x28000>;
  363. #address-cells = <0x1>;
  364. #size-cells = <0x1>;
  365. ranges = <0x0 0x18000 0x28000>;
  366. phandle = <0x5c>;
  367.  
  368. sram-section@0 {
  369. compatible = "allwinner,sun50i-a64-sram-c";
  370. reg = <0x0 0x28000>;
  371. phandle = <0x17>;
  372. };
  373. };
  374.  
  375. sram@1d00000 {
  376. compatible = "mmio-sram";
  377. reg = <0x1d00000 0x40000>;
  378. #address-cells = <0x1>;
  379. #size-cells = <0x1>;
  380. ranges = <0x0 0x1d00000 0x40000>;
  381. phandle = <0x5d>;
  382.  
  383. sram-section@0 {
  384. compatible = "allwinner,sun50i-a64-sram-c1", "allwinner,sun4i-a10-sram-c1";
  385. reg = <0x0 0x40000>;
  386. phandle = <0x22>;
  387. };
  388. };
  389. };
  390.  
  391. dma-controller@1c02000 {
  392. compatible = "allwinner,sun50i-a64-dma";
  393. reg = <0x1c02000 0x1000>;
  394. interrupts = <0x0 0x32 0x4>;
  395. clocks = <0x2 0x1e>;
  396. dma-channels = <0x8>;
  397. dma-requests = <0x1b>;
  398. resets = <0x2 0x7>;
  399. #dma-cells = <0x1>;
  400. phandle = <0x2d>;
  401. };
  402.  
  403. lcd-controller@1c0c000 {
  404. compatible = "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd";
  405. reg = <0x1c0c000 0x1000>;
  406. interrupts = <0x0 0x56 0x4>;
  407. clocks = <0x2 0x2f 0x2 0x64>;
  408. clock-names = "ahb", "tcon-ch0";
  409. clock-output-names = "tcon-pixel-clock";
  410. #clock-cells = <0x0>;
  411. resets = <0x2 0x18 0x2 0x23>;
  412. reset-names = "lcd", "lvds";
  413. phandle = <0x5e>;
  414.  
  415. ports {
  416. #address-cells = <0x1>;
  417. #size-cells = <0x0>;
  418.  
  419. port@0 {
  420. #address-cells = <0x1>;
  421. #size-cells = <0x0>;
  422. reg = <0x0>;
  423. phandle = <0x5f>;
  424.  
  425. endpoint@0 {
  426. reg = <0x0>;
  427. remote-endpoint = <0x1c>;
  428. phandle = <0x18>;
  429. };
  430.  
  431. endpoint@1 {
  432. reg = <0x1>;
  433. remote-endpoint = <0x1d>;
  434. phandle = <0x1a>;
  435. };
  436. };
  437.  
  438. port@1 {
  439. #address-cells = <0x1>;
  440. #size-cells = <0x0>;
  441. reg = <0x1>;
  442. phandle = <0x60>;
  443.  
  444. endpoint@1 {
  445. reg = <0x1>;
  446. remote-endpoint = <0x1e>;
  447. allwinner,tcon-channel = <0x1>;
  448. phandle = <0x43>;
  449. };
  450. };
  451. };
  452. };
  453.  
  454. lcd-controller@1c0d000 {
  455. compatible = "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv";
  456. reg = <0x1c0d000 0x1000>;
  457. interrupts = <0x0 0x57 0x4>;
  458. clocks = <0x2 0x30 0x2 0x65>;
  459. clock-names = "ahb", "tcon-ch1";
  460. resets = <0x2 0x19>;
  461. reset-names = "lcd";
  462. phandle = <0x61>;
  463.  
  464. ports {
  465. #address-cells = <0x1>;
  466. #size-cells = <0x0>;
  467.  
  468. port@0 {
  469. #address-cells = <0x1>;
  470. #size-cells = <0x0>;
  471. reg = <0x0>;
  472. phandle = <0x62>;
  473.  
  474. endpoint@0 {
  475. reg = <0x0>;
  476. remote-endpoint = <0x1f>;
  477. phandle = <0x19>;
  478. };
  479.  
  480. endpoint@1 {
  481. reg = <0x1>;
  482. remote-endpoint = <0x20>;
  483. phandle = <0x1b>;
  484. };
  485. };
  486.  
  487. port@1 {
  488. #address-cells = <0x1>;
  489. #size-cells = <0x0>;
  490. reg = <0x1>;
  491. phandle = <0x63>;
  492.  
  493. endpoint@1 {
  494. reg = <0x1>;
  495. remote-endpoint = <0x21>;
  496. phandle = <0x45>;
  497. };
  498. };
  499. };
  500. };
  501.  
  502. video-codec@1c0e000 {
  503. compatible = "allwinner,sun50i-a64-video-engine";
  504. reg = <0x1c0e000 0x1000>;
  505. clocks = <0x2 0x2e 0x2 0x6a 0x2 0x5f>;
  506. clock-names = "ahb", "mod", "ram";
  507. resets = <0x2 0x17>;
  508. interrupts = <0x0 0x3a 0x4>;
  509. allwinner,sram = <0x22 0x1>;
  510. };
  511.  
  512. mmc@1c0f000 {
  513. compatible = "allwinner,sun50i-a64-mmc";
  514. reg = <0x1c0f000 0x1000>;
  515. clocks = <0x2 0x1f 0x2 0x4b>;
  516. clock-names = "ahb", "mmc";
  517. resets = <0x2 0x8>;
  518. reset-names = "ahb";
  519. interrupts = <0x0 0x3c 0x4>;
  520. max-frequency = <0x8f0d180>;
  521. status = "okay";
  522. bus-width = <0x4>;
  523. #address-cells = <0x1>;
  524. #size-cells = <0x0>;
  525. pinctrl-names = "default";
  526. pinctrl-0 = <0x23>;
  527. vmmc-supply = <0x24>;
  528. cd-gpios = <0x25 0x5 0x6 0x1>;
  529. disable-wp;
  530. phandle = <0x64>;
  531. };
  532.  
  533. mmc@1c10000 {
  534. compatible = "allwinner,sun50i-a64-mmc";
  535. reg = <0x1c10000 0x1000>;
  536. clocks = <0x2 0x20 0x2 0x4c>;
  537. clock-names = "ahb", "mmc";
  538. resets = <0x2 0x9>;
  539. reset-names = "ahb";
  540. interrupts = <0x0 0x3d 0x4>;
  541. max-frequency = <0x8f0d180>;
  542. status = "okay";
  543. #address-cells = <0x1>;
  544. #size-cells = <0x0>;
  545. pinctrl-names = "default";
  546. pinctrl-0 = <0x26>;
  547. vmmc-supply = <0x27>;
  548. vqmmc-supply = <0x28>;
  549. mmc-pwrseq = <0x29>;
  550. non-removable;
  551. bus-width = <0x4>;
  552. phandle = <0x65>;
  553. };
  554.  
  555. mmc@1c11000 {
  556. compatible = "allwinner,sun50i-a64-emmc";
  557. reg = <0x1c11000 0x1000>;
  558. clocks = <0x2 0x21 0x2 0x4d>;
  559. clock-names = "ahb", "mmc";
  560. resets = <0x2 0xa>;
  561. reset-names = "ahb";
  562. interrupts = <0x0 0x3e 0x4>;
  563. max-frequency = <0xbebc200>;
  564. status = "disabled";
  565. #address-cells = <0x1>;
  566. #size-cells = <0x0>;
  567. phandle = <0x66>;
  568. };
  569.  
  570. eeprom@1c14000 {
  571. compatible = "allwinner,sun50i-a64-sid";
  572. reg = <0x1c14000 0x400>;
  573. #address-cells = <0x1>;
  574. #size-cells = <0x1>;
  575. phandle = <0x67>;
  576.  
  577. thermal-sensor-calibration@34 {
  578. reg = <0x34 0x8>;
  579. phandle = <0x2f>;
  580. };
  581. };
  582.  
  583. crypto@1c15000 {
  584. compatible = "allwinner,sun50i-a64-crypto";
  585. reg = <0x1c15000 0x1000>;
  586. interrupts = <0x0 0x5e 0x4>;
  587. clocks = <0x2 0x1d 0x2 0x4f>;
  588. clock-names = "bus", "mod";
  589. resets = <0x2 0x6>;
  590. phandle = <0x68>;
  591. };
  592.  
  593. usb@1c19000 {
  594. compatible = "allwinner,sun8i-a33-musb";
  595. reg = <0x1c19000 0x400>;
  596. clocks = <0x2 0x29>;
  597. resets = <0x2 0x12>;
  598. interrupts = <0x0 0x47 0x4>;
  599. interrupt-names = "mc";
  600. phys = <0x2a 0x0>;
  601. phy-names = "usb";
  602. extcon = <0x2a 0x0>;
  603. dr_mode = "host";
  604. status = "okay";
  605. phandle = <0x69>;
  606. };
  607.  
  608. phy@1c19400 {
  609. compatible = "allwinner,sun50i-a64-usb-phy";
  610. reg = <0x1c19400 0x14 0x1c1a800 0x4 0x1c1b800 0x4>;
  611. reg-names = "phy_ctrl", "pmu0", "pmu1";
  612. clocks = <0x2 0x56 0x2 0x57>;
  613. clock-names = "usb0_phy", "usb1_phy";
  614. resets = <0x2 0x0 0x2 0x1>;
  615. reset-names = "usb0_reset", "usb1_reset";
  616. status = "okay";
  617. #phy-cells = <0x1>;
  618. phandle = <0x2a>;
  619. };
  620.  
  621. usb@1c1a000 {
  622. compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
  623. reg = <0x1c1a000 0x100>;
  624. interrupts = <0x0 0x48 0x4>;
  625. clocks = <0x2 0x2c 0x2 0x2a 0x2 0x5b>;
  626. resets = <0x2 0x15 0x2 0x13>;
  627. status = "okay";
  628. phandle = <0x6a>;
  629. };
  630.  
  631. usb@1c1a400 {
  632. compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
  633. reg = <0x1c1a400 0x100>;
  634. interrupts = <0x0 0x49 0x4>;
  635. clocks = <0x2 0x2c 0x2 0x5b>;
  636. resets = <0x2 0x15>;
  637. status = "okay";
  638. phandle = <0x6b>;
  639. };
  640.  
  641. usb@1c1b000 {
  642. compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
  643. reg = <0x1c1b000 0x100>;
  644. interrupts = <0x0 0x4a 0x4>;
  645. clocks = <0x2 0x2d 0x2 0x2b 0x2 0x5d>;
  646. resets = <0x2 0x16 0x2 0x14>;
  647. phys = <0x2a 0x1>;
  648. phy-names = "usb";
  649. status = "okay";
  650. phandle = <0x6c>;
  651. };
  652.  
  653. usb@1c1b400 {
  654. compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
  655. reg = <0x1c1b400 0x100>;
  656. interrupts = <0x0 0x4b 0x4>;
  657. clocks = <0x2 0x2d 0x2 0x5d>;
  658. resets = <0x2 0x16>;
  659. phys = <0x2a 0x1>;
  660. phy-names = "usb";
  661. status = "okay";
  662. phandle = <0x6d>;
  663. };
  664.  
  665. clock@1c20000 {
  666. compatible = "allwinner,sun50i-a64-ccu";
  667. reg = <0x1c20000 0x400>;
  668. clocks = <0x2b 0x2c 0x0>;
  669. clock-names = "hosc", "losc";
  670. #clock-cells = <0x1>;
  671. #reset-cells = <0x1>;
  672. phandle = <0x2>;
  673. };
  674.  
  675. pinctrl@1c20800 {
  676. compatible = "allwinner,sun50i-a64-pinctrl";
  677. reg = <0x1c20800 0x400>;
  678. interrupts = <0x0 0xb 0x4 0x0 0x11 0x4 0x0 0x15 0x4>;
  679. clocks = <0x2 0x3a 0x2b 0x2c 0x0>;
  680. clock-names = "apb", "hosc", "losc";
  681. gpio-controller;
  682. #gpio-cells = <0x3>;
  683. interrupt-controller;
  684. #interrupt-cells = <0x3>;
  685. phandle = <0x25>;
  686.  
  687. aif2-pins {
  688. pins = "PB4", "PB5", "PB6", "PB7";
  689. function = "aif2";
  690. phandle = <0x6e>;
  691. };
  692.  
  693. aif3-pins {
  694. pins = "PG10", "PG11", "PG12", "PG13";
  695. function = "aif3";
  696. phandle = <0x6f>;
  697. };
  698.  
  699. csi-pins {
  700. pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
  701. function = "csi";
  702. phandle = <0x41>;
  703. };
  704.  
  705. csi-mclk-pin {
  706. pins = "PE1";
  707. function = "csi";
  708. phandle = <0x70>;
  709. };
  710.  
  711. i2c0-pins {
  712. pins = "PH0", "PH1";
  713. function = "i2c0";
  714. phandle = <0x37>;
  715. };
  716.  
  717. i2c1-pins {
  718. pins = "PH2", "PH3";
  719. function = "i2c1";
  720. bias-pull-up;
  721. phandle = <0x38>;
  722. };
  723.  
  724. i2c2-pins {
  725. pins = "PE14", "PE15";
  726. function = "i2c2";
  727. phandle = <0x39>;
  728. };
  729.  
  730. lcd-rgb666-pins {
  731. pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21";
  732. function = "lcd0";
  733. phandle = <0x71>;
  734. };
  735.  
  736. mmc0-pins {
  737. pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  738. function = "mmc0";
  739. drive-strength = <0x1e>;
  740. bias-pull-up;
  741. phandle = <0x23>;
  742. };
  743.  
  744. mmc1-pins {
  745. pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  746. function = "mmc1";
  747. drive-strength = <0x1e>;
  748. bias-pull-up;
  749. phandle = <0x26>;
  750. };
  751.  
  752. mmc2-pins {
  753. pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  754. function = "mmc2";
  755. drive-strength = <0x1e>;
  756. bias-pull-up;
  757. phandle = <0x72>;
  758. };
  759.  
  760. mmc2-ds-pin {
  761. pins = "PC1";
  762. function = "mmc2";
  763. drive-strength = <0x1e>;
  764. bias-pull-up;
  765. phandle = <0x73>;
  766. };
  767.  
  768. pwm-pin {
  769. pins = "PD22";
  770. function = "pwm";
  771. phandle = <0x40>;
  772. };
  773.  
  774. rmii-pins {
  775. pins = "PD10", "PD11", "PD13", "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23";
  776. function = "emac";
  777. drive-strength = <0x28>;
  778. phandle = <0x74>;
  779. };
  780.  
  781. rgmii-pins {
  782. pins = "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23";
  783. function = "emac";
  784. drive-strength = <0x28>;
  785. phandle = <0x3d>;
  786. };
  787.  
  788. spdif-tx-pin {
  789. pins = "PH8";
  790. function = "spdif";
  791. phandle = <0x2e>;
  792. };
  793.  
  794. spi0-pins {
  795. pins = "PC0", "PC1", "PC2", "PC3";
  796. function = "spi0";
  797. phandle = <0x3a>;
  798. };
  799.  
  800. spi1-pins {
  801. pins = "PD0", "PD1", "PD2", "PD3";
  802. function = "spi1";
  803. phandle = <0x3b>;
  804. };
  805.  
  806. uart0-pb-pins {
  807. pins = "PB8", "PB9";
  808. function = "uart0";
  809. phandle = <0x30>;
  810. };
  811.  
  812. uart1-pins {
  813. pins = "PG6", "PG7";
  814. function = "uart1";
  815. phandle = <0x31>;
  816. };
  817.  
  818. uart1-rts-cts-pins {
  819. pins = "PG8", "PG9";
  820. function = "uart1";
  821. phandle = <0x32>;
  822. };
  823.  
  824. uart2-pins {
  825. pins = "PB0", "PB1";
  826. function = "uart2";
  827. phandle = <0x34>;
  828. };
  829.  
  830. uart3-pins {
  831. pins = "PD0", "PD1";
  832. function = "uart3";
  833. phandle = <0x35>;
  834. };
  835.  
  836. uart4-pins {
  837. pins = "PD2", "PD3";
  838. function = "uart4";
  839. phandle = <0x36>;
  840. };
  841.  
  842. uart4-rts-cts-pins {
  843. pins = "PD4", "PD5";
  844. function = "uart4";
  845. phandle = <0x75>;
  846. };
  847. };
  848.  
  849. spdif@1c21000 {
  850. #sound-dai-cells = <0x0>;
  851. compatible = "allwinner,sun50i-a64-spdif", "allwinner,sun8i-h3-spdif";
  852. reg = <0x1c21000 0x400>;
  853. interrupts = <0x0 0xc 0x4>;
  854. clocks = <0x2 0x39 0x2 0x55>;
  855. resets = <0x2 0x25>;
  856. clock-names = "apb", "spdif";
  857. dmas = <0x2d 0x2>;
  858. dma-names = "tx";
  859. pinctrl-names = "default";
  860. pinctrl-0 = <0x2e>;
  861. status = "disabled";
  862. phandle = <0x12>;
  863. };
  864.  
  865. lradc@1c21800 {
  866. compatible = "allwinner,sun50i-a64-lradc", "allwinner,sun4i-a10-lradc-keys";
  867. reg = <0x1c21800 0x400>;
  868. interrupts = <0x0 0x1e 0x4>;
  869. status = "disabled";
  870. phandle = <0x76>;
  871. };
  872.  
  873. i2s@1c22000 {
  874. #sound-dai-cells = <0x0>;
  875. compatible = "allwinner,sun50i-a64-i2s", "allwinner,sun8i-h3-i2s";
  876. reg = <0x1c22000 0x400>;
  877. interrupts = <0x0 0xd 0x4>;
  878. clocks = <0x2 0x3c 0x2 0x52>;
  879. clock-names = "apb", "mod";
  880. resets = <0x2 0x27>;
  881. dma-names = "rx", "tx";
  882. dmas = <0x2d 0x3 0x2d 0x3>;
  883. status = "disabled";
  884. phandle = <0x77>;
  885. };
  886.  
  887. i2s@1c22400 {
  888. #sound-dai-cells = <0x0>;
  889. compatible = "allwinner,sun50i-a64-i2s", "allwinner,sun8i-h3-i2s";
  890. reg = <0x1c22400 0x400>;
  891. interrupts = <0x0 0xe 0x4>;
  892. clocks = <0x2 0x3d 0x2 0x53>;
  893. clock-names = "apb", "mod";
  894. resets = <0x2 0x28>;
  895. dma-names = "rx", "tx";
  896. dmas = <0x2d 0x4 0x2d 0x4>;
  897. status = "disabled";
  898. phandle = <0x78>;
  899. };
  900.  
  901. dai@1c22c00 {
  902. #sound-dai-cells = <0x0>;
  903. compatible = "allwinner,sun50i-a64-codec-i2s";
  904. reg = <0x1c22c00 0x200>;
  905. interrupts = <0x0 0x1d 0x4>;
  906. clocks = <0x2 0x38 0x2 0x6b>;
  907. clock-names = "apb", "mod";
  908. resets = <0x2 0x24>;
  909. dmas = <0x2d 0xf 0x2d 0xf>;
  910. dma-names = "rx", "tx";
  911. status = "okay";
  912. phandle = <0x10>;
  913. };
  914.  
  915. codec@1c22e00 {
  916. #sound-dai-cells = <0x1>;
  917. compatible = "allwinner,sun50i-a64-codec";
  918. reg = <0x1c22e00 0x600>;
  919. interrupts = <0x0 0x1c 0x4>;
  920. clocks = <0x2 0x38 0x2 0x6b>;
  921. clock-names = "bus", "mod";
  922. status = "okay";
  923. phandle = <0x11>;
  924. };
  925.  
  926. thermal-sensor@1c25000 {
  927. compatible = "allwinner,sun50i-a64-ths";
  928. reg = <0x1c25000 0x100>;
  929. clocks = <0x2 0x3b 0x2 0x49>;
  930. clock-names = "bus", "mod";
  931. interrupts = <0x0 0x1f 0x4>;
  932. resets = <0x2 0x26>;
  933. nvmem-cells = <0x2f>;
  934. nvmem-cell-names = "calibration";
  935. #thermal-sensor-cells = <0x1>;
  936. phandle = <0x14>;
  937. };
  938.  
  939. serial@1c28000 {
  940. compatible = "snps,dw-apb-uart";
  941. reg = <0x1c28000 0x400>;
  942. interrupts = <0x0 0x0 0x4>;
  943. reg-shift = <0x2>;
  944. reg-io-width = <0x4>;
  945. fifo-size = <0x40>;
  946. clocks = <0x2 0x43>;
  947. resets = <0x2 0x2e>;
  948. status = "okay";
  949. pinctrl-names = "default";
  950. pinctrl-0 = <0x30>;
  951. phandle = <0x79>;
  952. };
  953.  
  954. serial@1c28400 {
  955. compatible = "snps,dw-apb-uart";
  956. reg = <0x1c28400 0x400>;
  957. interrupts = <0x0 0x1 0x4>;
  958. reg-shift = <0x2>;
  959. reg-io-width = <0x4>;
  960. fifo-size = <0x40>;
  961. clocks = <0x2 0x44>;
  962. resets = <0x2 0x2f>;
  963. status = "okay";
  964. pinctrl-names = "default";
  965. pinctrl-0 = <0x31 0x32>;
  966. phandle = <0x7a>;
  967.  
  968. bluetooth {
  969. compatible = "realtek,rtl8723bs-bt";
  970. reset-gpios = <0x33 0x0 0x4 0x1>;
  971. device-wake-gpios = <0x33 0x0 0x5 0x0>;
  972. host-wake-gpios = <0x33 0x0 0x6 0x0>;
  973. firmware-postfix = "pine64";
  974. };
  975. };
  976.  
  977. serial@1c28800 {
  978. compatible = "snps,dw-apb-uart";
  979. reg = <0x1c28800 0x400>;
  980. interrupts = <0x0 0x2 0x4>;
  981. reg-shift = <0x2>;
  982. reg-io-width = <0x4>;
  983. fifo-size = <0x40>;
  984. clocks = <0x2 0x45>;
  985. resets = <0x2 0x30>;
  986. status = "disabled";
  987. pinctrl-names = "default";
  988. pinctrl-0 = <0x34>;
  989. phandle = <0x7b>;
  990. };
  991.  
  992. serial@1c28c00 {
  993. compatible = "snps,dw-apb-uart";
  994. reg = <0x1c28c00 0x400>;
  995. interrupts = <0x0 0x3 0x4>;
  996. reg-shift = <0x2>;
  997. reg-io-width = <0x4>;
  998. fifo-size = <0x40>;
  999. clocks = <0x2 0x46>;
  1000. resets = <0x2 0x31>;
  1001. status = "disabled";
  1002. pinctrl-names = "default";
  1003. pinctrl-0 = <0x35>;
  1004. phandle = <0x7c>;
  1005. };
  1006.  
  1007. serial@1c29000 {
  1008. compatible = "snps,dw-apb-uart";
  1009. reg = <0x1c29000 0x400>;
  1010. interrupts = <0x0 0x4 0x4>;
  1011. reg-shift = <0x2>;
  1012. reg-io-width = <0x4>;
  1013. fifo-size = <0x40>;
  1014. clocks = <0x2 0x47>;
  1015. resets = <0x2 0x32>;
  1016. status = "disabled";
  1017. pinctrl-names = "default";
  1018. pinctrl-0 = <0x36>;
  1019. phandle = <0x7d>;
  1020. };
  1021.  
  1022. i2c@1c2ac00 {
  1023. compatible = "allwinner,sun6i-a31-i2c";
  1024. reg = <0x1c2ac00 0x400>;
  1025. interrupts = <0x0 0x6 0x4>;
  1026. clocks = <0x2 0x3f>;
  1027. resets = <0x2 0x2a>;
  1028. pinctrl-names = "default";
  1029. pinctrl-0 = <0x37>;
  1030. status = "disabled";
  1031. #address-cells = <0x1>;
  1032. #size-cells = <0x0>;
  1033. phandle = <0x7e>;
  1034. };
  1035.  
  1036. i2c@1c2b000 {
  1037. compatible = "allwinner,sun6i-a31-i2c";
  1038. reg = <0x1c2b000 0x400>;
  1039. interrupts = <0x0 0x7 0x4>;
  1040. clocks = <0x2 0x40>;
  1041. resets = <0x2 0x2b>;
  1042. pinctrl-names = "default";
  1043. pinctrl-0 = <0x38>;
  1044. status = "okay";
  1045. #address-cells = <0x1>;
  1046. #size-cells = <0x0>;
  1047. phandle = <0x7f>;
  1048. };
  1049.  
  1050. i2c@1c2b400 {
  1051. compatible = "allwinner,sun6i-a31-i2c";
  1052. reg = <0x1c2b400 0x400>;
  1053. interrupts = <0x0 0x8 0x4>;
  1054. clocks = <0x2 0x41>;
  1055. resets = <0x2 0x2c>;
  1056. pinctrl-names = "default";
  1057. pinctrl-0 = <0x39>;
  1058. status = "disabled";
  1059. #address-cells = <0x1>;
  1060. #size-cells = <0x0>;
  1061. phandle = <0x80>;
  1062. };
  1063.  
  1064. spi@1c68000 {
  1065. compatible = "allwinner,sun8i-h3-spi";
  1066. reg = <0x1c68000 0x1000>;
  1067. interrupts = <0x0 0x41 0x4>;
  1068. clocks = <0x2 0x27 0x2 0x50>;
  1069. clock-names = "ahb", "mod";
  1070. dmas = <0x2d 0x17 0x2d 0x17>;
  1071. dma-names = "rx", "tx";
  1072. pinctrl-names = "default";
  1073. pinctrl-0 = <0x3a>;
  1074. resets = <0x2 0x10>;
  1075. status = "okay";
  1076. num-cs = <0x1>;
  1077. #address-cells = <0x1>;
  1078. #size-cells = <0x0>;
  1079. phandle = <0x81>;
  1080.  
  1081. spi-flash@0 {
  1082. #address-cells = <0x1>;
  1083. #size-cells = <0x0>;
  1084. compatible = "jedec,spi-nor";
  1085. reg = <0x0>;
  1086. spi-max-frequency = <0x989680>;
  1087. status = "disabled";
  1088.  
  1089. partitions {
  1090. compatible = "fixed-partitions";
  1091. #address-cells = <0x1>;
  1092. #size-cells = <0x1>;
  1093.  
  1094. partition@0 {
  1095. label = "uboot";
  1096. reg = <0x0 0x100000>;
  1097. };
  1098.  
  1099. partition@100000 {
  1100. label = "env";
  1101. reg = <0x100000 0x100000>;
  1102. };
  1103.  
  1104. partition@200000 {
  1105. label = "data";
  1106. reg = <0x200000 0x200000>;
  1107. };
  1108. };
  1109. };
  1110. };
  1111.  
  1112. spi@1c69000 {
  1113. compatible = "allwinner,sun8i-h3-spi";
  1114. reg = <0x1c69000 0x1000>;
  1115. interrupts = <0x0 0x42 0x4>;
  1116. clocks = <0x2 0x28 0x2 0x51>;
  1117. clock-names = "ahb", "mod";
  1118. dmas = <0x2d 0x18 0x2d 0x18>;
  1119. dma-names = "rx", "tx";
  1120. pinctrl-names = "default";
  1121. pinctrl-0 = <0x3b>;
  1122. resets = <0x2 0x11>;
  1123. status = "disabled";
  1124. num-cs = <0x1>;
  1125. #address-cells = <0x1>;
  1126. #size-cells = <0x0>;
  1127. phandle = <0x82>;
  1128. };
  1129.  
  1130. ethernet@1c30000 {
  1131. compatible = "allwinner,sun50i-a64-emac";
  1132. syscon = <0x3c>;
  1133. reg = <0x1c30000 0x10000>;
  1134. interrupts = <0x0 0x52 0x4>;
  1135. interrupt-names = "macirq";
  1136. resets = <0x2 0xd>;
  1137. reset-names = "stmmaceth";
  1138. clocks = <0x2 0x24>;
  1139. clock-names = "stmmaceth";
  1140. status = "okay";
  1141. pinctrl-names = "default";
  1142. pinctrl-0 = <0x3d>;
  1143. phy-mode = "rgmii-txid";
  1144. phy-handle = <0x3e>;
  1145. phy-supply = <0x3f>;
  1146. phandle = <0x83>;
  1147.  
  1148. mdio {
  1149. compatible = "snps,dwmac-mdio";
  1150. #address-cells = <0x1>;
  1151. #size-cells = <0x0>;
  1152. phandle = <0x84>;
  1153.  
  1154. ethernet-phy@1 {
  1155. compatible = "ethernet-phy-ieee802.3-c22";
  1156. reg = <0x1>;
  1157. phandle = <0x3e>;
  1158. };
  1159. };
  1160. };
  1161.  
  1162. gpu@1c40000 {
  1163. compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
  1164. reg = <0x1c40000 0x10000>;
  1165. interrupts = <0x0 0x61 0x4 0x0 0x62 0x4 0x0 0x63 0x4 0x0 0x64 0x4 0x0 0x66 0x4 0x0 0x67 0x4 0x0 0x65 0x4>;
  1166. interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1", "pmu";
  1167. clocks = <0x2 0x35 0x2 0x72>;
  1168. clock-names = "bus", "core";
  1169. resets = <0x2 0x1f>;
  1170. phandle = <0x85>;
  1171. };
  1172.  
  1173. interrupt-controller@1c81000 {
  1174. compatible = "arm,gic-400";
  1175. reg = <0x1c81000 0x1000 0x1c82000 0x2000 0x1c84000 0x2000 0x1c86000 0x2000>;
  1176. interrupts = <0x1 0x9 0xf04>;
  1177. interrupt-controller;
  1178. #interrupt-cells = <0x3>;
  1179. phandle = <0x1>;
  1180. };
  1181.  
  1182. pwm@1c21400 {
  1183. compatible = "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm";
  1184. reg = <0x1c21400 0x400>;
  1185. clocks = <0x2b>;
  1186. pinctrl-names = "default";
  1187. pinctrl-0 = <0x40>;
  1188. #pwm-cells = <0x3>;
  1189. status = "disabled";
  1190. phandle = <0x86>;
  1191. };
  1192.  
  1193. csi@1cb0000 {
  1194. compatible = "allwinner,sun50i-a64-csi";
  1195. reg = <0x1cb0000 0x1000>;
  1196. interrupts = <0x0 0x54 0x4>;
  1197. clocks = <0x2 0x32 0x2 0x68 0x2 0x60>;
  1198. clock-names = "bus", "mod", "ram";
  1199. resets = <0x2 0x1b>;
  1200. pinctrl-names = "default";
  1201. pinctrl-0 = <0x41>;
  1202. status = "disabled";
  1203. phandle = <0x87>;
  1204. };
  1205.  
  1206. dsi@1ca0000 {
  1207. compatible = "allwinner,sun50i-a64-mipi-dsi";
  1208. reg = <0x1ca0000 0x1000>;
  1209. interrupts = <0x0 0x59 0x4>;
  1210. clocks = <0x2 0x1c>;
  1211. resets = <0x2 0x5>;
  1212. phys = <0x42>;
  1213. phy-names = "dphy";
  1214. status = "disabled";
  1215. #address-cells = <0x1>;
  1216. #size-cells = <0x0>;
  1217. phandle = <0x88>;
  1218.  
  1219. port {
  1220.  
  1221. endpoint {
  1222. remote-endpoint = <0x43>;
  1223. phandle = <0x1e>;
  1224. };
  1225. };
  1226. };
  1227.  
  1228. d-phy@1ca1000 {
  1229. compatible = "allwinner,sun50i-a64-mipi-dphy", "allwinner,sun6i-a31-mipi-dphy";
  1230. reg = <0x1ca1000 0x1000>;
  1231. clocks = <0x2 0x1c 0x2 0x71>;
  1232. clock-names = "bus", "mod";
  1233. resets = <0x2 0x5>;
  1234. status = "disabled";
  1235. #phy-cells = <0x0>;
  1236. phandle = <0x42>;
  1237. };
  1238.  
  1239. hdmi@1ee0000 {
  1240. #sound-dai-cells = <0x0>;
  1241. compatible = "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi";
  1242. reg = <0x1ee0000 0x10000>;
  1243. reg-io-width = <0x1>;
  1244. interrupts = <0x0 0x58 0x4>;
  1245. clocks = <0x2 0x33 0x2 0x6f 0x2 0x6e>;
  1246. clock-names = "iahb", "isfr", "tmds";
  1247. resets = <0x2 0x1d>;
  1248. reset-names = "ctrl";
  1249. phys = <0x44>;
  1250. phy-names = "phy";
  1251. status = "okay";
  1252. hvcc-supply = <0x4>;
  1253. phandle = <0x47>;
  1254.  
  1255. ports {
  1256. #address-cells = <0x1>;
  1257. #size-cells = <0x0>;
  1258.  
  1259. port@0 {
  1260. reg = <0x0>;
  1261. phandle = <0x89>;
  1262.  
  1263. endpoint {
  1264. remote-endpoint = <0x45>;
  1265. phandle = <0x21>;
  1266. };
  1267. };
  1268.  
  1269. port@1 {
  1270. reg = <0x1>;
  1271. phandle = <0x8a>;
  1272.  
  1273. endpoint {
  1274. remote-endpoint = <0x46>;
  1275. phandle = <0x4f>;
  1276. };
  1277. };
  1278. };
  1279. };
  1280.  
  1281. hdmi-phy@1ef0000 {
  1282. compatible = "allwinner,sun50i-a64-hdmi-phy";
  1283. reg = <0x1ef0000 0x10000>;
  1284. clocks = <0x2 0x33 0x2 0x6f 0x2 0x7>;
  1285. clock-names = "bus", "mod", "pll-0";
  1286. resets = <0x2 0x1c>;
  1287. reset-names = "phy";
  1288. #phy-cells = <0x0>;
  1289. phandle = <0x44>;
  1290. };
  1291.  
  1292. i2s@1c22800 {
  1293. #sound-dai-cells = <0x0>;
  1294. compatible = "allwinner,sun8i-h3-i2s";
  1295. reg = <0x1c22800 0x400>;
  1296. interrupts = <0x0 0xf 0x4>;
  1297. clocks = <0x2 0x3e 0x2 0x54>;
  1298. clock-names = "apb", "mod";
  1299. dmas = <0x2d 0x1b>;
  1300. resets = <0x2 0x29>;
  1301. dma-names = "tx";
  1302. status = "okay";
  1303. phandle = <0x48>;
  1304. };
  1305.  
  1306. sound_hdmi {
  1307. compatible = "simple-audio-card";
  1308. simple-audio-card,format = "i2s";
  1309. simple-audio-card,name = "allwinner,hdmi";
  1310. simple-audio-card,mclk-fs = <0x100>;
  1311. status = "okay";
  1312. phandle = <0x8b>;
  1313.  
  1314. simple-audio-card,codec {
  1315. sound-dai = <0x47>;
  1316. };
  1317.  
  1318. simple-audio-card,cpu {
  1319. sound-dai = <0x48>;
  1320. };
  1321. };
  1322.  
  1323. rtc@1f00000 {
  1324. compatible = "allwinner,sun50i-a64-rtc", "allwinner,sun8i-h3-rtc";
  1325. reg = <0x1f00000 0x400>;
  1326. interrupts = <0x0 0x28 0x4 0x0 0x29 0x4>;
  1327. clock-output-names = "osc32k", "osc32k-out", "iosc";
  1328. clocks = <0x49>;
  1329. #clock-cells = <0x1>;
  1330. phandle = <0x2c>;
  1331. };
  1332.  
  1333. interrupt-controller@1f00c00 {
  1334. compatible = "allwinner,sun50i-a64-r-intc", "allwinner,sun6i-a31-r-intc";
  1335. interrupt-controller;
  1336. #interrupt-cells = <0x2>;
  1337. reg = <0x1f00c00 0x400>;
  1338. interrupts = <0x0 0x20 0x4>;
  1339. phandle = <0x4e>;
  1340. };
  1341.  
  1342. clock@1f01400 {
  1343. compatible = "allwinner,sun50i-a64-r-ccu";
  1344. reg = <0x1f01400 0x100>;
  1345. clocks = <0x2b 0x2c 0x0 0x2c 0x2 0x2 0xb>;
  1346. clock-names = "hosc", "losc", "iosc", "pll-periph";
  1347. #clock-cells = <0x1>;
  1348. #reset-cells = <0x1>;
  1349. phandle = <0x4a>;
  1350. };
  1351.  
  1352. codec-analog@1f015c0 {
  1353. compatible = "allwinner,sun50i-a64-codec-analog";
  1354. reg = <0x1f015c0 0x4>;
  1355. status = "okay";
  1356. cpvdd-supply = <0x28>;
  1357. phandle = <0xe>;
  1358. };
  1359.  
  1360. i2c@1f02400 {
  1361. compatible = "allwinner,sun50i-a64-i2c", "allwinner,sun6i-a31-i2c";
  1362. reg = <0x1f02400 0x400>;
  1363. interrupts = <0x0 0x2c 0x4>;
  1364. clocks = <0x4a 0x9>;
  1365. resets = <0x4a 0x5>;
  1366. status = "disabled";
  1367. #address-cells = <0x1>;
  1368. #size-cells = <0x0>;
  1369. phandle = <0x8c>;
  1370. };
  1371.  
  1372. ir@1f02000 {
  1373. compatible = "allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir";
  1374. reg = <0x1f02000 0x400>;
  1375. clocks = <0x4a 0x4 0x4a 0xb>;
  1376. clock-names = "apb", "ir";
  1377. resets = <0x4a 0x0>;
  1378. interrupts = <0x0 0x25 0x4>;
  1379. pinctrl-names = "default";
  1380. pinctrl-0 = <0x4b>;
  1381. status = "disabled";
  1382. phandle = <0x8d>;
  1383. };
  1384.  
  1385. pwm@1f03800 {
  1386. compatible = "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm";
  1387. reg = <0x1f03800 0x400>;
  1388. clocks = <0x2b>;
  1389. pinctrl-names = "default";
  1390. pinctrl-0 = <0x4c>;
  1391. #pwm-cells = <0x3>;
  1392. status = "disabled";
  1393. phandle = <0x8e>;
  1394. };
  1395.  
  1396. pinctrl@1f02c00 {
  1397. compatible = "allwinner,sun50i-a64-r-pinctrl";
  1398. reg = <0x1f02c00 0x400>;
  1399. interrupts = <0x0 0x2d 0x4>;
  1400. clocks = <0x4a 0x3 0x2b 0x49>;
  1401. clock-names = "apb", "hosc", "losc";
  1402. gpio-controller;
  1403. #gpio-cells = <0x3>;
  1404. interrupt-controller;
  1405. #interrupt-cells = <0x3>;
  1406. phandle = <0x33>;
  1407.  
  1408. r-i2c-pl89-pins {
  1409. pins = "PL8", "PL9";
  1410. function = "s_i2c";
  1411. phandle = <0x8f>;
  1412. };
  1413.  
  1414. r-ir-rx-pin {
  1415. pins = "PL11";
  1416. function = "s_cir_rx";
  1417. phandle = <0x4b>;
  1418. };
  1419.  
  1420. r-pwm-pin {
  1421. pins = "PL10";
  1422. function = "s_pwm";
  1423. phandle = <0x4c>;
  1424. };
  1425.  
  1426. r-rsb-pins {
  1427. pins = "PL0", "PL1";
  1428. function = "s_rsb";
  1429. phandle = <0x4d>;
  1430. };
  1431. };
  1432.  
  1433. rsb@1f03400 {
  1434. compatible = "allwinner,sun8i-a23-rsb";
  1435. reg = <0x1f03400 0x400>;
  1436. interrupts = <0x0 0x27 0x4>;
  1437. clocks = <0x4a 0x6>;
  1438. clock-frequency = <0x2dc6c0>;
  1439. resets = <0x4a 0x2>;
  1440. pinctrl-names = "default";
  1441. pinctrl-0 = <0x4d>;
  1442. status = "okay";
  1443. #address-cells = <0x1>;
  1444. #size-cells = <0x0>;
  1445. phandle = <0x90>;
  1446.  
  1447. pmic@3a3 {
  1448. compatible = "x-powers,axp803";
  1449. reg = <0x3a3>;
  1450. interrupt-parent = <0x4e>;
  1451. interrupts = <0x0 0x8>;
  1452. interrupt-controller;
  1453. #interrupt-cells = <0x1>;
  1454. phandle = <0x91>;
  1455.  
  1456. ac-power-supply {
  1457. compatible = "x-powers,axp803-ac-power-supply", "x-powers,axp813-ac-power-supply";
  1458. status = "okay";
  1459. phandle = <0x92>;
  1460. };
  1461.  
  1462. adc {
  1463. compatible = "x-powers,axp803-adc", "x-powers,axp813-adc";
  1464. #io-channel-cells = <0x1>;
  1465. phandle = <0x93>;
  1466. };
  1467.  
  1468. gpio {
  1469. compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio";
  1470. gpio-controller;
  1471. #gpio-cells = <0x2>;
  1472. phandle = <0x94>;
  1473.  
  1474. gpio0-ldo {
  1475. pins = "GPIO0";
  1476. function = "ldo";
  1477. phandle = <0x95>;
  1478. };
  1479.  
  1480. gpio1-ldo {
  1481. pins = "GPIO1";
  1482. function = "ldo";
  1483. phandle = <0x96>;
  1484. };
  1485. };
  1486.  
  1487. battery-power-supply {
  1488. compatible = "x-powers,axp803-battery-power-supply", "x-powers,axp813-battery-power-supply";
  1489. status = "okay";
  1490. phandle = <0x97>;
  1491. };
  1492.  
  1493. regulators {
  1494. x-powers,dcdc-freq = <0xbb8>;
  1495.  
  1496. aldo1 {
  1497. regulator-name = "aldo1";
  1498. phandle = <0x98>;
  1499. };
  1500.  
  1501. aldo2 {
  1502. regulator-name = "vcc-pl";
  1503. regulator-always-on;
  1504. regulator-min-microvolt = <0x1b7740>;
  1505. regulator-max-microvolt = <0x325aa0>;
  1506. phandle = <0x99>;
  1507. };
  1508.  
  1509. aldo3 {
  1510. regulator-name = "vcc-pll-avcc";
  1511. regulator-always-on;
  1512. regulator-min-microvolt = <0x2dc6c0>;
  1513. regulator-max-microvolt = <0x2dc6c0>;
  1514. phandle = <0x9a>;
  1515. };
  1516.  
  1517. dc1sw {
  1518. regulator-name = "vcc-phy";
  1519. regulator-enable-ramp-delay = <0x186a0>;
  1520. phandle = <0x3f>;
  1521. };
  1522.  
  1523. dcdc1 {
  1524. regulator-name = "vcc-3v3";
  1525. regulator-always-on;
  1526. regulator-min-microvolt = <0x325aa0>;
  1527. regulator-max-microvolt = <0x325aa0>;
  1528. phandle = <0x24>;
  1529. };
  1530.  
  1531. dcdc2 {
  1532. regulator-name = "vdd-cpux";
  1533. regulator-always-on;
  1534. regulator-min-microvolt = <0xfde80>;
  1535. regulator-max-microvolt = <0x13d620>;
  1536. phandle = <0x7>;
  1537. };
  1538.  
  1539. dcdc3 {
  1540. regulator-name = "dcdc3";
  1541. phandle = <0x9b>;
  1542. };
  1543.  
  1544. dcdc4 {
  1545. regulator-name = "dcdc4";
  1546. phandle = <0x9c>;
  1547. };
  1548.  
  1549. dcdc5 {
  1550. regulator-name = "vcc-dram";
  1551. regulator-always-on;
  1552. regulator-min-microvolt = <0x14c080>;
  1553. regulator-max-microvolt = <0x14c080>;
  1554. phandle = <0x9d>;
  1555. };
  1556.  
  1557. dcdc6 {
  1558. regulator-name = "vdd-sys";
  1559. regulator-always-on;
  1560. regulator-min-microvolt = <0x10c8e0>;
  1561. regulator-max-microvolt = <0x10c8e0>;
  1562. phandle = <0x9e>;
  1563. };
  1564.  
  1565. dldo1 {
  1566. regulator-name = "vcc-hdmi";
  1567. regulator-min-microvolt = <0x325aa0>;
  1568. regulator-max-microvolt = <0x325aa0>;
  1569. phandle = <0x4>;
  1570. };
  1571.  
  1572. dldo2 {
  1573. regulator-name = "vcc-mipi";
  1574. regulator-min-microvolt = <0x325aa0>;
  1575. regulator-max-microvolt = <0x325aa0>;
  1576. phandle = <0x9f>;
  1577. };
  1578.  
  1579. dldo3 {
  1580. regulator-name = "dldo3";
  1581. phandle = <0xa0>;
  1582. };
  1583.  
  1584. dldo4 {
  1585. regulator-name = "vcc-wifi";
  1586. regulator-min-microvolt = <0x325aa0>;
  1587. regulator-max-microvolt = <0x325aa0>;
  1588. phandle = <0x27>;
  1589. };
  1590.  
  1591. eldo1 {
  1592. regulator-name = "cpvdd";
  1593. regulator-min-microvolt = <0x1b7740>;
  1594. regulator-max-microvolt = <0x1b7740>;
  1595. phandle = <0x28>;
  1596. };
  1597.  
  1598. eldo2 {
  1599. regulator-name = "eldo2";
  1600. phandle = <0xa1>;
  1601. };
  1602.  
  1603. eldo3 {
  1604. regulator-name = "eldo3";
  1605. phandle = <0xa2>;
  1606. };
  1607.  
  1608. fldo1 {
  1609. regulator-name = "vcc-1v2-hsic";
  1610. regulator-min-microvolt = <0x124f80>;
  1611. regulator-max-microvolt = <0x124f80>;
  1612. phandle = <0xa3>;
  1613. };
  1614.  
  1615. fldo2 {
  1616. regulator-name = "vdd-cpus";
  1617. regulator-always-on;
  1618. regulator-min-microvolt = <0x10c8e0>;
  1619. regulator-max-microvolt = <0x10c8e0>;
  1620. phandle = <0xa4>;
  1621. };
  1622.  
  1623. ldo-io0 {
  1624. regulator-name = "ldo-io0";
  1625. status = "disabled";
  1626. phandle = <0xa5>;
  1627. };
  1628.  
  1629. ldo-io1 {
  1630. regulator-name = "ldo-io1";
  1631. status = "disabled";
  1632. phandle = <0xa6>;
  1633. };
  1634.  
  1635. rtc-ldo {
  1636. regulator-always-on;
  1637. regulator-min-microvolt = <0x2dc6c0>;
  1638. regulator-max-microvolt = <0x2dc6c0>;
  1639. regulator-name = "vcc-rtc";
  1640. phandle = <0xa7>;
  1641. };
  1642.  
  1643. drivevbus {
  1644. regulator-name = "drivevbus";
  1645. status = "disabled";
  1646. phandle = <0xa8>;
  1647. };
  1648. };
  1649.  
  1650. usb-power-supply {
  1651. compatible = "x-powers,axp803-usb-power-supply", "x-powers,axp813-usb-power-supply";
  1652. status = "disabled";
  1653. phandle = <0xa9>;
  1654. };
  1655. };
  1656. };
  1657.  
  1658. watchdog@1c20ca0 {
  1659. compatible = "allwinner,sun50i-a64-wdt", "allwinner,sun6i-a31-wdt";
  1660. reg = <0x1c20ca0 0x20>;
  1661. interrupts = <0x0 0x19 0x4>;
  1662. clocks = <0x2b>;
  1663. phandle = <0xaa>;
  1664. };
  1665. };
  1666.  
  1667. opp_table0 {
  1668. compatible = "operating-points-v2";
  1669. opp-shared;
  1670. phandle = <0x6>;
  1671.  
  1672. opp-648000000 {
  1673. opp-hz = <0x0 0x269fb200>;
  1674. opp-microvolt = <0xfde80>;
  1675. clock-latency-ns = <0x3b9b0>;
  1676. };
  1677.  
  1678. opp-816000000 {
  1679. opp-hz = <0x0 0x30a32c00>;
  1680. opp-microvolt = <0x10c8e0>;
  1681. clock-latency-ns = <0x3b9b0>;
  1682. };
  1683.  
  1684. opp-912000000 {
  1685. opp-hz = <0x0 0x365c0400>;
  1686. opp-microvolt = <0x111700>;
  1687. clock-latency-ns = <0x3b9b0>;
  1688. };
  1689.  
  1690. opp-960000000 {
  1691. opp-hz = <0x0 0x39387000>;
  1692. opp-microvolt = <0x11b340>;
  1693. clock-latency-ns = <0x3b9b0>;
  1694. };
  1695.  
  1696. opp-1008000000 {
  1697. opp-hz = <0x0 0x3c14dc00>;
  1698. opp-microvolt = <0x124f80>;
  1699. clock-latency-ns = <0x3b9b0>;
  1700. };
  1701.  
  1702. opp-1056000000 {
  1703. opp-hz = <0x0 0x3ef14800>;
  1704. opp-microvolt = <0x12ebc0>;
  1705. clock-latency-ns = <0x3b9b0>;
  1706. };
  1707.  
  1708. opp-1104000000 {
  1709. opp-hz = <0x0 0x41cdb400>;
  1710. opp-microvolt = <0x1339e0>;
  1711. clock-latency-ns = <0x3b9b0>;
  1712. };
  1713.  
  1714. opp-1152000000 {
  1715. opp-hz = <0x0 0x44aa2000>;
  1716. opp-microvolt = <0x13d620>;
  1717. clock-latency-ns = <0x3b9b0>;
  1718. };
  1719. };
  1720.  
  1721. aliases {
  1722. ethernet0 = "/soc/ethernet@1c30000";
  1723. serial0 = "/soc/serial@1c28000";
  1724. serial1 = "/soc/serial@1c28400";
  1725. serial2 = "/soc/serial@1c28800";
  1726. serial3 = "/soc/serial@1c28c00";
  1727. serial4 = "/soc/serial@1c29000";
  1728. };
  1729.  
  1730. hdmi-connector {
  1731. compatible = "hdmi-connector";
  1732. type = [61 00];
  1733.  
  1734. port {
  1735.  
  1736. endpoint {
  1737. remote-endpoint = <0x4f>;
  1738. phandle = <0x46>;
  1739. };
  1740. };
  1741. };
  1742.  
  1743. wifi_pwrseq {
  1744. compatible = "mmc-pwrseq-simple";
  1745. reset-gpios = <0x33 0x0 0x2 0x1>;
  1746. phandle = <0x29>;
  1747. };
  1748.  
  1749. __symbols__ {
  1750. simplefb_lcd = "/chosen/framebuffer-lcd";
  1751. simplefb_hdmi = "/chosen/framebuffer-hdmi";
  1752. cpu0 = "/cpus/cpu@0";
  1753. cpu1 = "/cpus/cpu@1";
  1754. cpu2 = "/cpus/cpu@2";
  1755. cpu3 = "/cpus/cpu@3";
  1756. L2 = "/cpus/l2-cache";
  1757. de = "/display-engine";
  1758. osc24M = "/osc24M_clk";
  1759. osc32k = "/osc32k_clk";
  1760. sound = "/sound";
  1761. link0_cpu = "/sound/simple-audio-card,dai-link@0/cpu";
  1762. link0_codec = "/sound/simple-audio-card,dai-link@0/codec";
  1763. spdif_out = "/spdif-out";
  1764. cpu_thermal = "/thermal-zones/cpu0-thermal";
  1765. cpu_alert0 = "/thermal-zones/cpu0-thermal/trips/cpu_alert0";
  1766. cpu_alert1 = "/thermal-zones/cpu0-thermal/trips/cpu_alert1";
  1767. cpu_crit = "/thermal-zones/cpu0-thermal/trips/cpu_crit";
  1768. gpu0_thermal = "/thermal-zones/gpu0-thermal";
  1769. gpu1_thermal = "/thermal-zones/gpu1-thermal";
  1770. display_clocks = "/soc/bus@1000000/clock@0";
  1771. rotate = "/soc/bus@1000000/rotate@20000";
  1772. mixer0 = "/soc/bus@1000000/mixer@100000";
  1773. mixer0_out = "/soc/bus@1000000/mixer@100000/ports/port@1";
  1774. mixer0_out_tcon0 = "/soc/bus@1000000/mixer@100000/ports/port@1/endpoint@0";
  1775. mixer0_out_tcon1 = "/soc/bus@1000000/mixer@100000/ports/port@1/endpoint@1";
  1776. mixer1 = "/soc/bus@1000000/mixer@200000";
  1777. mixer1_out = "/soc/bus@1000000/mixer@200000/ports/port@1";
  1778. mixer1_out_tcon0 = "/soc/bus@1000000/mixer@200000/ports/port@1/endpoint@0";
  1779. mixer1_out_tcon1 = "/soc/bus@1000000/mixer@200000/ports/port@1/endpoint@1";
  1780. syscon = "/soc/syscon@1c00000";
  1781. sram_c = "/soc/syscon@1c00000/sram@18000";
  1782. de2_sram = "/soc/syscon@1c00000/sram@18000/sram-section@0";
  1783. sram_c1 = "/soc/syscon@1c00000/sram@1d00000";
  1784. ve_sram = "/soc/syscon@1c00000/sram@1d00000/sram-section@0";
  1785. dma = "/soc/dma-controller@1c02000";
  1786. tcon0 = "/soc/lcd-controller@1c0c000";
  1787. tcon0_in = "/soc/lcd-controller@1c0c000/ports/port@0";
  1788. tcon0_in_mixer0 = "/soc/lcd-controller@1c0c000/ports/port@0/endpoint@0";
  1789. tcon0_in_mixer1 = "/soc/lcd-controller@1c0c000/ports/port@0/endpoint@1";
  1790. tcon0_out = "/soc/lcd-controller@1c0c000/ports/port@1";
  1791. tcon0_out_dsi = "/soc/lcd-controller@1c0c000/ports/port@1/endpoint@1";
  1792. tcon1 = "/soc/lcd-controller@1c0d000";
  1793. tcon1_in = "/soc/lcd-controller@1c0d000/ports/port@0";
  1794. tcon1_in_mixer0 = "/soc/lcd-controller@1c0d000/ports/port@0/endpoint@0";
  1795. tcon1_in_mixer1 = "/soc/lcd-controller@1c0d000/ports/port@0/endpoint@1";
  1796. tcon1_out = "/soc/lcd-controller@1c0d000/ports/port@1";
  1797. tcon1_out_hdmi = "/soc/lcd-controller@1c0d000/ports/port@1/endpoint@1";
  1798. mmc0 = "/soc/mmc@1c0f000";
  1799. mmc1 = "/soc/mmc@1c10000";
  1800. mmc2 = "/soc/mmc@1c11000";
  1801. sid = "/soc/eeprom@1c14000";
  1802. ths_calibration = "/soc/eeprom@1c14000/thermal-sensor-calibration@34";
  1803. crypto = "/soc/crypto@1c15000";
  1804. usb_otg = "/soc/usb@1c19000";
  1805. usbphy = "/soc/phy@1c19400";
  1806. ehci0 = "/soc/usb@1c1a000";
  1807. ohci0 = "/soc/usb@1c1a400";
  1808. ehci1 = "/soc/usb@1c1b000";
  1809. ohci1 = "/soc/usb@1c1b400";
  1810. ccu = "/soc/clock@1c20000";
  1811. pio = "/soc/pinctrl@1c20800";
  1812. aif2_pins = "/soc/pinctrl@1c20800/aif2-pins";
  1813. aif3_pins = "/soc/pinctrl@1c20800/aif3-pins";
  1814. csi_pins = "/soc/pinctrl@1c20800/csi-pins";
  1815. csi_mclk_pin = "/soc/pinctrl@1c20800/csi-mclk-pin";
  1816. i2c0_pins = "/soc/pinctrl@1c20800/i2c0-pins";
  1817. i2c1_pins = "/soc/pinctrl@1c20800/i2c1-pins";
  1818. i2c2_pins = "/soc/pinctrl@1c20800/i2c2-pins";
  1819. lcd_rgb666_pins = "/soc/pinctrl@1c20800/lcd-rgb666-pins";
  1820. mmc0_pins = "/soc/pinctrl@1c20800/mmc0-pins";
  1821. mmc1_pins = "/soc/pinctrl@1c20800/mmc1-pins";
  1822. mmc2_pins = "/soc/pinctrl@1c20800/mmc2-pins";
  1823. mmc2_ds_pin = "/soc/pinctrl@1c20800/mmc2-ds-pin";
  1824. pwm_pin = "/soc/pinctrl@1c20800/pwm-pin";
  1825. rmii_pins = "/soc/pinctrl@1c20800/rmii-pins";
  1826. rgmii_pins = "/soc/pinctrl@1c20800/rgmii-pins";
  1827. spdif_tx_pin = "/soc/pinctrl@1c20800/spdif-tx-pin";
  1828. spi0_pins = "/soc/pinctrl@1c20800/spi0-pins";
  1829. spi1_pins = "/soc/pinctrl@1c20800/spi1-pins";
  1830. uart0_pb_pins = "/soc/pinctrl@1c20800/uart0-pb-pins";
  1831. uart1_pins = "/soc/pinctrl@1c20800/uart1-pins";
  1832. uart1_rts_cts_pins = "/soc/pinctrl@1c20800/uart1-rts-cts-pins";
  1833. uart2_pins = "/soc/pinctrl@1c20800/uart2-pins";
  1834. uart3_pins = "/soc/pinctrl@1c20800/uart3-pins";
  1835. uart4_pins = "/soc/pinctrl@1c20800/uart4-pins";
  1836. uart4_rts_cts_pins = "/soc/pinctrl@1c20800/uart4-rts-cts-pins";
  1837. spdif = "/soc/spdif@1c21000";
  1838. lradc = "/soc/lradc@1c21800";
  1839. i2s0 = "/soc/i2s@1c22000";
  1840. i2s1 = "/soc/i2s@1c22400";
  1841. dai = "/soc/dai@1c22c00";
  1842. codec = "/soc/codec@1c22e00";
  1843. ths = "/soc/thermal-sensor@1c25000";
  1844. uart0 = "/soc/serial@1c28000";
  1845. uart1 = "/soc/serial@1c28400";
  1846. uart2 = "/soc/serial@1c28800";
  1847. uart3 = "/soc/serial@1c28c00";
  1848. uart4 = "/soc/serial@1c29000";
  1849. i2c0 = "/soc/i2c@1c2ac00";
  1850. i2c1 = "/soc/i2c@1c2b000";
  1851. i2c2 = "/soc/i2c@1c2b400";
  1852. spi0 = "/soc/spi@1c68000";
  1853. spi1 = "/soc/spi@1c69000";
  1854. emac = "/soc/ethernet@1c30000";
  1855. mdio = "/soc/ethernet@1c30000/mdio";
  1856. ext_rgmii_phy = "/soc/ethernet@1c30000/mdio/ethernet-phy@1";
  1857. ext_rmii_phy1 = "/soc/ethernet@1c30000/mdio/ethernet-phy@1";
  1858. mali = "/soc/gpu@1c40000";
  1859. gic = "/soc/interrupt-controller@1c81000";
  1860. pwm = "/soc/pwm@1c21400";
  1861. csi = "/soc/csi@1cb0000";
  1862. dsi = "/soc/dsi@1ca0000";
  1863. dsi_in_tcon0 = "/soc/dsi@1ca0000/port/endpoint";
  1864. dphy = "/soc/d-phy@1ca1000";
  1865. hdmi = "/soc/hdmi@1ee0000";
  1866. hdmi_in = "/soc/hdmi@1ee0000/ports/port@0";
  1867. hdmi_in_tcon1 = "/soc/hdmi@1ee0000/ports/port@0/endpoint";
  1868. hdmi_out = "/soc/hdmi@1ee0000/ports/port@1";
  1869. hdmi_out_con = "/soc/hdmi@1ee0000/ports/port@1/endpoint";
  1870. hdmi_phy = "/soc/hdmi-phy@1ef0000";
  1871. i2s2 = "/soc/i2s@1c22800";
  1872. sound_hdmi = "/soc/sound_hdmi";
  1873. rtc = "/soc/rtc@1f00000";
  1874. r_intc = "/soc/interrupt-controller@1f00c00";
  1875. r_ccu = "/soc/clock@1f01400";
  1876. codec_analog = "/soc/codec-analog@1f015c0";
  1877. r_i2c = "/soc/i2c@1f02400";
  1878. r_ir = "/soc/ir@1f02000";
  1879. r_pwm = "/soc/pwm@1f03800";
  1880. r_pio = "/soc/pinctrl@1f02c00";
  1881. r_i2c_pl89_pins = "/soc/pinctrl@1f02c00/r-i2c-pl89-pins";
  1882. r_ir_rx_pin = "/soc/pinctrl@1f02c00/r-ir-rx-pin";
  1883. r_pwm_pin = "/soc/pinctrl@1f02c00/r-pwm-pin";
  1884. r_rsb_pins = "/soc/pinctrl@1f02c00/r-rsb-pins";
  1885. r_rsb = "/soc/rsb@1f03400";
  1886. axp803 = "/soc/rsb@1f03400/pmic@3a3";
  1887. ac_power_supply = "/soc/rsb@1f03400/pmic@3a3/ac-power-supply";
  1888. axp_adc = "/soc/rsb@1f03400/pmic@3a3/adc";
  1889. axp_gpio = "/soc/rsb@1f03400/pmic@3a3/gpio";
  1890. gpio0_ldo = "/soc/rsb@1f03400/pmic@3a3/gpio/gpio0-ldo";
  1891. gpio1_ldo = "/soc/rsb@1f03400/pmic@3a3/gpio/gpio1-ldo";
  1892. battery_power_supply = "/soc/rsb@1f03400/pmic@3a3/battery-power-supply";
  1893. reg_aldo1 = "/soc/rsb@1f03400/pmic@3a3/regulators/aldo1";
  1894. reg_aldo2 = "/soc/rsb@1f03400/pmic@3a3/regulators/aldo2";
  1895. reg_aldo3 = "/soc/rsb@1f03400/pmic@3a3/regulators/aldo3";
  1896. reg_dc1sw = "/soc/rsb@1f03400/pmic@3a3/regulators/dc1sw";
  1897. reg_dcdc1 = "/soc/rsb@1f03400/pmic@3a3/regulators/dcdc1";
  1898. reg_dcdc2 = "/soc/rsb@1f03400/pmic@3a3/regulators/dcdc2";
  1899. reg_dcdc3 = "/soc/rsb@1f03400/pmic@3a3/regulators/dcdc3";
  1900. reg_dcdc4 = "/soc/rsb@1f03400/pmic@3a3/regulators/dcdc4";
  1901. reg_dcdc5 = "/soc/rsb@1f03400/pmic@3a3/regulators/dcdc5";
  1902. reg_dcdc6 = "/soc/rsb@1f03400/pmic@3a3/regulators/dcdc6";
  1903. reg_dldo1 = "/soc/rsb@1f03400/pmic@3a3/regulators/dldo1";
  1904. reg_dldo2 = "/soc/rsb@1f03400/pmic@3a3/regulators/dldo2";
  1905. reg_dldo3 = "/soc/rsb@1f03400/pmic@3a3/regulators/dldo3";
  1906. reg_dldo4 = "/soc/rsb@1f03400/pmic@3a3/regulators/dldo4";
  1907. reg_eldo1 = "/soc/rsb@1f03400/pmic@3a3/regulators/eldo1";
  1908. reg_eldo2 = "/soc/rsb@1f03400/pmic@3a3/regulators/eldo2";
  1909. reg_eldo3 = "/soc/rsb@1f03400/pmic@3a3/regulators/eldo3";
  1910. reg_fldo1 = "/soc/rsb@1f03400/pmic@3a3/regulators/fldo1";
  1911. reg_fldo2 = "/soc/rsb@1f03400/pmic@3a3/regulators/fldo2";
  1912. reg_ldo_io0 = "/soc/rsb@1f03400/pmic@3a3/regulators/ldo-io0";
  1913. reg_ldo_io1 = "/soc/rsb@1f03400/pmic@3a3/regulators/ldo-io1";
  1914. reg_rtc_ldo = "/soc/rsb@1f03400/pmic@3a3/regulators/rtc-ldo";
  1915. reg_drivevbus = "/soc/rsb@1f03400/pmic@3a3/regulators/drivevbus";
  1916. usb_power_supply = "/soc/rsb@1f03400/pmic@3a3/usb-power-supply";
  1917. wdt0 = "/soc/watchdog@1c20ca0";
  1918. cpu0_opp_table = "/opp_table0";
  1919. hdmi_con_in = "/hdmi-connector/port/endpoint";
  1920. wifi_pwrseq = "/wifi_pwrseq";
  1921. };
  1922. };
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