module counter(

    input logic clk, resetn, start,
    output logic [2:0] count
);

    localparam MAX_VAL = 5;
    localparam CNT_LIM = 5;//????????
    logic [2:0] delay_cnt;
    logic [2:0] run_cnt;

    enum logic unsigned [2:0] {ST_DELAY, ST_STOP, ST_RUN} state;

    always_ff @ (posedge clk or negedge resetn)
    begin
        if(!resetn)
        begin
            delay_cnt <= 0;
            run_cnt <= 0;
            count <= 0;
            if(start)
                state <= ST_RUN;

            else
                state <= ST_STOP;
        end

        else
        begin
            case(state)

            ST_RUN: begin
                if(start)//|| count != 0)
                begin
                    if( (count < MAX_VAL) || (run_cnt < CNT_LIM-1) )
                    begin
                        count <= count + 1;
                        run_cnt <= run_cnt + 1;
                    end

                    else
                    begin
                        count <= 0;
                        run_cnt <= 0;
                        state <= ST_DELAY;
                    end
                end

                else
                begin
                    if(count == 0)
                        state <= ST_STOP;
                    else
                    begin
                        if( (count < MAX_VAL) )// || (run_cnt < CNT_LIM) )
                        begin
                            count <= count + 1;
                            run_cnt <= run_cnt + 1;
                        end
                        else
                            state <= ST_STOP;
                    end
                end
            end

            ST_STOP: begin
                if(!start)
                begin
                    run_cnt <= 0;
                    count <= 0;
                end
                else
                    state <= ST_RUN;
            end

            ST_DELAY: begin
                if( delay_cnt < CNT_LIM)
                begin
                    count <= 0;
                    delay_cnt <= delay_cnt + 1;
                end
                else
                begin
                    delay_cnt <= 0;
                    if(start)
                        state <= ST_RUN;
                    else
                        state <= ST_STOP;
                end
            end
            endcase
        end
    end
endmodule