FSM;-------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY fsm IS
port (	reset: in std_logic;
	clk: in std_logic;
	w, c, r: in std_logic;
	enable: out std_logic_vector(0 to 1);
	licz, drive, creset: out std_logic);
END ENTITY fsm;

--
ARCHITECTURE z12 OF fsm IS

type stany is (idle, read, write1, write2, compare);
signal state, next_state : stany;
signal req: std_logic_vector(2 downto 0);

BEGIN

synchrP: process (clk, reset)
begin
	if reset='0' then
		state <= idle;
	elsif (rising_edge(clk)) then
		state<= next_state;
	end if;
end process;

req <= w&c&r;

kombP: process(state, req)
begin

case state is
when idle =>
	if (req="100") then
		next_state <= write1; enable <= "10"; licz<='0';
	elsif (req="010") then
		next_state <= compare; enable<="00"; licz<='1';
	elsif (req="001") then
		next_state <= read; enable<="00"; licz<='0';
	else
		next_state <= idle; enable<="00"; licz<='0';
	end if;
	drive <= '0'; creset <='0';

when read =>
if(req = "001") then
  next_state <= read;
  licz <= '0';
  drive <= '1';


elsif(req = "100") then
  next_state <= write1;
  drive <= '0';
  licz <= '0';

elsif(req = "010") then
  next_state <= compare;
  licz <='1';
  drive <= '0';


end if;

enable <="00";

creset<='0';



------------------------------------------------------------

when write1 =>
  next_state <= write2;
enable<="01";
licz<='0';
drive<='0';
creset <='1';


------------------------------------------------------------
when write2 =>
if(req = "100") then
  next_state <= write1;
  enable <= "10";
  licz <='0';

elsif(req = "010") then
  next_state <= compare;
  enable <= "00";
  licz <='1';

elsif(req = "001") then
  next_state <= read;
  enable <= "00";
  licz <='0';


else
  next_state <= idle;
  enable <= "00";
  licz <='0';

end if;
drive <= '0';
creset <='0';
---------------------------------------------------------------
when compare =>
if(req = "100") then
  next_state <= write1;
  licz <= '0';

elsif(req = "010") then
  next_state <= compare;
  licz <='1';

elsif(req = "001") then
  next_state <= read;
  licz <= '0';

else
  next_state <= idle;
  licz<='0';

end if;

enable <= "00";
drive <= '0';
creset <= '0';



end case;
end process;


END ARCHITECTURE z12;





COMPARAGE:-----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY comprange IS
  generic (m: integer range 0 to 1024 := 4);
  port (reset: in std_logic;
  	clk : in std_logic;
        write, comp, read: in std_logic;
        data: inout UNSIGNED (m-1 downto 0));
END ENTITY comprange;

--
ARCHITECTURE z12 OF comprange IS

component reg
  generic (m : integer range 0 to 1024 := 4);
  port (    data_in: in UNSIGNED (m-1 downto 0);
            reg_out: out UNSIGNED (m-1 downto 0);
            clk, enable: in std_logic);
END component;

component counter
  generic(m: integer range 0 to 1024 := 4);
  port(clk, reset: in std_logic;
       licz, inc: in std_logic;
       count: out UNSIGNED(m-1 downto 0));
END component;

component fsm
  port (reset: in std_logic;
  	clk: in std_logic;
        w, r, c: in std_logic;
        enable: out std_logic_vector(0 to 1);
        licz, drive, creset: out std_logic);
END component;

component bu3
  generic (m : integer :=4);
   port (    data_in: in UNSIGNED (m-1 downto 0);
             data_out: out UNSIGNED (m-1 downto 0);
             drive: in std_logic);
END component;

component comp3
   port (    data_in: in UNSIGNED (m-1 downto 0);
             range1, range2: in UNSIGNED (m-1 downto 0);
             inc: out std_logic);
END component;


signal licz, drive, inc, creset: std_logic;
signal reg1out, reg2out, countout: UNSIGNED(m-1 downto 0);
signal enable: std_logic_vector (0 to 1);

BEGIN
--port => sygnal

Reg1: reg port map
(
  reg_out =>reg1out,
  data_in => data,
  enable => enable(0),
  clk=>clk
);
Reg2: reg port map
(
  reg_out =>reg2out,
  data_in => data,
  enable => enable(1),
  clk=>clk
);

Buf3s: bu3 port map
(
  data_in => countout,
  data_out => data,
  drive => drive
);


Control: fsm port map
(
  clk => clk,
  w => write,
  r => read,
  c => comp,
  enable => enable,
  licz => licz,
  drive => drive,
  reset => reset,
  creset => creset
);

Count: counter port map
(
  clk => clk,
  reset => creset,
  licz => licz,
  inc => inc,
  count => countout
);
Compare: comp3 port map
(
  data_in => data,
  range1 => reg1out,
  range2 => reg2out,
  inc => inc
);

END ARCHITECTURE z12;