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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 11/10/2023 05:13:54 PM
  7. // Design Name:
  8. // Module Name: Rx_fsm
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22.  
  23. module Rx_fsm(
  24. input CLK50MHZ,
  25. input baud_tick,
  26. input FIFO_nFull,
  27. input RxD,
  28. input n_rst,
  29. output reg [7:0] sample,
  30. output reg Rx_Done
  31. //output reg [3:0] tick_no, data_stop_no //should be removed later
  32. );
  33.  
  34. reg [5:0] state, next_state;
  35. reg [3:0] tick_no = 4'b0;
  36. reg [3:0] bit_no = 4'b0;
  37. parameter init = 6'b000001,
  38. wait7 = 6'b000010,
  39. wait16 = 6'b000100,
  40. sample_out = 6'b001000,
  41. add_bit = 6'b010000,
  42. done = 6'b100000;
  43. // State and next state register
  44. always@(posedge CLK50MHZ or negedge n_rst) begin
  45. if(!n_rst) begin
  46. state <= init;
  47. tick_no <= 0;
  48. bit_no <= 0;
  49. end
  50. else if(baud_tick) begin
  51. state <= next_state;
  52. bit_no <= bit_no;
  53. tick_no <= tick_no;
  54. end
  55. else begin
  56. state <= state;
  57. bit_no <= bit_no;
  58. tick_no <= tick_no;
  59. end
  60. end
  61.  
  62. //Counter register
  63. always@(posedge CLK50MHZ or negedge n_rst) begin
  64. if(!n_rst) begin
  65. tick_no <= 0;
  66. end
  67. else if(baud_tick) tick_no <= tick_no + 1;
  68. else tick_no <= tick_no;
  69. end
  70.  
  71. always@(state, RxD) begin: next_state_logic
  72. case(state)
  73. init: begin
  74. tick_no = 0;
  75. bit_no = 0;
  76. if(!RxD) next_state = wait7;
  77. else next_state = init;
  78. end
  79. wait7: begin
  80. bit_no = 0;
  81. tick_no = tick_no + 1;
  82. if(tick_no == 8) begin
  83. next_state = wait16;
  84. tick_no = 0;
  85. end
  86. else next_state = wait7;
  87. end
  88. wait16: begin
  89. bit_no = bit_no;
  90. tick_no = tick_no + 1;
  91. if(tick_no == 16) begin
  92. next_state = sample_out;
  93. tick_no = 0;
  94. end
  95. else next_state = wait16;
  96. end
  97. sample_out: begin
  98. next_state = add_bit;
  99. tick_no = tick_no;
  100. bit_no = bit_no;
  101. end
  102. add_bit: begin
  103. bit_no = bit_no + 1;
  104. tick_no = 0;
  105. if(bit_no == 8) begin
  106. next_state = done;
  107. bit_no = 0;
  108. tick_no = 0;
  109. end
  110. else next_state = wait16;
  111. end
  112. done: begin
  113. tick_no = 0;
  114. bit_no = 0;
  115. next_state = init;
  116. end
  117. default: begin
  118. next_state = init;
  119. tick_no = 0;
  120. bit_no = 0;
  121. end
  122. endcase
  123. end
  124.  
  125. always@(state) begin: output_logic
  126. case(state)
  127. init: begin
  128. sample <= 8'b0;
  129. Rx_Done <= 1'b0;
  130. end
  131. wait7: begin
  132. sample <= 8'b0;
  133. Rx_Done <= 1'b0;
  134. end
  135. wait16: begin
  136. sample <= 8'b0;
  137. Rx_Done <= 1'b0;
  138. end
  139. sample_out: begin
  140. sample[bit_no] <= 1'b1;
  141. Rx_Done <= 1'b0;
  142. end
  143. add_bit: begin
  144. sample <= 8'b0;
  145. Rx_Done <= 1'b0;
  146. end
  147. done: begin
  148. sample <= 8'b0;
  149. Rx_Done <= 1'b1;
  150. end
  151. default: begin
  152. sample <= 8'b0;
  153. Rx_Done <= 1'b0;
  154. end
  155. endcase
  156. end
  157. endmodule
  158.  
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