library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all;
use ieee.std_logic_textio.all;

entity example_file_io_tb is

end example_file_io_tb;


architecture behave of example_file_io_tb is

  -----------------------------------------------------------------------------
  -- Declare the Component Under Test
  -----------------------------------------------------------------------------
COMPONENT  Fulladder_generic is
GENERIC (
	data_width : INTEGER := 4);
PORT (
	a : IN STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
	b : IN STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
	cin : IN STD_LOGIC :='0';
	s : OUT STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
	cout : OUT STD_LOGIC);
END COMPONENT ;
  -----------------------------------------------------------------------------
  -- Testbench Internal Signals
  -----------------------------------------------------------------------------
  file file_VECTORS : text;
  file file_RESULTS : text;

  constant c_WIDTH : natural := 4;

  signal r_ADD_TERM1 : std_logic_vector(c_WIDTH-1 downto 0) := (others => '0');
  signal r_ADD_TERM2 : std_logic_vector(c_WIDTH-1 downto 0) := (others => '0');
  signal w_SUM       : std_logic_vector(c_WIDTH-1 downto 0);

begin

  -----------------------------------------------------------------------------
  -- Instantiate and Map UUT
  -----------------------------------------------------------------------------
  fulladder_inst : Fulladder_generic
    generic map (
      data_width => c_WIDTH)
    port map (
      a => r_ADD_TERM1,
      b => r_ADD_TERM2,
      s => w_SUM
      );


  ---------------------------------------------------------------------------
  -- This procedure reads the file input_vectors.txt which is located in the
  -- simulation project area.
  -- It will read the data in and send it to the ripple-adder component
  -- to perform the operations.  The result is written to the
  -- output_results.txt file, located in the same directory.
  ---------------------------------------------------------------------------
  process
    variable v_ILINE     : line;
    variable v_OLINE     : line;
    variable v_ADD_TERM1 : std_logic_vector(c_WIDTH-1 downto 0);
    variable v_ADD_TERM2 : std_logic_vector(c_WIDTH-1 downto 0);
    variable v_SPACE     : character;

  begin

    file_open(file_VECTORS, "D:\UNI\ITCE211\Codes\textio3\input_vectors.txt",  read_mode);
    file_open(file_RESULTS, "D:\UNI\ITCE211\Codes\textio3\output_results.txt", write_mode);

    while not endfile(file_VECTORS) loop
      readline(file_VECTORS, v_ILINE);
      read(v_ILINE, v_ADD_TERM1);
      read(v_ILINE, v_SPACE);           -- read in the space character
      read(v_ILINE, v_ADD_TERM2);

      -- Pass the variable to a signal to allow the ripple-carry to use it
      r_ADD_TERM1 <= v_ADD_TERM1;
      r_ADD_TERM2 <= v_ADD_TERM2;

      wait for 60 ns;

      write(v_OLINE, w_SUM, right, c_WIDTH);
      writeline(file_RESULTS, v_OLINE);
    end loop;

    file_close(file_VECTORS);
    file_close(file_RESULTS);

    wait;
  end process;

end behave;