module i2s_asynchronous_fifo
(
    // clocks
    input r_clk,
    input w_clk,
    // resets
    input r_rst_n,
    input w_rst_n,
    // enables
    input fifo_read_en,
    input fifo_write_en,
    input direct_read,
    input direct_write,
    // control signals
    input fifo_clear,
    input [ADDRESS_WIDTH-1:0] fifo_threshold,
    output reg [ADDRESS_WIDTH-1:0] fifo_fill_level,
    // flag signals
    output fifo_empty,
    output fifo_almost_empty,
    output fifo_full,
    output fifo_almost_full,
    // data access ports
    input [DATA_WIDTH-1:0] fifo_write_data,
    output reg [DATA_WIDTH-1:0] fifo_read_data,
    // input
    // debug FIFO memory access
    input fifo_debug_en,
    input fifo_debug_read_en,
    input fifo_debug_write_en,
    input [ADDRESS_WIDTH-1:0] fifo_mem_write_address,
    input [ADDRESS_WIDTH-1:0] fifo_mem_read_address,
    input [DATA_WIDTH-1:0] fifo_mem_write_data,
    output reg [DATA_WIDTH-1:0] fifo_mem_read_data
);

parameter DATA_WIDTH = 32;
parameter ADDRESS_WIDTH = 5;
parameter FIFO_DEPTH = (1 << ADDRESS_WIDTH);

// internal signals
reg next_read_addr_en, next_write_addr_en;
reg [ADDRESS_WIDTH-1:0] next_read_addr, next_write_addr;
reg direct_read, direct_write;
reg gray_clear_read, gray_clear_write;

// component instantiations
i2s_gray_counter
#(
    .COUNTER_WIDTH(ADDRESS_WIDTH)
)
i2s_gray_counter_read_i
(
    .clk(r_clk),
    .clear(gray_clear_read),
    .direct_access(direct_read),
    .en(next_read_addr_en),
    .gray_count_out(next_read_addr)
);

i2s_gray_counter
#(
    .COUNTER_WIDTH(ADDRESS_WIDTH)
)
i2s_gray_counter_write_i
(
    .clk(w_clk),
    .clear(gray_clear_write),
    .direct_access(direct_write),
    .en(next_write_addr_en),
    .gray_count_out(next_write_addr)
);

// read process
always @(posedge r_clk or posedge direct_read or negedge r_rst_n) begin
    if !(r_rst_n) begin
        fifo_read_data <= '0;
    end
    else begin
    end
end

// write process
always @(posedge w_clk or posedge direct_write or negedge w_rst_n) begin
    if !(w_rst_n) begin
    end
    else begin
    end
end

// continuous assignments
assign gray_clear_read = ~r_rst_n | fifo_clear;
assign gray_clear_write = ~w_rst_n | fifo_clear;

endmodule