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AnatolySharapov

functional.tcl

Apr 9th, 2021
185
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  1. # ////////////////////////////////////////////////////////////////////
  2. # File name     : functional.tcl
  3. # Author        : Anatoly A. Sharapov
  4. # Email         : a.a.sharapov@gmail.com
  5. # Phone         : +7 903 231-11-26
  6. # Company       : PJS MIEA
  7. # Dep           : 311
  8. # Description   : Functional simulation script  
  9. # Last revision : 20.02.2021
  10. # /////////////////////////////////////////////////////////////////////
  11.  
  12. if {!([vsimAuth] == "ALTERA STARTER EDITION")} {
  13.     # https://electronix.ru/forum/index.php?app=forums&module=forums&controller=topic&id=122907
  14.     # main window at full screen
  15.     wm state . zoomed
  16. }
  17.  
  18. # clear transript window of ModelSim or QuestaSim
  19. .main clear
  20.  
  21. # create library
  22. if [file exists work] {
  23.     vdel -all
  24. }
  25.  
  26. vlib work
  27.  
  28. # SystemVerilog Project Files
  29. variable Project_Path ../RTL/Project
  30. variable Project_SystemVerilog_Files_Compiled 0
  31. variable Project_SystemVerilog_Files [glob -nocomplain $Project_Path/*.sv]
  32. if {[llength $Project_SystemVerilog_Files]} {
  33.     vlog +acc +include+$Project_Path $Project_Path/*.sv
  34.     variable Project_SystemVerilog_Files_Compiled 1
  35. }
  36.  
  37. # Compile SystemVerilog TestBench's Files
  38. variable TestBench_Path ../RTL/TestBench
  39. variable TestBench_SystemVerilog_Files_Compiled 0
  40. variable TestBench_SystemVerilog_Files [glob -nocomplain $TestBench_Path/*.sv]
  41. if {[llength $TestBench_SystemVerilog_Files]} {
  42.     vlog +acc $TestBench_Path/*.sv
  43.     variable TestBench_SystemVerilog_Files_Compiled 1
  44. }
  45.  
  46. if {!($Project_SystemVerilog_Files_Compiled &&
  47.       $TestBench_SystemVerilog_Files_Compiled )} {
  48.     puts "Error compiling files!"
  49.     Exit
  50. }
  51.  
  52. variable testbench clk1MHzFrom64MHzena_tb
  53. vsim -L work work.$testbench
  54.  
  55. variable wave_window_kind "white_foreground_and_black_background"
  56. source wave_window_signals.tcl
  57. wave_window_signals $wave_window_kind $testbench
  58.  
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