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  1. diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
  2. index cc51e4746b3b..a2602b5d5378 100644
  3. --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
  4. +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
  5. @@ -16,6 +16,8 @@ Required Properties:
  6.    * "xtal": the 24MHz system oscillator
  7.    * "ddr_pll": the DDR PLL clock
  8.    * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
  9. +  * "rmii_clk": (if present) the 50MHz RMII reference clock (from the PHY or
  10. +                an external oscillator
  11.  
  12.  Parent node should have the following properties :
  13.  - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
  14. diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
  15. index 7d41cf291f40..93d4150ee3e3 100644
  16. --- a/arch/arm/boot/dts/meson8.dtsi
  17. +++ b/arch/arm/boot/dts/meson8.dtsi
  18. @@ -823,8 +823,8 @@ cvbs_trimming: calib@1f8 {
  19.  };
  20.  
  21.  &ethmac {
  22. -   clocks = <&clkc CLKID_ETH>;
  23. -   clock-names = "stmmaceth";
  24. +   clocks = <&clkc CLKID_ETH>, <&clkc CLKID_ETH_CLK>;
  25. +   clock-names = "stmmaceth", "clkin0";
  26.  
  27.     power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
  28.  };
  29. diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
  30. index 0f7993a1b515..f664f6fd25cc 100644
  31. --- a/drivers/clk/meson/meson8b.c
  32. +++ b/drivers/clk/meson/meson8b.c
  33. @@ -2639,6 +2639,101 @@ static struct clk_regmap meson8b_cts_i958 = {
  34.     },
  35.  };
  36.  
  37. +static u32 meson8_eth_clk_mux_table[] = { 7 };
  38. +
  39. +static struct clk_regmap meson8_eth_clk_sel = {
  40. +   .data = &(struct clk_regmap_mux_data){
  41. +       .offset = HHI_ETH_CLK_CNTL,
  42. +       .mask = 0x7,
  43. +       .shift = 9,
  44. +       .table = meson8_eth_clk_mux_table,
  45. +   },
  46. +   .hw.init = &(struct clk_init_data) {
  47. +       .name = "eth_clk_sel",
  48. +       .ops = &clk_regmap_mux_ops,
  49. +       .parent_data = &(const struct clk_parent_data) {
  50. +           /* TODO: all other parents are unknown */
  51. +           .fw_name = "rmii_clk",
  52. +       },
  53. +       .num_parents = 1,
  54. +   },
  55. +};
  56. +
  57. +static struct clk_regmap meson8_eth_clk_div = {
  58. +   .data = &(struct clk_regmap_div_data){
  59. +       .offset = HHI_ETH_CLK_CNTL,
  60. +       .shift = 0,
  61. +       .width = 8,
  62. +   },
  63. +   .hw.init = &(struct clk_init_data) {
  64. +       .name = "eth_clk_div",
  65. +       .ops = &clk_regmap_divider_ops,
  66. +       .parent_hws = (const struct clk_hw *[]) {
  67. +           &meson8_eth_clk_sel.hw
  68. +       },
  69. +       .num_parents = 1,
  70. +       .flags = CLK_SET_RATE_PARENT,
  71. +   },
  72. +};
  73. +
  74. +static int meson8_eth_clk_get_phase(struct clk_hw *hw)
  75. +{
  76. +   struct clk_regmap *clk = to_clk_regmap(hw);
  77. +   unsigned int val;
  78. +
  79. +   regmap_read(clk->map, HHI_ETH_CLK_CNTL, &val);
  80. +
  81. +   return (val & BIT(14)) ? 180 : 0;
  82. +}
  83. +
  84. +static int meson8_eth_clk_set_phase(struct clk_hw *hw, int degrees)
  85. +{
  86. +   struct clk_regmap *clk = to_clk_regmap(hw);
  87. +   u32 set;
  88. +
  89. +   if (degrees == 180)
  90. +       set = BIT(14);
  91. +   else if (degrees == 0)
  92. +       set = 0;
  93. +   else
  94. +       return -EINVAL;
  95. +
  96. +   return regmap_update_bits(clk->map, HHI_ETH_CLK_CNTL, BIT(14), set);
  97. +}
  98. +
  99. +const struct clk_ops meson8_eth_clk_phase_ops = {
  100. +   .get_phase = meson8_eth_clk_get_phase,
  101. +   .set_phase = meson8_eth_clk_set_phase,
  102. +};
  103. +
  104. +static struct clk_regmap meson8_eth_clk_phase = {
  105. +   .hw.init = &(struct clk_init_data){
  106. +       .name = "eth_clk_inverted",
  107. +       .ops = &meson8_eth_clk_phase_ops,
  108. +       .parent_hws = (const struct clk_hw *[]) {
  109. +           &meson8_eth_clk_div.hw
  110. +       },
  111. +       .num_parents = 1,
  112. +       .flags = CLK_SET_RATE_PARENT,
  113. +   },
  114. +};
  115. +
  116. +static struct clk_regmap meson8_eth_clk_gate = {
  117. +   .data = &(struct clk_regmap_gate_data){
  118. +       .offset = HHI_ETH_CLK_CNTL,
  119. +       .bit_idx = 8,
  120. +   },
  121. +   .hw.init = &(struct clk_init_data){
  122. +       .name = "eth_clk_en",
  123. +       .ops = &clk_regmap_gate_ops,
  124. +       .parent_hws = (const struct clk_hw *[]) {
  125. +           &meson8_eth_clk_phase.hw
  126. +       },
  127. +       .num_parents = 1,
  128. +       .flags = CLK_SET_RATE_PARENT,
  129. +   },
  130. +};
  131. +
  132.  #define MESON_GATE(_name, _reg, _bit) \
  133.     MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
  134.  
  135. @@ -2933,6 +3028,10 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
  136.         [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
  137.         [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
  138.         [CLKID_CTS_I958]        = &meson8b_cts_i958.hw,
  139. +       [CLKID_ETH_CLK_SEL]     = &meson8_eth_clk_sel.hw,
  140. +       [CLKID_ETH_CLK_DIV]     = &meson8_eth_clk_div.hw,
  141. +       [CLKID_ETH_CLK_PHASE]       = &meson8_eth_clk_phase.hw,
  142. +       [CLKID_ETH_CLK]         = &meson8_eth_clk_gate.hw,
  143.         [CLK_NR_CLKS]           = NULL,
  144.     },
  145.     .num = CLK_NR_CLKS,
  146. @@ -3563,6 +3662,10 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
  147.     &meson8b_cts_mclk_i958_div,
  148.     &meson8b_cts_mclk_i958,
  149.     &meson8b_cts_i958,
  150. +   &meson8_eth_clk_sel,
  151. +   &meson8_eth_clk_div,
  152. +   &meson8_eth_clk_phase,
  153. +   &meson8_eth_clk_gate,
  154.  };
  155.  
  156.  static const struct meson8b_clk_reset_line {
  157. diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
  158. index 2569f3431fbe..25cf987284fb 100644
  159. --- a/drivers/clk/meson/meson8b.h
  160. +++ b/drivers/clk/meson/meson8b.h
  161. @@ -43,6 +43,7 @@
  162.  #define HHI_MALI_CLK_CNTL      0x1b0 /* 0x6c offset in data sheet */
  163.  #define HHI_VPU_CLK_CNTL       0x1bc /* 0x6f offset in data sheet */
  164.  #define HHI_HDMI_CLK_CNTL      0x1cc /* 0x73 offset in data sheet */
  165. +#define HHI_ETH_CLK_CNTL       0x1d8 /* 0x76 offset in data sheet */
  166.  #define HHI_VDEC_CLK_CNTL      0x1e0 /* 0x78 offset in data sheet */
  167.  #define HHI_VDEC2_CLK_CNTL     0x1e4 /* 0x79 offset in data sheet */
  168.  #define HHI_VDEC3_CLK_CNTL     0x1e8 /* 0x7a offset in data sheet */
  169. @@ -180,8 +181,11 @@
  170.  #define CLKID_CTS_AMCLK_DIV    208
  171.  #define CLKID_CTS_MCLK_I958_SEL    210
  172.  #define CLKID_CTS_MCLK_I958_DIV    211
  173. +#define CLKID_ETH_CLK_SEL  214
  174. +#define CLKID_ETH_CLK_DIV  215
  175. +#define CLKID_ETH_CLK_PHASE    216
  176.  
  177. -#define CLK_NR_CLKS        214
  178. +#define CLK_NR_CLKS        218
  179.  
  180.  /*
  181.   * include the CLKID and RESETID that have
  182. diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
  183. index bba4c4bdc166..e6750ee4a091 100644
  184. --- a/include/dt-bindings/clock/meson8b-clkc.h
  185. +++ b/include/dt-bindings/clock/meson8b-clkc.h
  186. @@ -126,5 +126,6 @@
  187.  #define CLKID_CTS_AMCLK        209
  188.  #define CLKID_CTS_MCLK_I958    212
  189.  #define CLKID_CTS_I958     213
  190. +#define CLKID_ETH_CLK      217
  191.  
  192.  #endif /* __MESON8B_CLKC_H */
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