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  1. #include <Arduino.h>
  2. #include <SPI.h>
  3.  
  4. // #define DEBUG_MODE true
  5.  
  6. enum CFREQ
  7. {
  8. CFREQ_868 = 0,
  9. CFREQ_915,
  10. CFREQ_433,
  11. CFREQ_918,
  12. CFREQ_LAST
  13. };
  14.  
  15. enum RFSTATE
  16. {
  17. RFSTATE_IDLE = 0,
  18. RFSTATE_RX,
  19. RFSTATE_TX
  20. };
  21.  
  22. #define CC1101_GDO2 11
  23. #define chipSelectPin 4
  24.  
  25. #define PAIR_TIME_OUT 5000 // ms
  26. #define RX_TIME_OUT 300 // ms
  27. #define TX_REQ_CNTS 12 // xx times tx msg will be sent before decided to skip msg ids
  28.  
  29. #define MODE_LOW_SPEED 0x01 // RF speed = 4800 bps (default is 38 Kbps)
  30. #define NUMBER_OF_FCHANNELS 10
  31. #define WRITE_BURST 0x40
  32. #define READ_SINGLE 0x80
  33. #define READ_BURST 0xC0
  34. #define CC1101_CONFIG_REGISTER READ_SINGLE
  35. #define CC1101_STATUS_REGISTER READ_BURST
  36. #define CC1101_PATABLE 0x3E // PATABLE address
  37. #define CC1101_TXFIFO 0x3F // TX FIFO address
  38. #define CC1101_RXFIFO 0x3F // RX FIFO address
  39. #define CC1101_UNKNOWNFIFO 0x7E // ? FIFO address
  40.  
  41. #define CC1101_SRES 0x30 // Reset CC1101 chip
  42. #define CC1101_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA):
  43. // Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
  44. #define CC1101_SXOFF 0x32 // Turn off crystal oscillator
  45. #define CC1101_SCAL 0x33 // Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without
  46. // setting manual calibration mode (MCSM0.FS_AUTOCAL=0)
  47. #define CC1101_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1
  48. #define CC1101_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
  49. // If in RX state and CCA is enabled: Only go to TX if channel is clear
  50. #define CC1101_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable
  51. #define CC1101_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if
  52. // WORCTRL.RC_PD=0
  53. #define CC1101_SPWD 0x39 // Enter power down mode when CSn goes high
  54. #define CC1101_SFRX 0x3A // Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states
  55. #define CC1101_SFTX 0x3B // Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states
  56. #define CC1101_SWORRST 0x3C // Reset real time clock to Event1 value
  57. #define CC1101_SNOP 0x3D // No operation. May be used to get access to the chip status byte
  58.  
  59. /**
  60. CC1101 configuration registers
  61. */
  62. #define CC1101_IOCFG2 0x00 // GDO2 Output Pin Configuration
  63. #define CC1101_IOCFG1 0x01 // GDO1 Output Pin Configuration
  64. #define CC1101_IOCFG0 0x02 // GDO0 Output Pin Configuration
  65. #define CC1101_FIFOTHR 0x03 // RX FIFO and TX FIFO Thresholds
  66. #define CC1101_SYNC1 0x04 // Sync Word, High Byte
  67. #define CC1101_SYNC0 0x05 // Sync Word, Low Byte
  68. #define CC1101_PKTLEN 0x06 // Packet Length
  69. #define CC1101_PKTCTRL1 0x07 // Packet Automation Control
  70. #define CC1101_PKTCTRL0 0x08 // Packet Automation Control
  71. #define CC1101_ADDR 0x09 // Device Address
  72. #define CC1101_CHANNR 0x0A // Channel Number
  73. #define CC1101_FSCTRL1 0x0B // Frequency Synthesizer Control
  74. #define CC1101_FSCTRL0 0x0C // Frequency Synthesizer Control
  75. #define CC1101_FREQ2 0x0D // Frequency Control Word, High Byte
  76. #define CC1101_FREQ1 0x0E // Frequency Control Word, Middle Byte
  77. #define CC1101_FREQ0 0x0F // Frequency Control Word, Low Byte
  78. #define CC1101_MDMCFG4 0x10 // Modem Configuration
  79. #define CC1101_MDMCFG3 0x11 // Modem Configuration
  80. #define CC1101_MDMCFG2 0x12 // Modem Configuration
  81. #define CC1101_MDMCFG1 0x13 // Modem Configuration
  82. #define CC1101_MDMCFG0 0x14 // Modem Configuration
  83. #define CC1101_DEVIATN 0x15 // Modem Deviation Setting
  84. #define CC1101_MCSM2 0x16 // Main Radio Control State Machine Configuration
  85. #define CC1101_MCSM1 0x17 // Main Radio Control State Machine Configuration
  86. #define CC1101_MCSM0 0x18 // Main Radio Control State Machine Configuration
  87. #define CC1101_FOCCFG 0x19 // Frequency Offset Compensation Configuration
  88. #define CC1101_BSCFG 0x1A // Bit Synchronization Configuration
  89. #define CC1101_AGCCTRL2 0x1B // AGC Control
  90. #define CC1101_AGCCTRL1 0x1C // AGC Control
  91. #define CC1101_AGCCTRL0 0x1D // AGC Control
  92. #define CC1101_WOREVT1 0x1E // High Byte Event0 Timeout
  93. #define CC1101_WOREVT0 0x1F // Low Byte Event0 Timeout
  94. #define CC1101_WORCTRL 0x20 // Wake On Radio Control
  95. #define CC1101_FREND1 0x21 // Front End RX Configuration
  96. #define CC1101_FREND0 0x22 // Front End TX Configuration
  97. #define CC1101_FSCAL3 0x23 // Frequency Synthesizer Calibration
  98. #define CC1101_FSCAL2 0x24 // Frequency Synthesizer Calibration
  99. #define CC1101_FSCAL1 0x25 // Frequency Synthesizer Calibration
  100. #define CC1101_FSCAL0 0x26 // Frequency Synthesizer Calibration
  101. #define CC1101_RCCTRL1 0x27 // RC Oscillator Configuration
  102. #define CC1101_RCCTRL0 0x28 // RC Oscillator Configuration
  103. #define CC1101_FSTEST 0x29 // Frequency Synthesizer Calibration Control
  104. #define CC1101_PTEST 0x2A // Production Test
  105. #define CC1101_AGCTEST 0x2B // AGC Test
  106. #define CC1101_TEST2 0x2C // Various Test Settings
  107. #define CC1101_TEST1 0x2D // Various Test Settings
  108. #define CC1101_TEST0 0x2E // Various Test Settings
  109.  
  110. /**
  111. Status registers
  112. */
  113. #define CC1101_PARTNUM 0x30 // Chip ID
  114. #define CC1101_VERSION 0x31 // Chip ID
  115. #define CC1101_FREQEST 0x32 // Frequency Offset Estimate from Demodulator
  116. #define CC1101_LQI 0x33 // Demodulator Estimate for Link Quality
  117. #define CC1101_RSSI 0x34 // Received Signal Strength Indication
  118. #define CC1101_MARCSTATE 0x35 // Main Radio Control State Machine State
  119. #define CC1101_WORTIME1 0x36 // High Byte of WOR Time
  120. #define CC1101_WORTIME0 0x37 // Low Byte of WOR Time
  121. #define CC1101_PKTSTATUS 0x38 // Current GDOx Status and Packet Status
  122. #define CC1101_VCO_VC_DAC 0x39 // Current Setting from PLL Calibration Module
  123. #define CC1101_TXBYTES 0x3A // Underflow and Number of Bytes
  124. #define CC1101_RXBYTES 0x3B // Overflow and Number of Bytes
  125. #define CC1101_RCCTRL1_STATUS 0x3C // Last RC Oscillator Calibration Result
  126. #define CC1101_RCCTRL0_STATUS 0x3D // Last RC Oscillator Calibration Result
  127.  
  128. //#define CC1101_DEFVAL_IOCFG2 0x29 // GDO2 Output Pin Configuration
  129. #define CC1101_DEFVAL_IOCFG2 0x0A // CHECK IF THIS IS OK!?
  130. #define CC1101_DEFVAL_IOCFG1 0x2E // GDO1 Output Pin Configuration
  131. #define CC1101_DEFVAL_IOCFG0 0x2E // HIGH IMPEDANCE 3-STATE
  132. #define CC1101_SERIAL_OUT_IOCFG0 0x0D // ASYNC SERIAL DATA OUT
  133. #define CC1101_DEFVAL_FIFOTHR 0x07 // RX FIFO and TX FIFO Thresholds
  134. #define CC1101_DEFVAL_SYNC1 0xB5 // Synchronization word, high byte
  135. #define CC1101_DEFVAL_SYNC0 0x47 // Synchronization word, low byte
  136. #define CC1101_DEFVAL_PKTLEN 0x3D // Packet Length
  137. #define CC1101_DEFVAL_PKTCTRL1 0x04 // Packet Automation Control
  138. #define CC1101_DEFVAL_PKTCTRL0 0x32 // Packet Automation Control
  139. #define CC1101_DEFVAL_ADDR 0xFF // Device Address
  140. #define CC1101_DEFVAL_CHANNR 0x00 // Channel Number
  141. #define CC1101_DEFVAL_FSCTRL1 0x08 // Frequency Synthesizer Control
  142. #define CC1101_DEFVAL_FSCTRL0 0x00 // Frequency Synthesizer Control
  143. // Carrier frequency = 868 MHz
  144. #define CC1101_DEFVAL_FREQ2_868 0x21 // Frequency Control Word, High Byte
  145. #define CC1101_DEFVAL_FREQ1_868 0x65 // Frequency Control Word, Middle Byte [modified!]
  146. #define CC1101_DEFVAL_FREQ0_868 0x8A // Frequency Control Word, Low Byte [modified!]
  147. // Carrier frequency = 902 MHz
  148. #define CC1101_DEFVAL_FREQ2_915 0x22 // Frequency Control Word, High Byte
  149. #define CC1101_DEFVAL_FREQ1_915 0xB1 // Frequency Control Word, Middle Byte
  150. #define CC1101_DEFVAL_FREQ0_915 0x3B // Frequency Control Word, Low Byte
  151. // Carrier frequency = 918 MHz
  152. #define CC1101_DEFVAL_FREQ2_918 0x23 // Frequency Control Word, High Byte
  153. #define CC1101_DEFVAL_FREQ1_918 0x4E // Frequency Control Word, Middle Byte
  154. #define CC1101_DEFVAL_FREQ0_918 0xC4 // Frequency Control Word, Low Byte
  155.  
  156. // Carrier frequency = 433 MHz
  157. #define CC1101_DEFVAL_FREQ2_433 0x10 // Frequency Control Word, High Byte
  158. #define CC1101_DEFVAL_FREQ1_433 0xA7 // Frequency Control Word, Middle Byte
  159. #define CC1101_DEFVAL_FREQ0_433 0x62 // Frequency Control Word, Low Byte
  160.  
  161. #define CC1101_DEFVAL_MDMCFG4 0x5A
  162. #define CC1101_DEFVAL_MDMCFG3 0x83 // Modem Configuration
  163. #define CC1101_DEFVAL_MDMCFG2 0x00 // Modem Configuration
  164. #define CC1101_DEFVAL_MDMCFG1 0x22 // Modem Configuration
  165. #define CC1101_DEFVAL_MDMCFG0 0xF8 // Modem Configuration
  166. #define CC1101_DEFVAL_DEVIATN 0x50 // Modem Deviation Setting
  167. #define CC1101_DEFVAL_MCSM2 0x07 // Main Radio Control State Machine Configuration
  168. //#define CC1101_DEFVAL_MCSM1 0x30 // Main Radio Control State Machine Configuration
  169. #define CC1101_DEFVAL_MCSM1 0x20 // Main Radio Control State Machine Configuration
  170. #define CC1101_DEFVAL_MCSM0 0x18 // Main Radio Control State Machine Configuration
  171. #define CC1101_DEFVAL_FOCCFG 0x1D // Frequency Offset Compensation Configuration
  172. #define CC1101_DEFVAL_BSCFG 0x1C // Bit Synchronization Configuration
  173. #define CC1101_DEFVAL_AGCCTRL2 0xC7 // AGC Control
  174. #define CC1101_DEFVAL_AGCCTRL1 0x00 // AGC Control
  175. #define CC1101_DEFVAL_AGCCTRL0 0xB2 // AGC Control
  176. #define CC1101_DEFVAL_WOREVT1 0x87 // High Byte Event0 Timeout
  177. #define CC1101_DEFVAL_WOREVT0 0x6B // Low Byte Event0 Timeout
  178. #define CC1101_DEFVAL_WORCTRL 0xFB // Wake On Radio Control
  179. #define CC1101_DEFVAL_FREND1 0xB6 // Front End RX Configuration
  180. #define CC1101_DEFVAL_FREND0 0x17 // Front End TX Configuration
  181. #define CC1101_DEFVAL_FSCAL3 0xE9 // Frequency Synthesizer Calibration
  182. #define CC1101_DEFVAL_FSCAL2 0x2A // Frequency Synthesizer Calibration
  183. #define CC1101_DEFVAL_FSCAL1 0x00 // Frequency Synthesizer Calibration
  184. #define CC1101_DEFVAL_FSCAL0 0x1F // Frequency Synthesizer Calibration
  185. #define CC1101_DEFVAL_RCCTRL1 0x41 // RC Oscillator Configuration
  186. #define CC1101_DEFVAL_RCCTRL0 0x00 // RC Oscillator Configuration
  187. #define CC1101_DEFVAL_FSTEST 0x59 // Frequency Synthesizer Calibration Control
  188. #define CC1101_DEFVAL_PTEST 0x7F // Production Test
  189. #define CC1101_DEFVAL_AGCTEST 0x3F // AGC Test
  190. #define CC1101_DEFVAL_TEST2 0x81 // Various Test Settings
  191. #define CC1101_DEFVAL_TEST1 0x35 // Various Test Settings
  192. #define CC1101_DEFVAL_TEST0 0x09 // Various Test Settings
  193.  
  194. /**
  195. Alias for some default values
  196. */
  197. #define CCDEF_CHANNR CC1101_DEFVAL_CHANNR
  198. #define CCDEF_SYNC0 CC1101_DEFVAL_SYNC0
  199. #define CCDEF_SYNC1 CC1101_DEFVAL_SYNC1
  200. #define CCDEF_ADDR CC1101_DEFVAL_ADDR
  201.  
  202. /**
  203. Macros
  204. */
  205. // Read CC1101 Config register
  206. #define readConfigReg(regAddr) readReg(regAddr, CC1101_CONFIG_REGISTER)
  207. // Read CC1101 Status register
  208. #define readStatusReg(regAddr) readReg(regAddr, CC1101_STATUS_REGISTER)
  209. // Enter Rx state
  210. //#define setRxState() cmdStrobe(CC1101_SRX)
  211. // Enter Tx state
  212. //#define setTxState() cmdStrobe(CC1101_STX)
  213. // Enter IDLE state
  214. #define setIdleState() cmdStrobe(CC1101_SIDLE)
  215. // Flush Rx FIFO
  216. #define flushRxFifo() cmdStrobe(CC1101_SFRX)
  217. // Flush Tx FIFO
  218. #define flushTxFifo() cmdStrobe(CC1101_SFTX)
  219. // Disable address check
  220. #define disableAddressCheck() writeReg(CC1101_PKTCTRL1, 0x04)
  221. // Enable address check
  222. #define enableAddressCheck() writeReg(CC1101_PKTCTRL1, 0x06)
  223. // Disable CCA
  224. #define disableCCA() writeReg(CC1101_MCSM1, 0)
  225. // Enable CCA
  226. #define enableCCA() writeReg(CC1101_MCSM1, CC1101_DEFVAL_MCSM1)
  227. // PATABLE values
  228. #define PA_LowPower 0x60
  229. #define PA_LongDistance 0xC0
  230.  
  231. /**
  232. Class: CC1101
  233.  
  234. Description:
  235. CC1101 interface
  236. */
  237. class CC1101
  238. {
  239. private:
  240. void writeBurstReg(uint8_t regAddr, uint8_t* buffer, uint8_t len);
  241. void readBurstReg(uint8_t * buffer, uint8_t regAddr, uint8_t len);
  242. void setRegsFromEeprom(void);
  243. uint8_t *manchester_decode(uint8_t rx_buff[], uint8_t len, uint8_t *rx_payload);
  244. uint8_t *manchester_encode(uint8_t tx_buff[], uint8_t len, uint8_t *test_arr);
  245. uint8_t transmit_data(uint8_t payload[], uint8_t len);
  246. uint8_t calc_crc(uint8_t dataframe[], uint8_t len);
  247.  
  248. enum codes_enum
  249. {
  250. fan_speed,
  251. indoor_hum,
  252. fan_info,
  253. bypass_mode
  254. };
  255.  
  256. struct codes
  257. {
  258. uint16_t code_id;
  259. bool rx_flag;
  260. };
  261.  
  262. codes msg_id[3];
  263.  
  264. public:
  265.  
  266. struct datapoints
  267. {
  268. uint8_t fan_speed;
  269. uint8_t indoor_humidity;
  270. uint8_t outdoor_humidity;
  271. uint16_t exhaust_temperature;
  272. uint16_t supply_temperature;
  273. uint16_t indoor_temperature;
  274. uint16_t outdoor_temperature;
  275. uint8_t bypass_position;
  276. uint8_t bypass_mode;
  277. uint8_t exhaust_fanspeed;
  278. uint8_t supply_fanspeed;
  279. uint16_t exhaust_flow;
  280. uint16_t supply_flow;
  281. uint8_t address[6];
  282. };
  283.  
  284. datapoints new_fan_state;
  285. datapoints current_fan_state;
  286.  
  287. CC1101(void);
  288. void cmdStrobe(uint8_t cmd);
  289. void wakeUp(void);
  290. bool tx_fanspeed(uint8_t fan_speed);
  291. bool set_bypass(uint8_t bypass_mode);
  292. uint8_t request_fan_state(void);
  293. uint8_t readReg(uint8_t regAddr, uint8_t regType);
  294. void writeReg(uint8_t regAddr, uint8_t value);
  295. void config_registers(void);
  296. void reset(void);
  297. void init(void);
  298. void set_rx_mode(void);
  299. bool clone_mode(void);
  300. void setCarrierFreq(uint8_t freq);
  301. void setPowerDownState();
  302. void setRxState(void);
  303. void setTxState(void);
  304.  
  305. };
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