Divider #2

module divider(

   input clk,
   input rst,
   input [3:0] inA,
   input [3:0] inB,
   output [4:0] rem,
   output [3:0] quot

);

reg [1:0] q;
reg [3:0] A;
reg [3:0] B;
reg [4:0] P;
reg [2:0] k;
reg [3:0] cnt;

reg[3:0] state,state_nxt;
localparam s0=3'd0, s1=3'd1,s2=3'd2,s3=3'd3;

always @(posedge clk or posedge rst)
begin
    if (rst) begin
      state <= s0;
      A <= inA;
      B <= inB;
      q <= 1'b0;
      k <= 3'b0;
      P <= 5'b0;
      cnt <= 4'd3;
   end
   else begin
      case(state)
        s0:
           if(B[3] == 1'd0)
              begin
                  {P[4:0], A[3:0], B[3:0]} <= {P[3:0],A[3:0],B[3:0],1'b0};
                  k <= k + 1'b1;
                  state <= s0;
              end
           else
              state <= s1;
        s1:
        if(cnt > 0)
           case({A[3],A[2],A[1]})
              3'd0,3'd7: begin
                  q <= 2'd0;
                  {P, A} <= {P[3:0],A,1'b0};
                  cnt <= cnt - 1;
                  state <= s1;
              end
              default:
                 begin
                     if(P[4] == 1) begin
                        q <= 2'b01;
                        {P, A} <= {P[3:0],A,1'b0};
                        P <= P + {1'b0,B};
                        cnt <= cnt - 1;
                        state <= s1;
                     end
                     else
                     begin
                        q <= 2'b10;
                        {P, A} <= {P[3:0],A[3:1],1'b0};
                        P <= P - {1'b0,B};
                        cnt <= cnt - 1;
                        state <= s1;
                     end
                 end
           endcase
       else state <= s2;
       s2:
          begin
              if(P[4] == 1)
              begin
                 P <= P + {1'b0,B};
                 A <= A - 1'b1;
                 //P <= P << k;
              end
          end
  endcase
   end
end

assign rem = P[3:0];
assign quot = A;

endmodule