tsuckow

ThermoProcessor

Mar 13th, 2011
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  1. module ThermoProcessor
  2. (
  3.     clock,
  4.     rst,
  5.     ooo
  6. );
  7.  
  8. input clock, rst;
  9. output ooo;
  10.  
  11.  
  12.  
  13.  
  14. //
  15. //Processor
  16. wire sig_tick;
  17.  
  18. //Wishbone Common
  19. wire wb_clk = clock;
  20. wire wb_rst = rst;
  21.  
  22. // Instruction master i/f wires
  23. wire [31:0] wb_rim_adr_o;
  24. wire        wb_rim_cyc_o;
  25. wire [31:0] wb_rim_dat_i;
  26. wire [31:0] wb_rim_dat_o;
  27. wire [3:0]  wb_rim_sel_o;
  28. wire        wb_rim_ack_i;
  29. wire        wb_rim_err_i;
  30. wire        wb_rim_rty_i;
  31. wire        wb_rim_we_o;
  32. wire        wb_rim_stb_o;
  33. wire [2:0]  wb_rim_cti_o;
  34. wire        wb_rim_bte_o;
  35.  
  36. // Data master i/f wires
  37. wire [31:0] wb_rdm_adr_o;
  38. wire        wb_rdm_cyc_o;
  39. wire [31:0] wb_rdm_dat_i;
  40. wire [31:0] wb_rdm_dat_o;
  41. wire [3:0]  wb_rdm_sel_o;
  42. wire        wb_rdm_ack_i;
  43. wire        wb_rdm_err_i;
  44. wire        wb_rdm_rty_i;
  45. wire        wb_rdm_we_o;
  46. wire        wb_rdm_stb_o;
  47. wire [2:0]  wb_rdm_cti_o;
  48. wire        wb_rdm_bte_o;
  49.  
  50. // Debug i/f wires
  51. wire [3:0]  dbg_lss;
  52. wire [1:0]  dbg_is;
  53. wire [10:0] dbg_wp;
  54. wire        dbg_bp;
  55. wire [31:0] dbg_dat_dbg;
  56. wire [31:0] dbg_dat_risc;
  57. wire [31:0] dbg_adr;
  58. wire        dbg_ewt;
  59. wire        dbg_stall = 1'b0;
  60. wire [2:0]  dbg_op;
  61.  
  62. or1200_top proc
  63. (
  64.  
  65.     .rst_i      ( wb_rst ),
  66.     .clk_i      ( wb_clk ),
  67.  
  68.     .clmode_i   ( 2'b00 ), // 1 to 1 clock?
  69.  
  70.     // WISHBONE Instruction Master
  71.     .iwb_clk_i  ( wb_clk ),
  72.     .iwb_rst_i  ( wb_rst ),
  73.     .iwb_cyc_o  ( wb_rim_cyc_o ),
  74.     .iwb_adr_o  ( wb_rim_adr_o ),
  75.     .iwb_dat_i  ( wb_rim_dat_i ),
  76.     .iwb_dat_o  ( wb_rim_dat_o ),
  77.     .iwb_sel_o  ( wb_rim_sel_o ),
  78.     .iwb_ack_i  ( wb_rim_ack_i ),
  79.     .iwb_err_i  ( wb_rim_err_i ),
  80.     .iwb_rty_i  ( wb_rim_rty_i ),
  81.     .iwb_we_o   ( wb_rim_we_o  ),
  82.     .iwb_stb_o  ( wb_rim_stb_o ),
  83.     .iwb_cti_o  ( wb_rim_cti_o ),
  84.     .iwb_bte_o  ( wb_rim_bte_o ),
  85.  
  86.     // WISHBONE Data Master
  87.     .dwb_clk_i  ( wb_clk ),
  88.     .dwb_rst_i  ( wb_rst ),
  89.     .dwb_cyc_o  ( wb_rdm_cyc_o ),
  90.     .dwb_adr_o  ( wb_rdm_adr_o ),
  91.     .dwb_dat_i  ( wb_rdm_dat_i ),
  92.     .dwb_dat_o  ( wb_rdm_dat_o ),
  93.     .dwb_sel_o  ( wb_rdm_sel_o ),
  94.     .dwb_ack_i  ( wb_rdm_ack_i ),
  95.     .dwb_err_i  ( wb_rdm_err_i ),
  96.     .dwb_rty_i  ( wb_rdm_rty_i ),
  97.     .dwb_we_o   ( wb_rdm_we_o  ),
  98.     .dwb_stb_o  ( wb_rdm_stb_o ),
  99.     .dwb_cti_o  ( wb_rdm_cti_o ),
  100.     .dwb_bte_o  ( wb_rdm_bte_o ),
  101.  
  102.     // Debug
  103.     .dbg_stall_i( dbg_stall ),
  104.     .dbg_dat_i  ( dbg_dat_dbg ),
  105.     .dbg_adr_i  ( dbg_adr ),
  106.     .dbg_ewt_i  ( 1'b0 ),
  107.     .dbg_lss_o  ( dbg_lss ),
  108.     .dbg_is_o   ( dbg_is ),
  109.     .dbg_wp_o   ( dbg_wp ),
  110.     .dbg_bp_o   ( dbg_bp ),
  111.     .dbg_dat_o  ( dbg_dat_risc ),
  112.    
  113.     //Not all are accounted for ?
  114.     //dbg_stall_i, dbg_ewt_i,   dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
  115.     //dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
  116.  
  117.     // Power Management
  118.     .pm_clksd_o ( ),
  119.     .pm_cpustall_i  ( 1'b0 ),
  120.     .pm_dc_gate_o   ( ),
  121.     .pm_ic_gate_o   ( ),
  122.     .pm_dmmu_gate_o ( ),
  123.     .pm_immu_gate_o ( ),
  124.     .pm_tt_gate_o   ( ),
  125.     .pm_cpu_gate_o  ( ),
  126.     .pm_wakeup_o    ( ),
  127.     .pm_lvolt_o ( ),
  128.  
  129.     // Interrupts
  130.     .pic_ints_i ( 20'b0 ),
  131.  
  132.     .sig_tick(sig_tick)
  133. );
  134.  
  135. //
  136. //Instruction Wishbone Bus
  137. rom_wb
  138. #(
  139.     .data_width (32),
  140.     .addr_width (13)
  141. )
  142. INST_ROM
  143. (
  144.     .dat_i(wb_rim_dat_o),
  145.     .dat_o(wb_rim_dat_i),
  146.     .adr_i(wb_rim_adr_o),
  147.     .we_i (wb_rim_we_o),
  148.     .sel_i(wb_rim_sel_o),
  149.     .cyc_i(wb_rim_cyc_o),
  150.     .stb_i(wb_rim_stb_o),
  151.     .ack_o(wb_rim_ack_i),
  152.     .cti_i(wb_rim_cti_o),
  153.     .clk_i(wb_clk),
  154.     .rst_i(wb_rst)
  155. );
  156.  
  157. assign wb_rdm_ack_i = 1'b0;
  158. assign wb_rdm_rty_i = 1'b1;
  159. assign wb_rdm_err_i = 1'b0;
  160. assign wb_rim_rty_i = 1'b0;
  161. assign wb_rim_err_i = 1'b0;
  162.  
  163. assign ooo = wb_rim_cyc_o;
  164.  
  165. endmodule
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