APB_UVM_TB_TOP

module apb_tb_top;

    import uvm_pkg::*;
    `include "uvm_macros.svh"

    import apb_pkg::*;

    // Clock generation
    bit PCLK;
    parameter CYCLE = 10;

    initial begin
        forever #(CYCLE/2) PCLK = ~PCLK;
    end

    // Parameters
    parameter SET_DATA_WIDTH = 8;
    parameter SET_ADDR_WIDTH = 8;

    // Wires
    logic PWRITE_w;
    logic [(SET_DATA_WIDTH-1):0] PWDATA_w;
    logic [(SET_ADDR_WIDTH-1):0] PADDR_w;
    logic PREADY_w;
    logic PSLVERR_w;
    logic [(SET_DATA_WIDTH-1):0] PRDATA_w;

    // Interface instantiation
    apb_mst_intf mst_if0 (PCLK);

    apb_slv_intf #(.DATA_WIDTH(SET_DATA_WIDTH), .ADDR_WIDTH(SET_ADDR_WIDTH)) slv_if0 (.PCLK(PCLK));
    // Connecting the slave intf with the wires
    assign slv_if0.PWRITE   = PWRITE_w;
    assign slv_if0.PREADY   = PREADY_w;

    apb_slv_intf #(.DATA_WIDTH(SET_DATA_WIDTH), .ADDR_WIDTH(SET_ADDR_WIDTH)) slv_if1 (.PCLK(PCLK));
    // Connecting the slave intf with the wires
    assign slv_if1.PWRITE   = PWRITE_w;
    assign slv_if1.PREADY   = PREADY_w;

    // DUV Instantiation
    apb_master #(.DATA_WIDTH(SET_DATA_WIDTH), .ADDR_WIDTH(SET_ADDR_WIDTH)) DUV (
        .PCLK(PCLK),
        .PRESETN(mst_if0.PRESETN),
        .BWRITE(mst_if0.BWRITE),
        .BWDATA(mst_if0.BWDATA),
        .BADDR(mst_if0.BADDR),
        .BSEL0(mst_if0.BSEL0),
        .BSEL1(mst_if0.BSEL1),
        .PENABLE(PENABLE_w),
        .PWRITE(PWRITE_w),
        .PWDATA(PWDATA_w),
        .PADDR(PADDR_w),
        .PSEL0(slv_if0.PSEL),
        .PSEL1(slv_if1.PSEL),
        .PREADY(PREADY_w),
        .PSLVERR(PSLVERR_w),
        .PRDATA(PRDATA_w)
    );

    initial begin
        run_test();
    end

endmodule: apb_tb_top