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-- Company:
-- Engineer:
--
-- Create Date: 04/16/2019 01:02:49 PM
-- Design Name:
-- Module Name: inm_float - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity inm_float is
    Port ( clk   : in STD_LOGIC;
           x     : in STD_LOGIC_VECTOR (31 downto 0);
           y     : in STD_LOGIC_VECTOR (31 downto 0);
           rst   : in STD_LOGIC;
           start : in STD_LOGIC;

           r : out STD_LOGIC_VECTOR (31 downto 0));
end inm_float;

architecture Behavioral of inm_float is

signal rez_m  : std_logic_vector (51 downto 0) := (others => '0');
signal term   : std_logic := '0';
signal plus_x : std_logic_vector (25 downto 0) := (others => '0');
signal plus_y : std_logic_vector (25 downto 0) := (others => '0');
signal do_op  : std_logic := '0';

begin

    process(x,y)
    begin
        if (x = x"00000000" or y = x"00000000") then
            do_op <= '0';
            r <= x"00000000";
        elsif (term = '1') then
            do_op <= '0';
        else
            do_op <= '1';
        end if;
    end process;

    plus_x <= "01" & x (23 downto 0);
    plus_y <= "01" & y (23 downto 0);

    INM_MANTISE: entity WORK.inm_gen generic map (n => 26) port map(
                Clk   => clk,
                Rst   => rst,
                Start => do_op,
                X     => plus_x,
                Y     => plus_y,
                A     => rez_m,
                Term  => term );



end Behavioral;