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  1.  
  2. # NiPoGi AK2PLUS AMI BIOS
  3.  
  4. Main menu has the following items
  5.  
  6. - Main
  7. - Advanced
  8. - Chipset
  9. - Security
  10. - Boot
  11. - Save & Exit
  12.  
  13. Options preceded by an asterisk '*' are read-only. Options preceded by the '>' character open
  14. sub-tabs. Some options enable other pages depending on its values.
  15.  
  16.  
  17. **Main**
  18.  
  19. Option | Value | Description
  20. --------------------------------|-----------------------|-------------------------------------------
  21. **BIOS Information** | |
  22. | |
  23. * BIOS Vendor | American Megatrends |
  24. * Core Version | 5.26 |
  25. * Compliancy | UEFI 2.8; PI 1.7 |
  26. * Project Version | AN3 0.01 x64 |
  27. * Build Date and Time | 10/09/2023 13:45:53 |
  28. * Access Level | Administrator |
  29. | |
  30. **Processor Information** | |
  31. | |
  32. * Name | Alder Lake ULX |
  33. * Type | Intel(R) N100 |
  34. * Total Memory | 16384 MB |
  35. * Memory Frequency | 2667 MHz |
  36. | |
  37. System Language | [English] | Choose the System default Language
  38. System Date | [Thu 02/20/2025] | Set the Date. Use Tab to switch between
  39. | | Date elements. Default Ranges:
  40. | | Year: 1998- 9999,
  41. | | Months: 1-12,
  42. | | Days: Dependent on Month.
  43. | | Range of Years may vary.
  44. System Time | [07:21:04] | Set the Time. Use Tab to swith between
  45. | | Time elements.
  46.  
  47.  
  48. **Advanced**
  49.  
  50. Option | Value | Description
  51. --------------------------------|-----------------------|-------------------------------------------
  52. > CPU Information | |
  53. > Power & Performance | |
  54. | |
  55. > Realtek PCIe GBE Family | |
  56. Controller | |
  57. (MAC:56:1D:EF:3A:EC:76) | |
  58.  
  59.  
  60. **Advanced -> CPU Information**
  61.  
  62. Option | Value | Description
  63. --------------------------------|-----------------------|-------------------------------------------
  64. **CPU Configuration** | |
  65. | |
  66. > Efficient-core Information | | Display the E-core Information
  67. *> Performance-core Information| |
  68. | |
  69. * ID | 0xB06E0 |
  70. * Brand String | Intel(R) N100 |
  71. * VMX | Supported |
  72. * SMX/TXT | Not Supported |
  73. | |
  74. C6DRAM | [Enabled] | Enable/Disable moving of DRAM contents to
  75. | | PRM memory when CPU is in C6 state
  76. CPU Flex Ratio Override | [Disabled] | Enable/Disable CPU Flex Ratio Programming
  77. * CPU Flex Ratio Settings | [8] | This value must be between Max Efficiency
  78. | | Ratio (LFM) and Maximum non-turbo ratio
  79. | | set by Hardware (HFN)
  80. Hardware Prefetcher | [Enabled] | To turn on/off the MLC streamer prefetcher
  81. Adjacent Cache Line Prefetch | [Enabled] | To turn on/off prefetching of adjacent
  82. | | cache line
  83. Intel (VMX) Virtualization | [Enabled] | When enabled, a VMM can utilize the
  84. Technology | | additional hardware capabilities provided
  85. | | by Vanderpool Technology
  86. PECI | [Enabled] | Enable/Disable PECI
  87. AVX | [Enabled] | Enable/Disable the Avx 2 Instructions.
  88. | | This is applicable for Performance-core
  89. | | only
  90. Active Efficient-cores | [All] | Number of E-cores to enable in each
  91. | | processor package. Note: Number of Cores
  92. | | and E-cores are looked at together. When
  93. | | both are {0,0}, Pcode will enable all
  94. | | cores.
  95. | | Valid options: [All], [3], [2], [1],
  96. | | [0].
  97. BIST | [Disabled] | Enable/Disable BIST (Build-In Self Test)
  98. | | on reset
  99. AP threads Idle Manner | [MWAIT Loop] | AP threads Idle Manner for waiting signal
  100. | | to run.
  101. | | Valid options: [HALT Loop], [MWAIT Loop],
  102. | | [RUN Loop]
  103. AES | [Enabled] | Enable/Disable AES (Advanced Encryption
  104. | | Standard)
  105. MachineCheck | [Enabled] | Enable/Disable Machine Check
  106. MonitorMWAIT | [Enabled] | Enable/Disable MonitorMWAIT, if Disable
  107. | | MonitorMWAIT, the AP threads Idle Manner
  108. | | should not set in MWAIT Loop.
  109. > CPU SMM Enhancement | | CPU SMM Enhancement
  110.  
  111.  
  112. **Advanced -> CPU Information -> Efficient-core Information**
  113.  
  114. Option | Value | Description
  115. --------------------------------|-----------------------|-------------------------------------------
  116. **Efficient-core Information** | |
  117. | |
  118. * L1 Data Cache | 32 kB x 4 |
  119. * L1 Instruction Cache | 64 kB x 4 |
  120. * L2 Cache | 2048 kB |
  121. * L3 Cache | 6 MB |
  122.  
  123.  
  124. **Advanced -> CPU Information -> CPU SMM Enhancement**
  125.  
  126. Option | Value | Description
  127. --------------------------------|-----------------------|-------------------------------------------
  128. **CPU SMM Enhancement** | |
  129. | |
  130. SMM Use Delay Indication | [Enabled] | Enable/Disable usage of SMM_DELAYED MSR
  131. | | for MP sync in SMI
  132. SMM Use Block Indication | [Enabled] | Enable/Disable usage of SMM_BLOCKED MSR
  133. | | for MP sync in SMI
  134. SMM Use SMM en-US Indication | [Enabled] | Enable/Disable usage of SMM_ENABLE MSR for
  135. | | MP sync in SMI
  136.  
  137.  
  138. **Advanced -> Power & Performance**
  139.  
  140. Option | Value | Description
  141. --------------------------------|-----------------------|-------------------------------------------
  142. **Power & Performance** | |
  143. | |
  144. > CPU - Power Management | | CPU - Power Management Control Options
  145. Control | |
  146. > GT - Power Management | | GT - Power Management Control Options
  147. Control | |
  148.  
  149.  
  150. **Advanced -> Power & Performance -> CPU - Power Management Control**
  151.  
  152. Option | Value | Description
  153. --------------------------------|-----------------------|-------------------------------------------
  154. **CPU - Power Management | |
  155. Control** | |
  156. | |
  157. Boot Performance Mode | [Turbo Performance] | Select the performance state that the BIOS
  158. | | will set starting from reset vector.
  159. | | Valid options: [Max Battery],
  160. | | [Max Non-Turbo Performance],
  161. | | [Turbo Performance]
  162. Intel(R) SpeedStep(tm) | [Enabled] | Allow more than two frequencies ranges to
  163. | | be supported
  164. Race To Halt | [Enabled] | Enable/DisableRace To Halt feature. RTH
  165. | | will dynamically increase CPU frequency in
  166. | | order to enter pkg C-State faster to
  167. | | reduce overall power. (RTH is controlled
  168. | | through MSR 1FC bit 20)
  169. Intel(R) Speed Shift | [Enabled] | Enable/Disable Intel(R) Speed Shift
  170. Technology | | Technology support. Enabling will expose
  171. | | the CPPC v2 interface to allow for
  172. | | hardware controlled P-states.
  173. Per Core P State OS control | [Enabled] | Enable/Disable Per Core P state OS control
  174. mode | | mode. Disabling will set Bit 31 = 1
  175. | | command 0x06. When set, the highest core
  176. | | request is used for all other core
  177. | | requests.
  178. HwP Autonomous Per Core P | [Enabled] | Disable Autonomous PCPS (Bit 30 = 1,
  179. State | | command 0x11) Autonomous will request the
  180. | | same value for all cores all the time.
  181. | | Enable PCPS (default Bit 30 = 0, command
  182. | | 0x11)
  183. HwP Autonomous EPP Grouping | [Enabled] | Enable EPP Grouping (default Bit 29 = 0,
  184. | | command 0x11) Autonomous will request the
  185. | | same values for all cores with same EPP.
  186. | | Disable EPP grouping (Bit 29 = 1, command
  187. | | 0x11) autonomous will not necessarily
  188. | | request same values for all cores with
  189. | | same EPP.
  190. EPB override over PECI | [Disabled] | Enable/Disable EPB override over PECI.
  191. | | Enable by sending pcode command 0x2B,
  192. | | subcommand 0x03 to 1. This will allow OOB
  193. | | EPB PECI override control
  194. HwP Lock | [Enabled] | Enable/Disable HWP Lock support in Misc
  195. | | Power Management MSR.
  196. HDC Control | [Enabled] | This option allow HDC configuration.
  197. | | Disabled: Disable HDC. Enable: Can be
  198. | | enabled by OS if OS native support is
  199. | | available
  200. Turbo Mode | [Enabled] | Enable/Disable processor Turbo Mode
  201. | | (require EMTTM enabled too). AUTO means
  202. | | enabled
  203. > View/Configure Turbo | | View/Configure Turbo Options
  204. Options | |
  205. > CPU VR Settings | | CPU VR Settings
  206. Platform PL1 Enable | [Enabled] | Enable/Disable Platform Power Limit 1
  207. | | programming. If this option is enabled, it
  208. | | activates the PL1 value to be used by the
  209. | | processor to limit the average power of
  210. | | given time window.
  211. Platform PL1 Power | [15000] | Platform Limit 1 Power in Milli
  212. | | Watts/Percent. BIOS will round to the
  213. | | nearest 1/8W when programming. Any value
  214. | | can be programmed between Max and Min
  215. | | Power Limits (specified by
  216. | | PACKAGE_POWER_SKU_MSR). For example, if
  217. | | 12.50W, enter 12500, if 12% enter 12000,
  218. | | if 50% enter 50000. This setting will act
  219. | | as the new PL1 value fot the Package RAPL
  220. | | algorithm.
  221. Platform PL1 Time Window | [0] | Platform Power Limit 1 Time Window value
  222. | | in seconds. The value may vary from 0 to
  223. | | 128, 0 = default values. Indicate the time
  224. | | window over wich Platform Processor Base
  225. | | Power (TDP) value should be maintained.
  226. Platform PL2 Enable | [Enabled] | Enable/Disable Platform Power Limit 2
  227. | | programming. If this option is disabled,
  228. | | BIOS will program the default values for
  229. | | Platform Power Limit 2.
  230. Platform PL2 Power | [15000] | Platform Poer Limit 2 Power in Milli
  231. | | Watts/Percent. BIOS will round to the
  232. | | nearest 1/8W when programming. Any value
  233. | | can be programmed between Max and Min
  234. | | Power Limits (specified by
  235. | | PACKAGE_POWER_SKU_MSR). For example, if
  236. | | 12.50W, enter 12500, if 12%, enter 12000,
  237. | | if 50%, enter 50000. This setting will act
  238. | | as the new PL2 value for the Package RAPL
  239. | | algorithm.
  240. Power Limit 4 Override | [Disabled] | Enable/Disable Power Limit 4 override. If
  241. | | this option is disabled, BIOS will leave
  242. | | the default values for Power Limit 4.
  243. C states | [Enabled] | Enable/Disable CPU Power Management.
  244. | | Allows CPU to go to C states when it's not
  245. | | 100% utilized.
  246. Enhanced C-states | [Enabled] | Enable/Disable C1E. When enabled, CPU will
  247. | | switch to minimum speed when all cores
  248. | | enter C-State
  249. C-State Auto Demotion | [C1] | Configure C-State Auto Demotion.
  250. | | Valid options: [Disabled], [C1].
  251. C-State Un-demotion | [C1] | Configure C-State Un-demotion.
  252. | | Valid options: [Disabled], [C1].
  253. Package C-State Demotion | [Enabled] | Package C-State Demotion
  254. Package C-State Un-demotion | [Enabled] | Package C-State Un-demotion
  255. CState Pre-Wake | [Enabled] | Disable - Sets bit 30 of POWER_CTL
  256. | | MSR(0x1FC) to 1 to disable the Cstate
  257. | | Pre-Wake.
  258. IO MWAIT Redirection | [Disabled] | When set, will map IO_read instructions
  259. | | sent to IO registers
  260. | | PMG_IO_BASE_ADDRBASE+offset to
  261. | | MWAIT(offset)
  262. Package C State Limit | [Auto] | Maximum Package C State Limit Setting. Cpu
  263. | | default: Leaves to factory default value.
  264. | | Auto: Initializes to deepest available
  265. | | Package C State Limit.
  266. | | Valid options: [C0/C1], [C2], [C3], [C6],
  267. | | [C7], [C7S], [C8], [C9], [C10],
  268. | | [Cpu Default], [Auto].
  269. **C6/C7 Short Latency Control | |
  270. (MSR 0x60B)** | |
  271. | |
  272. Time Unit | [1024 ns] | Unit of measurement for IRTL value - bits
  273. | | [12:10].
  274. | | Valid options: [1 ns], [32 ns], [1024 ns],
  275. | | [32768 ns], [1048576 ns], [33554432 ns].
  276. Latency | [0] | Interrupt Response Time Limit value - bits
  277. | | [9:0], Enter 0-1023.
  278. **C6/C7 Long Latency Control | |
  279. (MSR 0x60C)** | |
  280. | |
  281. Time Unit | [1024 ns] | Unit of measurement for IRTL value - bits
  282. | | [12:10].
  283. | | Valid options: [1 ns], [32 ns], [1024 ns],
  284. | | [32768 ns], [1048576 ns], [33554432 ns].
  285. Latency | [0] | Interrupt Response Time Limit value - bits
  286. | | [9:0], Enter 0-1023.
  287. **C8 Latency Control (MSR | |
  288. 0x633)** | |
  289. | |
  290. Time Unit | [1024 ns] | Unit of measurement for IRTL value - bits
  291. | | [12:10].
  292. | | Valid options: [1 ns], [32 ns], [1024 ns],
  293. | | [32768 ns], [1048576 ns], [33554432 ns].
  294. Latency | [0] | Interrupt Response Time Limit value - bits
  295. | | [9:0], Enter 0-1023.
  296. **C9 Latency Control (MSR | |
  297. 0x634)** | |
  298. | |
  299. Time Unit | [1024 ns] | Unit of measurement for IRTL value - bits
  300. | | [12:10].
  301. | | Valid options: [1 ns], [32 ns], [1024 ns],
  302. | | [32768 ns], [1048576 ns], [33554432 ns].
  303. Latency | [0] | Interrupt Response Time Limit value - bits
  304. | | [9:0], Enter 0-1023.
  305. | |
  306. **C10 Latency Control (MSR | |
  307. 0x635)** | |
  308. | |
  309. Time Unit | [1024 ns] | Unit of measurement for IRTL value - bits
  310. | | [12:10].
  311. | | Valid options: [1 ns], [32 ns], [1024 ns],
  312. | | [32768 ns], [1048576 ns], [33554432 ns].
  313. Latency | [0] | Interrupt Response Time Limit value - bits
  314. | | [9:0], Enter 0-1023.
  315. Thermal Monitor | [Enabled] | Enable/Disable Thermal Monitor
  316. Interrupt Redirection Mode | [Fixed Priority] | Interrupt Redirection Mode Select for
  317. Selection | | Logical Interrupts.
  318. | | Valid options: [Fixed Priority],
  319. | | [Round robin], [Hash Vector], [No Change].
  320. Timed MWAIT | [Disabled] | Enable/Disable Timed MWAIT Support
  321. > Custom P-state Table | | Add Custom P-state Table
  322. EC Turbo Control Mode | [Disabled] | Enable/Disable EC Turbo Control mode
  323. Energy Performance Gain | [Disabled] | Enable/Disable Energy Performance Gain
  324. EPG DIMM Idd3N | [26] | Active standby current (Idd3N) in
  325. | | milliamps from datasheet. Must be
  326. | | calculated on a per DIMM basis.
  327. EPG DIMM Idd3P | [11] | Active power-down current (Idd3P) in
  328. | | milliamps from datasheet. Must be
  329. | | calculated on a per DIMM basis.
  330. > Power Limit 3 Settings | | Power Limit 3 Settings
  331. > CPU Lock Configuration | | CPU Lock Configuration
  332.  
  333.  
  334. **Advanced -> Power & Performance -> CPU - Power Management Control ->
  335. View/Configure Turbo Options**
  336.  
  337. Option | Value | Description
  338. --------------------------------|-----------------------|-------------------------------------------
  339. **Current Turbo Settings** | |
  340. | |
  341. * Max Turbo Power Limit | [4095.875] |
  342. * Min Turbo Power Limit | [0.0] |
  343. * Package TDP Limit | [6.0] |
  344. * Power Limit 1 | [15.0] |
  345. * Power Limit 2 | [15.0] |
  346. | |
  347. > Turbo Ratio Limit Options | | View/Configure Turbo Ratio Limit Options
  348. Energy Efficient P-state | [Enabled] | Enable/Disable Energy Efficient P-state
  349. | | feature. When set to 0, will disable
  350. | | access to ENERGY_PERFORMANCE_BIAS MSR and
  351. | | CPUID Function 6 ECX[3] will read 0
  352. | | indicating no support for Energy Efficient
  353. | | policy setting. When set to 1 will enable
  354. | | access to ENERGY_PERFORMANCE_BIAS MSR 1B0H
  355. | | and CPUID Function 6 ECX[3] will read 1
  356. | | indicating Energy Efficient policy setting
  357. | | is supported.
  358. Package Power Limit MSR Clock | [Disabled] | Enable/Disable locking of Package Power
  359. | | Limit settings. When enabled,
  360. | | PACKAGE_POWER_LIMIT MSR will be locked and
  361. | | a reset will be required to unlock the
  362. | | register.
  363. Power Limit 1 Override | [Enabled] | Enable/Disable Power Limit 1 Override. If
  364. | | this option is disabled, BIOS will program
  365. | | the default values for Power Limit 1 and
  366. | | Power Limit 1 Time Window.
  367. Power Limit 1 | [15000] | Power Limit 1 in milli Watts. BIOS will
  368. | | round to neares 1/8W when programming,
  369. | | 0 = no custom override. For 12.50W, enter
  370. | | 12500. Overclocking SKU: value must be
  371. | | between Max and Min Power Limits
  372. | | (specified by PACKAGE_POWER_SKU_MSR).
  373. | | Other SKUs: This value must be between Min
  374. | | Power Limit and Processor Base Power (TDP)
  375. | | Limit. If value is 0, BIOS will program
  376. | | Processor Base Power (TDP) value.
  377. Power Limit 1 Time Window | [0] | Power Limit 1 Time Window value in
  378. | | seconds. The value may vary from 0 to 128,
  379. | | 0 = default value (28 sec for Mobile and 8
  380. | | sec for Desktop). Defines time window
  381. | | which Processor Base Power (TDP) value
  382. | | should be maintained.
  383. Power Limit 2 Override | [Enabled] | Enable/Disable Power Limit 2 Overrride. If
  384. | | this option is disabled, BIOS will program
  385. | | the default values for Power Limit 2.
  386. Power Limit 2 | [15000] | Power Limit 2 value in milli Watts. BIOS
  387. | | will round to the nearest 1/8W when
  388. | | programming. If the value is 0, BIOS will
  389. | | program this value as 1.25 * Processor
  390. | | Base Power (TDP). For 12.50W, enter 12500.
  391. | | Processor applies control policies such
  392. | | that package power does not exeed this
  393. | | limit.
  394. Energy Efficient Turbo | [Enabled] | Enable/Disable Energy Efficient Turbo
  395. | | Feature. This feature will
  396. | | opportunistically lower the turbo
  397. | | frequency to increase the efficiency.
  398. | | Recommended only to disable in
  399. | | overclocking situations where turbo
  400. | | frequency must remain constant. Otherwise,
  401. | | leave enabled.
  402.  
  403.  
  404. **Advanced -> Power & Performance -> CPU - Power Management Control ->
  405. View/Configure Turbo Options -> Turbo Ratio Limit Options**
  406.  
  407. Option | Value | Description
  408. --------------------------------|-----------------------|-------------------------------------------
  409. **Current Turbo Ratio Limit | |
  410. Settings** | |
  411. | |
  412. * E-core Turbo Ratio Limit | |
  413. Numcore0 | [1] |
  414. * E-core Turbo Ratio Limit | |
  415. Numcore1 | [2] |
  416. * E-core Turbo Ratio Limit | |
  417. Numcore2 | [3] |
  418. * E-core Turbo Ratio Limit | |
  419. Numcore3 | [4] |
  420. * E-core Turbo Ratio Limit | |
  421. Numcore4 | [5] |
  422. * E-core Turbo Ratio Limit | |
  423. Numcore5 | [6] |
  424. * E-core Turbo Ratio Limit | |
  425. Numcore6 | [7] |
  426. * E-core Turbo Ratio Limit | |
  427. Numcore7 | [8] |
  428. * E-core Turbo Ratio Limit | |
  429. Ratio0 | [34] |
  430. * E-core Turbo Ratio Limit | |
  431. Ratio1 | [34] |
  432. * E-core Turbo Ratio Limit | |
  433. Ratio2 | [31] |
  434. * E-core Turbo Ratio Limit | |
  435. Ratio3 | [29] |
  436. * E-core Turbo Ratio Limit | |
  437. Ratio4 | [29] |
  438. * E-core Turbo Ratio Limit | |
  439. Ratio5 | [29] |
  440. * E-core Turbo Ratio Limit | |
  441. Ratio6 | [29] |
  442. * E-core Turbo Ratio Limit | |
  443. Ratio7 | [29] |
  444. | |
  445. E-core Turbo Ratio Limit | [1] | Efficient-core Turbo Ratio Limit Numcore0
  446. Numcore0 | | defines the core range, the turbo ratio is
  447. | | defined in E-core Turbo Ratio Limit
  448. | | Ratio0. If value is zero, this entry is
  449. | | ignored.
  450. E-core Turbo Ratio Limit | [2] | Efficient-core Turbo Ratio Limit Numcore1
  451. Numcore1 | | defines the core range, the turbo ratio is
  452. | | defined in E-core Turbo Ratio Limit
  453. | | Ratio1. If value is zero, this entry is
  454. | | ignored.
  455. E-core Turbo Ratio Limit | [3] | Efficient-core Turbo Ratio Limit Numcore2
  456. Numcore2 | | defines the core range, the turbo ratio is
  457. | | defined in E-core Turbo Ratio Limit
  458. | | Ratio2. If value is zero, this entry is
  459. | | ignored.
  460. E-core Turbo Ratio Limit | [4] | Efficient-core Turbo Ratio Limit Numcore3
  461. Numcore3 | | defines the core range, the turbo ratio is
  462. | | defined in E-core Turbo Ratio Limit
  463. | | Ratio3. If value is zero, this entry is
  464. | | ignored.
  465. E-core Turbo Ratio Limit | [5] | Efficient-core Turbo Ratio Limit Numcore4
  466. Numcore4 | | defines the core range, the turbo ratio is
  467. | | defined in E-core Turbo Ratio Limit
  468. | | Ratio4. If value is zero, this entry is
  469. | | ignored.
  470. E-core Turbo Ratio Limit | [6] | Efficient-core Turbo Ratio Limit Numcore5
  471. Numcore5 | | defines the core range, the turbo ratio is
  472. | | defined in E-core Turbo Ratio Limit
  473. | | Ratio5. If value is zero, this entry is
  474. | | ignored.
  475. E-core Turbo Ratio Limit | [7] | Efficient-core Turbo Ratio Limit Numcore6
  476. Numcore6 | | defines the core range, the turbo ratio is
  477. | | defined in E-core Turbo Ratio Limit
  478. | | Ratio6. If value is zero, this entry is
  479. | | ignored.
  480. E-core Turbo Ratio Limit | [8] | Efficient-core Turbo Ratio Limit Numcore7
  481. Numcore7 | | defines the core range, the turbo ratio is
  482. | | defined in E-core Turbo Ratio Limit
  483. | | Ratio7. If value is zero, this entry is
  484. | | ignored.
  485. E-core Turbo Ratio Limit | [34] | Efficient-core Turbo Ratio Limit Ratio0
  486. Ratio0 | | defines the turbo ratio (max is 85
  487. | | irrespective of the core extension mode),
  488. | | the core range is defined in E-core Turbo
  489. | | Ratio Limit Numcore0.
  490. E-core Turbo Ratio Limit | [34] | Efficient-core Turbo Ratio Limit Ratio1
  491. Ratio1 | | defines the turbo ratio (max is 85
  492. | | irrespective of the core extension mode),
  493. | | the core range is defined in E-core Turbo
  494. | | Ratio Limit Numcore1.
  495. E-core Turbo Ratio Limit | [31] | Efficient-core Turbo Ratio Limit Ratio2
  496. Ratio2 | | defines the turbo ratio (max is 85
  497. | | irrespective of the core extension mode),
  498. | | the core range is defined in E-core Turbo
  499. | | Ratio Limit Numcore2.
  500. E-core Turbo Ratio Limit | [29] | Efficient-core Turbo Ratio Limit Ratio3
  501. Ratio3 | | defines the turbo ratio (max is 85
  502. | | irrespective of the core extension mode),
  503. | | the core range is defined in E-core Turbo
  504. | | Ratio Limit Numcore3.
  505. E-core Turbo Ratio Limit | [29] | Efficient-core Turbo Ratio Limit Ratio4
  506. Ratio4 | | defines the turbo ratio (max is 85
  507. | | irrespective of the core extension mode),
  508. | | the core range is defined in E-core Turbo
  509. | | Ratio Limit Numcore4.
  510. E-core Turbo Ratio Limit | [29] | Efficient-core Turbo Ratio Limit Ratio5
  511. Ratio5 | | defines the turbo ratio (max is 85
  512. | | irrespective of the core extension mode),
  513. | | the core range is defined in E-core Turbo
  514. | | Ratio Limit Numcore5.
  515. E-core Turbo Ratio Limit | [29] | Efficient-core Turbo Ratio Limit Ratio6
  516. Ratio6 | | defines the turbo ratio (max is 85
  517. | | irrespective of the core extension mode),
  518. | | the core range is defined in E-core Turbo
  519. | | Ratio Limit Numcore6.
  520. E-core Turbo Ratio Limit | [29] | Efficient-core Turbo Ratio Limit Ratio7
  521. Ratio7 | | defines the turbo ratio (max is 85
  522. | | irrespective of the core extension mode),
  523. | | the core range is defined in E-core Turbo
  524. | | Ratio Limit Numcore7.
  525.  
  526.  
  527. **Advanced -> Power & Performance -> CPU - Power Management Control -> CPU VR Settings**
  528.  
  529. Option | Value | Description
  530. --------------------------------|-----------------------|-------------------------------------------
  531. **CPU VR Settings** | |
  532. | |
  533. * Current VccIn Aux Icc Max | [108] |
  534. PSYS Slope | [0] | PSYS Slope defined in 1/100 increments.
  535. | | Range is 0-200. For a 1.25 slope, enter
  536. | | 125, 0 = AUTO. Uses BIOS VR mailbox
  537. | | command 0x09.
  538. PSYS Offset | [0] | PSYS Offset defined in 1/1000 increments.
  539. | | Range is 0-63999. For an offset 25.348,
  540. | | enter 25348. PSYS uses BIOS VR mailbox
  541. | | command 0x04.
  542. PSYS Prefix | [+] | Sets the offset value as positive or
  543. | | negative.
  544. | | Valid options: [+], [-].
  545. PSYS PMax Power | [0] | PSYS PMax power, defined in 1/8W Watt or
  546. | | Percent Increments. For Watts , Range is
  547. | | 0-8192 (ex. for 125W, enter 1000). For
  548. | | ATX12V0 Percent, range is 0-1600 (ex. for
  549. | | 200%, enter 1600). Uses BIOS VR mailbox
  550. | | command 0x0B.
  551. Min Voltage Override | [Disabled] | Min Voltage Override. Enable to override
  552. | | minimum voltage for runtime and for C8.
  553. VccIn Aux Icc Max | [0] | Sets the Max Icc VccIn Aux value defined
  554. | | in 1/4A increments. Range is 0-512. For an
  555. | | IccMax 32A, enter 128 (32 * 4)
  556. VccIn Aux IMON Slope | [100] | VccIn Aux IMON Slope defined in 1/100
  557. | | increments. Range is 0-200. For a 1.25
  558. | | slope, enter 125, 0 = AUTO. Uses BIOS VR
  559. | | mailbox command 0x18.
  560. VccIn Aux IMON Offset | [0] | VccIn Aux IMON Offset defined in 1/1000
  561. | | increments. Range is 0-63999. For an
  562. | | offset of 25.348, enter 25348. IMON users
  563. | | BIOS VR mailbox command 0x18.
  564. VccIn Aux IMON Prefix | [+] | Set the offset value as positive or
  565. | | negative.
  566. | | Valid options: [+], [-].
  567. Vsys/Psys Critical | [Disabled] | Vsys/Psys Critical Enable or Disable.
  568. Assertion Deglitch Mantissa | [1] | Assertion Deglitch Mantissa 0x4F[7-3].
  569. | | Assertion Deglitch = 2μs * Mantissa *
  570. | | 2^(Exponent).
  571. Assertion Deglitch Exponent | [0] | Assertion Deglitch Exponent 0x4F[3-0].
  572. | | Assertion Deglitch = 2μs * Mantissa *
  573. | | 2^(Exponent).
  574. De Assertion Deglitch Mantissa | [13] | De Assertion Deglitch Mantissa 0x49[7-3].
  575. | | Assertion Deglitch = 2μs * Mantissa *
  576. | | 2^(Exponent).
  577. De Assertion Deglitch Exponent | [2] | De Assertion Deglitch Exponent 0x49[3-0].
  578. | | Assertion Deglitch = 2μs * Mantissa *
  579. | | 2^(Exponent).
  580. VR Power Delivery Design | [AUTO] | Specify the ADL Desktop board design used
  581. | | for the VR settings override values. By
  582. | | default, BIOS will override the default
  583. | | Desktop VR settings based on the board
  584. | | design. A value of AUTO(0) will use the
  585. | | board ID to determine the board design.
  586. | | Any other value will override the board id
  587. | | logig to provide a custom VR Power
  588. | | Delivery Design value. This is intended
  589. | | primarily for validation.
  590. | | Valid options: [AUTO], [AOL P 282 15W],
  591. | | [AOL P 482 28W], [AOL P 682 28W],
  592. | | [AOL P 682 45W], [AOL P 142 15W],
  593. | | [AOL P 242 15W], [AOL P 482 45W],
  594. | | [AOL P 442 45W], [AOL P 442 28W],
  595. | | [AOL P 282 28W], [AOL P 242 28W],
  596. | | [AOL P 142 28W], [AOL P 242 45W],
  597. | | [AOL P 182 28W], [AOL P 662 28W],
  598. | | [AOL P 642 28W], [AOL P 642 45W]
  599. > Acoustic Noise Settings | | Configure Acoustic Noise Settings for IA,
  600. | | GT and SA domains.
  601. > Core/IA VR Settings | | Core/IA VR Settings
  602. > GT VR Settings | | GT VR Settings
  603. > RFI Settings | | RFI Settings
  604.  
  605.  
  606. **Advanced -> Power & Performance -> CPU - Power Management Control -> CPU VR Settings ->
  607. Acoustic Noise Settings**
  608.  
  609. Option | Value | Description
  610. --------------------------------|-----------------------|-------------------------------------------
  611. **Acoustic Noise Settings** | |
  612. | |
  613. Acoustic Noise Mitigation | [Disabled] | Enabling this option will help mitigate
  614. | | acoustic noise on certain SKUs when the
  615. | | CPU is in deeper C state.
  616. Pre Wake Time | [0] | Set the maximum Pre Wake randomization
  617. | | time in micro ticks. Range is 0-255. This
  618. | | is for acoustic noise mitigation Dynamic
  619. | | Perodicity Alteration (DPA) tuning.
  620. Rump Up Time | [0] | Set the maximum Rump Up randomization time
  621. | | in micro ticks. Range is 0-255. This is
  622. | | for acoustic noise mitigation Dynamic
  623. | | Perodicity Alteration (DPA) tuning.
  624. Ramp Down Time | [0] | Set the maximum Ramp Down randomization
  625. | | time in micro ticks. Range is 0-255. This
  626. | | is for acoustic noise mitigation Dynamic
  627. | | Perodicity Alteration (DPA) tuning.
  628. | |
  629. **IA VR Domain** | |
  630. | |
  631. Disable Fast PKG C State Ramp | [FALSE] | This option needs to be configured to
  632. for IA Domain | | reduce acoustic noise during deeper C
  633. | | states. False: Don't disable Fast ramp
  634. | | during deeper C states; True: Disable Fast
  635. | | ramp during deeper C states.
  636. | | Valid options: [FALSE], [TRUE].
  637. Slow Slew Rate for IA Domain | [Fast/2] | Set VR IA Slow Slew Rate for Deep Package
  638. | | C State ramp time; Slow slew rate equals
  639. | | to Fast divided by number. The number is
  640. | | 2, 4, 8, 16 to slow down the slew rate to
  641. | | help minimize acoustic noise.
  642. | | Valid options: [Fast/2], [Fast/4],
  643. | | [Fast/8], [Fast/16].
  644. | |
  645. **GT VR Domain** | |
  646. | |
  647. Disable Fast PKG C State Ramp | [FALSE] | This option needs to be configured to
  648. for GT Domain | | reduce acoustic noise during deeper C
  649. | | states. False: Don't disable Fast ramp
  650. | | during deeper C states; True: Disable Fast
  651. | | ramp during deeper C states.
  652. | | Valid options: [FALSE], [TRUE].
  653. Slow Slew Rate for GT Domain | [Fast/2] | Set VR GT Slow Slew Rate for Deep Package
  654. | | C State ramp time; Slow slew rate equals
  655. | | to Fast divided by number. The number is
  656. | | 2, 4, 8 to slow down the slew rate to help
  657. | | minimize acoustic noise; divide by 16 is
  658. | | disabled.
  659. | | Valid options: [Fast/2], [Fast/4],
  660. | | [Fast/8].
  661.  
  662.  
  663. **Advanced -> Power & Performance -> CPU - Power Management Control -> CPU VR Settings ->
  664. Core/IA VR Settings**
  665.  
  666. Option | Value | Description
  667. --------------------------------|-----------------------|-------------------------------------------
  668. **Core/IA VR Domain** | |
  669. | |
  670. VR Config Enable | [Enabled] | VR Config Enable.
  671. * Current AC Loadline | [500] |
  672. * Current DC Loadline | [500] |
  673. * Current Psi1 Threshold | [80] |
  674. * Current Psi2 Threshold | [20] |
  675. * Current Psi3 Threshold | [4] |
  676. * Current Imon Slope | [0] |
  677. * Current Imon Offset | [1] |
  678. * Current VR Current Limit | [148] |
  679. * Current Tdc Current Limit | [208] |
  680. * Current Voltage Limit | [1600] |
  681. AC Loadline | [0] | AC Loadline defined in 1/100 mOhms, and
  682. | | 1255 = 12.55 mOhms. Range is 0-6249
  683. | | (0-62.49 mOhms). 0 = AUTO/HW default.
  684. | | Uses BIOS mailbox command 0x02.
  685. DC Loadline | [0] | DC Loadline defined in 1/100 mOhms, and
  686. | | 1255 = 12.55 mOhms. Range is 0-6249
  687. | | (0-62.49 mOhms). 0 = AUTO/HW default. Uses
  688. | | BIOS mailbox command 0x02.
  689. PS Current Threshold1 | [80] | PS Current Threshold1, defined in 1/4A
  690. | | increments. A value of 400 = 100A. Range
  691. | | 0-512, which translate to 0-128A.
  692. | | 0 = Auto. Uses BIOS VR mailbox command
  693. | | 0x03.
  694. PS Current Threshold2 | [20] | PS Current Threshold2, defined in 1/4A
  695. | | increments. A value of 400 = 100A. Range
  696. | | 0-512, which translate to 0-128A.
  697. | | 0 = Auto. Uses BIOS VR mailbox command
  698. | | 0x03.
  699. PS Current Threshold3 | [4] | PS Current Threshold3, defined in 1/4A
  700. | | increments. A value of 400 = 100A. Range
  701. | | 0-512, which translate to 0-128A.
  702. | | 0 = Auto. Uses BIOS VR mailbox command
  703. | | 0x03.
  704. PS3 Enable | [Enabled] | PS3 Enable/Disable. 0 - Disabled,
  705. | | 1 - Enabled. Uses BIOS VR mailbox command
  706. | | 0x03.
  707. PS4 Enable | [Enabled] | PS4 Enable/Disable. 0 - Disabled,
  708. | | 1 - Enabled. Uses BIOS VR mailbox command
  709. | | 0x03.
  710. IMON Slope | 0 | IMON Slope defined in 1/100 increments.
  711. | | Range is 0-200. For a 1.25 slope, enter
  712. | | 125. 0 = AUTO. Uses BIOS VR mailbox
  713. | | command 0x04.
  714. IMON Offset | 0 | IMON Offset defined in 1/1000 increments.
  715. | | Range is 0-63999. For an offset of 25.348,
  716. | | enter 25348. IMON uses BIOS VR mailbox
  717. | | command 0x04.
  718. IMON Prefix | [+] | Sets the offset value as positive or
  719. | | negative.
  720. | | Valid options: [+], [-].
  721. VR Current Limit | [0] | Voltage Regulator Current Limit (IccMax).
  722. | | This value represents the Maximum
  723. | | instantaneous current allowed at any given
  724. | | time. The value is represented in 1/4A
  725. | | increments. A value of 400 = 100A. 0 means
  726. | | AUTO. Uses BIOS VR mailbox command 0x06.
  727. VR Voltage Limit | [0] | Voltage Limit (VMAX). This value
  728. | | represents the Maximum instantaneous
  729. | | voltage allowed at any given time. Range
  730. | | is 0-7999mV. Uses BIOS VR mailbox command
  731. | | 0x08.
  732. TDC Enable | [Enabled] | TDC Enable, 0 - Disable, 1 - Enable.
  733. TDC Current Limit | [0] | TDC Current Limit, defined in 1/8A
  734. | | increments. Range 0-32767. For a TDC
  735. | | Current Limit of 125A, enter 1000. 0 = 0A,
  736. | | Uses BIOS VR mailbox command 0x1A.
  737. TDC Time Window | [1 sec] | VR TDC Time Window, value in seconds, 1s
  738. | | is default. Range from 1s to 448s.
  739. TDC Lock | [Disabled] | TDC Lock
  740. IRMS | [Disabled] | Enable/Disable IRMS - Current root mean
  741. | | square.
  742.  
  743.  
  744. **Advanced -> Power & Performance -> CPU - Power Management Control -> CPU VR Settings ->
  745. GT VR Settings**
  746.  
  747. Option | Value | Description
  748. --------------------------------|-----------------------|-------------------------------------------
  749. **GT VR Domain** | |
  750. | |
  751. VR Config Enable | [Enabled] | VR Config Enable.
  752. * Current AC Loadline | [650] |
  753. * Current DC Loadline | [650] |
  754. * Current Psi1 Threshold | [80] |
  755. * Current Psi2 Threshold | [20] |
  756. * Current Psi3 Threshold | [4] |
  757. * Current Imon Slope | [0] |
  758. * Current Imon Offset | [1] |
  759. * Current VR Current Limit | [104] |
  760. * Current Tdc Current Limit | [152] |
  761. * Current Voltage Limit | [1519] |
  762. AC Loadline | [0] | AC Loadline defined in 1/100 mOhms. A
  763. | | value of 100 = 1.00 mOhm and 1255 = 12.55
  764. | | mOhm. Range is 0-6249 (0-62.49 mOhms).
  765. | | 0 = AUTO/HW default. Uses BIOS mailbox
  766. | | command 0x02.
  767. DC Loadline | [0] | DC Loadline defined in 1/100 mOhms. A
  768. | | value of 100 = 1.00 mOhm and 1255 = 12.55
  769. | | mOhm. Range is 0-6249 (0-62.49 mOhms).
  770. | | 0 = AUTO/HW default. Uses BIOS mailbox
  771. | | command 0x02.
  772. PS Current Threshold1 | [80] | PS Current Threshold1, defined in 1/4A
  773. | | increments. A value of 400 = 100A. Range
  774. | | 0-512, which translate to 0-128A.
  775. | | 0 = Auto. Uses BIOS VR mailbox command
  776. | | 0x03.
  777. PS Current Threshold2 | [20] | PS Current Threshold2, defined in 1/4A
  778. | | increments. A value of 400 = 100A.
  779. | | Range 0-512, which translate to 0-128A.
  780. | | 0 = Auto. Uses BIOS VR mailbox command
  781. | | 0x03.
  782. PS Current Threshold3 | [4] | PS Current Threshold3, defined in 1/4A
  783. | | increments. A value of 400 = 100A.
  784. | | Range 0-512, which translate to 0-128A.
  785. | | 0 = Auto. Uses BIOS VR mailbox command
  786. | | 0x03.
  787. PS3 Enable | [Enabled] | PS3 Enable/Disable. 0 - Disabled,
  788. | | 1 - Enabled. Uses BIOS VR mailbox command
  789. | | 0x03.
  790. PS4 Enable | [Enabled] | PS4 Enable/Disable. 0 - Disabled,
  791. | | 1 - Enabled. Uses BIOS VR mailbox command
  792. | | 0x03.
  793. IMON Slope | 0 | IMON Slope defined in 1/100 increments.
  794. | | Range is 0-200. For a 1.25 slope, enter
  795. | | 125. 0 = AUTO. Uses BIOS VR mailbox
  796. | | command 0x04.
  797. IMON Offset | 0 | IMON Offset defined in 1/1000 increments.
  798. | | Range is 0-63999. For an offset of 25.348,
  799. | | enter 25348. IMON uses BIOS VR mailbox
  800. | | command 0x04.
  801. IMON Prefix | [+] | Sets the offset value as positive or
  802. | | negative.
  803. | | Valid options: [+], [-].
  804. VR Current Limit | [0] | Voltage Regulator Current Limit (IccMax).
  805. | | This value represents the Maximum
  806. | | instantaneous current allowed at any given
  807. | | time. The value is represented in 1/4A
  808. | | increments. A value of 400 = 100A. 0 means
  809. | | AUTO. Uses BIOS VR mailbox command 0x06.
  810. VR Voltage Limit | [0] | Voltage Limit (VMAX). This value
  811. | | represents the Maximum instantaneous
  812. | | voltage allowed at any given time. Range
  813. | | is 0-7999mV. Uses BIOS VR mailbox command
  814. | | 0x08.
  815. TDC Enable | [Enabled] | TDC Enable, 0 - Disable, 1 - Enable.
  816. TDC Current Limit | [0] | TDC Current Limit, defined in 1/8A
  817. | | increments. Range 0-32767. For a TDC
  818. | | Current Limit of 125A, enter 1000. 0 = 0A,
  819. | | Uses BIOS VR mailbox command 0x1A.
  820. TDC Time Window | [1 sec] | VR TDC Time Window, value in seconds, 1s
  821. | | is default. Range from 1s to 448s.
  822. TDC Lock | [Disabled] | TDC Lock
  823.  
  824.  
  825. **Advanced -> Power & Performance -> CPU - Power Management Control -> CPU VR Settings ->
  826. RFI Settings**
  827.  
  828. Option | Value | Description
  829. --------------------------------|-----------------------|-------------------------------------------
  830. **RFI Domain** | |
  831. | |
  832. * RFI Current Frequency | 139.200MHz |
  833. RFI Frequency | [0] | Set desired RFI frequency, in increments
  834. | | of 100kHz. (For a frequency of 100.6MHz,
  835. | | enter 1006)
  836. FIVR Spread Spectrum | [Enabled] | Enable or Disable the FIVR Spread
  837. | | Spectrum.
  838. RFI Spread Spectrum | [1.5%] | Set the Spread Spectrum.
  839. | | Valid options: [0.5%], [1%], [1.5%], [2%],
  840. | | [3%], [4%], [5%], [6%].
  841.  
  842.  
  843. **Advanced -> Power & Performance -> CPU - Power Management Control -> Custom P-state Table**
  844.  
  845. Option | Value | Description
  846. --------------------------------|-----------------------|-------------------------------------------
  847. **Custom P-state Table** | |
  848. | |
  849. Number of P states | [0] | Sets the number of custom P-states. At
  850. | | least 2 states must be present.
  851.  
  852.  
  853. **Advanced -> Power & Performance -> CPU - Power Management Control -> Power Limit 3 Settings**
  854.  
  855. Option | Value | Description
  856. --------------------------------|-----------------------|-------------------------------------------
  857. **Power Limit 3 Settings** | |
  858. | |
  859. Power Limit 3 Override | [Disabled] | Enable/Disable Power Limit 3 override. If
  860. | | this option is disabled, BIOS will leave
  861. | | the hardware default values for Power
  862. | | Limit 3 and Power Limit 3 Window.
  863. Power Limit 3 | [0] | Power Limit 3 in Milli Watts/Percent. BIOS
  864. | | will round to the nearest 1/8W when
  865. | | programming. For example, if 12.50W, enter
  866. | | 12500, if 12%, enter 12000, if 50% enter
  867. | | 50000. XE SKU: Any value can be
  868. | | programmed. Overclocking SKU: value must
  869. | | be between Max and Min Power Limits
  870. | | (specified by PACKAGE_POWER_SKU_MSR).
  871. | | Other SKUs: This value must be between Min
  872. | | Power Limit and Processor Base Power (TDP)
  873. | | Limit. If the value is 0, BIOS leaves the
  874. | | harware default value.
  875. Power Limit 3 Time Window | [0] | Power Limit 3 Time Window value in Milli
  876. | | seconds. The value may vary from 3 to 64
  877. | | (max). Indicates the time window over
  878. | | which Power Limit 3 value should be
  879. | | maintained. If the value is 0, BIOS leaves
  880. | | the hardware default value.
  881. Power Limit 3 Duty Cycle | [0] | Specify the duty cycle in percentage that
  882. | | the CPU is required to maintain over
  883. | | configured time window. Range is 0-100.
  884. Power Limit 3 Lock | [Disabled] | Power Limit 3 MSR 615h Lock. When enabled
  885. | | PL3 configurations are locked during OS.
  886. | | When disabled PL3 configuration can be
  887. | | changed during OS.
  888.  
  889.  
  890. **Advanced -> Power & Performance -> CPU - Power Management Control -> CPU Lock Configuration**
  891.  
  892. Option | Value | Description
  893. --------------------------------|-----------------------|-------------------------------------------
  894. **CPU Lock Configuration** | |
  895. | |
  896. CFG Lock | [Enabled] | Configure MSR 0xE2[15], CFG Lock bit.
  897. Overlocking Lock | [Enabled] | Enable/Disable Overclocking Lock (Bit 20)
  898. | | in FLEX_RATIO(194) MSR
  899.  
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