module mat_mul_accl(
    input logic CLK,
    input logic RESET,
    // start signal that comes in from avalon interface to start conv
    input logic MM_START,
    input logic [31:0] mat1 [8:0],
    input logic [31:0] mat2 [8:0],
    // done signal that tells interface multiplication is complete
    output logic [31:0] outmat [8:0],
    output logic MM_DONE
);
always_comb
begin

        outmat[0] = mat1[0]*mat2[0];
        outmat[1] = mat1[1]*mat2[1];
        outmat[2] = mat1[2]*mat2[2];
        outmat[3] = mat1[3]*mat2[3];
        outmat[4] = mat1[4]*mat2[4];
        outmat[5] = mat1[5]*mat2[5];
        outmat[6] = mat1[6]*mat2[6];
        outmat[7] = mat1[7]*mat2[7];
        outmat[8] = mat1[8]*mat2[8];

end
assign MM_DONE = 1'b1;
endmodule