Modelsim + PLL

`timescale 1ns / 1ps

module test_pll;

initial begin
    $display("test_pll");
end

reg clock;
initial clock = 0;
initial forever #2.5 clock = !clock;

reg pfdena;
reg areset;
reg scanclk;
reg phasestep;
reg phaseupdown;
reg [2:0] phasecounterselect;

wire c0_400;
wire c1_400;
wire c2_50;
wire locked;
wire phasedone;

initial begin
    pfdena = 1;
    areset = 0;
    scanclk = 0;
    phasestep = 0;
    phaseupdown = 0;
    phasecounterselect = 0;
    #10000;
    areset = 1;
    #10000;
    areset = 0;
end

pll pll_(
.areset(areset),
.inclk0(clock),
.pfdena(pfdena),
.phasecounterselect(phasecounterselect), // [2:0]
.phasestep(phasestep),
.phaseupdown(phaseupdown),
.scanclk(clock),
.c0(c0_400),
.c1(c1_400),
.c2(c2_50),
.locked(locked),
.phasedone(phasedone));

endmodule