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  1. Design Summary:
  2. Number of errors:      0
  3. Number of warnings:   52
  4. Logic Utilization:
  5.   Number of Slice Flip Flops:           325 out of   1,536   21%
  6.   Number of 4 input LUTs:             1,291 out of   1,536   84%
  7. Logic Distribution:
  8.   Number of occupied Slices:            766 out of     768   99%
  9.     Number of Slices containing only related logic:     766 out of     766 100%
  10.     Number of Slices containing unrelated logic:          0 out of     766   0%
  11.       *See NOTES below for an explanation of the effects of unrelated logic.
  12.   Total Number of 4 input LUTs:       1,396 out of   1,536   90%
  13.     Number used as logic:             1,289
  14.     Number used as a route-thru:        105
  15.     Number used as Shift registers:       2
  16.  
  17.   The Slice Logic Distribution report is not meaningful if the design is
  18.   over-mapped for a non-slice resource or if Placement fails.
  19.  
  20.   Number of bonded IOBs:                 78 out of     124   62%
  21.   Number of RAMB16s:                      1 out of       4   25%
  22.   Number of MULT18X18s:                   1 out of       4   25%
  23.   Number of BUFGMUXs:                     1 out of       8   12%
  24.   Number of DCMs:                         1 out of       2   50%
  25.  
  26. Average Fanout of Non-Clock Nets:                3.52
  27.  
  28. Peak Memory Usage:  146 MB
  29. Total REAL time to MAP completion:  8 secs
  30. Total CPU time to MAP completion:   4 secs
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