Design Summary:
Number of errors:      0
Number of warnings:   52
Logic Utilization:
  Number of Slice Flip Flops:           325 out of   1,536   21%
  Number of 4 input LUTs:             1,291 out of   1,536   84%
Logic Distribution:
  Number of occupied Slices:            766 out of     768   99%
    Number of Slices containing only related logic:     766 out of     766 100%
    Number of Slices containing unrelated logic:          0 out of     766   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:       1,396 out of   1,536   90%
    Number used as logic:             1,289
    Number used as a route-thru:        105
    Number used as Shift registers:       2

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 78 out of     124   62%
  Number of RAMB16s:                      1 out of       4   25%
  Number of MULT18X18s:                   1 out of       4   25%
  Number of BUFGMUXs:                     1 out of       8   12%
  Number of DCMs:                         1 out of       2   50%

Average Fanout of Non-Clock Nets:                3.52

Peak Memory Usage:  146 MB
Total REAL time to MAP completion:  8 secs
Total CPU time to MAP completion:   4 secs