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  1. --- ddr_uart.v 2020-02-04 13:26:04.860069367 +0100
  2. +++ ../../../../prjxray/minitests/litex/uart_ddr/arty/generated/top.v 2020-02-04 11:10:26.281053991 +0100
  3. @@ -20,63 +20,9 @@
  4. output ddram_clk_n,
  5. output ddram_cke,
  6. output ddram_odt,
  7. - output ddram_reset_n,
  8. - output [3:0] led
  9. + output ddram_reset_n
  10. );
  11.  
  12. -wire [3:0] led;
  13. -
  14. -assign led[0] = main_locked;
  15. -assign led[1] = idelayctl_rdy;
  16. -assign led[2] = 0;
  17. -assign led[3] = 0;
  18. -
  19. -// Manually inserted OBUFs
  20. -wire [13:0] ddram_a_iob;
  21. -wire [ 2:0] ddram_ba_iob;
  22. -wire ddram_ras_n_iob;
  23. -wire ddram_cas_n_iob;
  24. -wire ddram_we_n_iob;
  25. -wire ddram_cs_n_iob;
  26. -wire [ 1:0] ddram_dm_iob;
  27. -wire ddram_cke_iob;
  28. -wire ddram_odt_iob;
  29. -wire ddram_reset_n_iob;
  30. -
  31. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a0 (.I(ddram_a_iob[ 0]), .O(ddram_a[ 0]));
  32. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a1 (.I(ddram_a_iob[ 1]), .O(ddram_a[ 1]));
  33. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a2 (.I(ddram_a_iob[ 2]), .O(ddram_a[ 2]));
  34. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a3 (.I(ddram_a_iob[ 3]), .O(ddram_a[ 3]));
  35. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a4 (.I(ddram_a_iob[ 4]), .O(ddram_a[ 4]));
  36. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a5 (.I(ddram_a_iob[ 5]), .O(ddram_a[ 5]));
  37. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a6 (.I(ddram_a_iob[ 6]), .O(ddram_a[ 6]));
  38. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a7 (.I(ddram_a_iob[ 7]), .O(ddram_a[ 7]));
  39. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a8 (.I(ddram_a_iob[ 8]), .O(ddram_a[ 8]));
  40. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a9 (.I(ddram_a_iob[ 9]), .O(ddram_a[ 9]));
  41. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a10 (.I(ddram_a_iob[10]), .O(ddram_a[10]));
  42. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a11 (.I(ddram_a_iob[11]), .O(ddram_a[11]));
  43. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a12 (.I(ddram_a_iob[12]), .O(ddram_a[12]));
  44. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a13 (.I(ddram_a_iob[13]), .O(ddram_a[13]));
  45. -
  46. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ba0 (.I(ddram_ba_iob[0]), .O(ddram_ba[0]));
  47. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ba1 (.I(ddram_ba_iob[1]), .O(ddram_ba[1]));
  48. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ba2 (.I(ddram_ba_iob[2]), .O(ddram_ba[2]));
  49. -
  50. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_dm0 (.I(ddram_dm_iob[0]), .O(ddram_dm[0]));
  51. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_dm1 (.I(ddram_dm_iob[1]), .O(ddram_dm[1]));
  52. -
  53. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ras (.I(ddram_ras_n_iob), .O(ddram_ras_n));
  54. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_cas (.I(ddram_cas_n_iob), .O(ddram_cas_n));
  55. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_we (.I(ddram_we_n_iob), .O(ddram_we_n));
  56. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_cs (.I(ddram_cs_n_iob), .O(ddram_cs_n));
  57. -
  58. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_cke (.I(ddram_cke_iob), .O(ddram_cke));
  59. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_odt (.I(ddram_odt_iob), .O(ddram_odt));
  60. -OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_rst (.I(ddram_reset_n_iob),.O(ddram_reset_n));
  61. -
  62. -// End manually inserted OBUFs
  63. -
  64. -wire idelayctl_rdy;
  65. reg main_ctrl_reset_storage = 1'd0;
  66. reg main_ctrl_reset_re = 1'd0;
  67. reg [31:0] main_ctrl_scratch_storage = 32'd305419896;
  68. @@ -208,13 +154,12 @@
  69. wire sys_clk;
  70. wire sys_rst;
  71. wire sys4x_clk;
  72. -wire sys4x_clkb;
  73. wire sys4x_dqs_clk;
  74. wire clk200_clk;
  75. wire clk200_rst;
  76. wire main_reset;
  77. wire main_locked;
  78. -wire main_pll_clkin;
  79. +wire main_clkin;
  80. wire main_clkout0;
  81. wire main_clkout_buf0;
  82. wire main_clkout1;
  83. @@ -223,7 +168,6 @@
  84. wire main_clkout_buf2;
  85. wire main_clkout3;
  86. wire main_clkout_buf3;
  87. -wire main_clkout_buf4;
  88. reg [3:0] main_reset_counter = 4'd15;
  89. reg main_ic_reset = 1'd1;
  90. reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd16;
  91. @@ -2444,9 +2388,9 @@
  92. endcase
  93. end
  94. assign main_reset = (~cpu_reset);
  95. +assign main_clkin = clk100;
  96. assign sys_clk = main_clkout_buf0;
  97. assign sys4x_clk = main_clkout_buf1;
  98. -assign sys4x_clkb = main_clkout_buf4;
  99. assign sys4x_dqs_clk = main_clkout_buf2;
  100. assign clk200_clk = main_clkout_buf3;
  101. always @(*) begin
  102. @@ -9708,51 +9652,31 @@
  103. $readmemh("mem_1.init", mem_1);
  104. end
  105.  
  106. -(* LOC="BUFGCTRL_X0Y16" *)
  107. BUFG BUFG(
  108. - .I(clk100),
  109. - .O(main_pll_clkin)
  110. -);
  111. -
  112. -(* LOC="BUFGCTRL_X0Y0" *)
  113. -BUFG BUFG_1(
  114. .I(main_clkout0),
  115. .O(main_clkout_buf0)
  116. );
  117.  
  118. -(* LOC="BUFGCTRL_X0Y1" *)
  119. -BUFG BUFG_2(
  120. +BUFG BUFG_1(
  121. .I(main_clkout1),
  122. .O(main_clkout_buf1)
  123. );
  124.  
  125. -(* LOC="BUFGCTRL_X0Y3" *)
  126. -BUFG BUFG_3(
  127. +BUFG BUFG_2(
  128. .I(main_clkout2),
  129. .O(main_clkout_buf2)
  130. );
  131.  
  132. -(* LOC="BUFGCTRL_X0Y2" *)
  133. -BUFG BUFG_4(
  134. +BUFG BUFG_3(
  135. .I(main_clkout3),
  136. .O(main_clkout_buf3)
  137. );
  138.  
  139. -(* LOC="BUFGCTRL_X0Y4" *)
  140. -BUFG BUFG_5(
  141. - .I((~main_clkout_buf1)),
  142. - .O(main_clkout_buf4)
  143. -);
  144. -
  145. -(* LOC="IDELAYCTRL_X1Y0" *)
  146. IDELAYCTRL IDELAYCTRL(
  147. - .REFCLK(sys4x_clk),
  148. - .RST(main_ic_reset),
  149. - .RDY(idelayctl_rdy)
  150. + .REFCLK(clk200_clk),
  151. + .RST(main_ic_reset)
  152. );
  153.  
  154. -wire tq;
  155. -
  156. OSERDESE2 #(
  157. .DATA_RATE_OQ("DDR"),
  158. .DATA_RATE_TQ("BUF"),
  159. @@ -9772,17 +9696,13 @@
  160. .D8(1'd1),
  161. .OCE(1'd1),
  162. .RST(sys_rst),
  163. - .OQ(main_a7ddrphy_sd_clk_se_nodelay),
  164. - .TQ(tq),
  165. - .TCE(1'd1),
  166. - .T1(1'b0)
  167. + .OQ(main_a7ddrphy_sd_clk_se_nodelay)
  168. );
  169.  
  170. -OBUFTDS OBUFTDS_2(
  171. +OBUFDS OBUFDS(
  172. .I(main_a7ddrphy_sd_clk_se_nodelay),
  173. .O(ddram_clk_p),
  174. - .OB(ddram_clk_n),
  175. - .T(tq)
  176. + .OB(ddram_clk_n)
  177. );
  178.  
  179. OSERDESE2 #(
  180. @@ -9804,7 +9724,7 @@
  181. .D8(main_a7ddrphy_dfi_p3_address[0]),
  182. .OCE(1'd1),
  183. .RST(sys_rst),
  184. - .OQ(ddram_a_iob[0])
  185. + .OQ(ddram_a[0])
  186. );
  187.  
  188. OSERDESE2 #(
  189. @@ -9826,7 +9746,7 @@
  190. .D8(main_a7ddrphy_dfi_p3_address[1]),
  191. .OCE(1'd1),
  192. .RST(sys_rst),
  193. - .OQ(ddram_a_iob[1])
  194. + .OQ(ddram_a[1])
  195. );
  196.  
  197. OSERDESE2 #(
  198. @@ -9848,7 +9768,7 @@
  199. .D8(main_a7ddrphy_dfi_p3_address[2]),
  200. .OCE(1'd1),
  201. .RST(sys_rst),
  202. - .OQ(ddram_a_iob[2])
  203. + .OQ(ddram_a[2])
  204. );
  205.  
  206. OSERDESE2 #(
  207. @@ -9870,7 +9790,7 @@
  208. .D8(main_a7ddrphy_dfi_p3_address[3]),
  209. .OCE(1'd1),
  210. .RST(sys_rst),
  211. - .OQ(ddram_a_iob[3])
  212. + .OQ(ddram_a[3])
  213. );
  214.  
  215. OSERDESE2 #(
  216. @@ -9892,7 +9812,7 @@
  217. .D8(main_a7ddrphy_dfi_p3_address[4]),
  218. .OCE(1'd1),
  219. .RST(sys_rst),
  220. - .OQ(ddram_a_iob[4])
  221. + .OQ(ddram_a[4])
  222. );
  223.  
  224. OSERDESE2 #(
  225. @@ -9914,7 +9834,7 @@
  226. .D8(main_a7ddrphy_dfi_p3_address[5]),
  227. .OCE(1'd1),
  228. .RST(sys_rst),
  229. - .OQ(ddram_a_iob[5])
  230. + .OQ(ddram_a[5])
  231. );
  232.  
  233. OSERDESE2 #(
  234. @@ -9936,7 +9856,7 @@
  235. .D8(main_a7ddrphy_dfi_p3_address[6]),
  236. .OCE(1'd1),
  237. .RST(sys_rst),
  238. - .OQ(ddram_a_iob[6])
  239. + .OQ(ddram_a[6])
  240. );
  241.  
  242. OSERDESE2 #(
  243. @@ -9958,7 +9878,7 @@
  244. .D8(main_a7ddrphy_dfi_p3_address[7]),
  245. .OCE(1'd1),
  246. .RST(sys_rst),
  247. - .OQ(ddram_a_iob[7])
  248. + .OQ(ddram_a[7])
  249. );
  250.  
  251. OSERDESE2 #(
  252. @@ -9980,7 +9900,7 @@
  253. .D8(main_a7ddrphy_dfi_p3_address[8]),
  254. .OCE(1'd1),
  255. .RST(sys_rst),
  256. - .OQ(ddram_a_iob[8])
  257. + .OQ(ddram_a[8])
  258. );
  259.  
  260. OSERDESE2 #(
  261. @@ -10002,7 +9922,7 @@
  262. .D8(main_a7ddrphy_dfi_p3_address[9]),
  263. .OCE(1'd1),
  264. .RST(sys_rst),
  265. - .OQ(ddram_a_iob[9])
  266. + .OQ(ddram_a[9])
  267. );
  268.  
  269. OSERDESE2 #(
  270. @@ -10024,7 +9944,7 @@
  271. .D8(main_a7ddrphy_dfi_p3_address[10]),
  272. .OCE(1'd1),
  273. .RST(sys_rst),
  274. - .OQ(ddram_a_iob[10])
  275. + .OQ(ddram_a[10])
  276. );
  277.  
  278. OSERDESE2 #(
  279. @@ -10046,7 +9966,7 @@
  280. .D8(main_a7ddrphy_dfi_p3_address[11]),
  281. .OCE(1'd1),
  282. .RST(sys_rst),
  283. - .OQ(ddram_a_iob[11])
  284. + .OQ(ddram_a[11])
  285. );
  286.  
  287. OSERDESE2 #(
  288. @@ -10068,7 +9988,7 @@
  289. .D8(main_a7ddrphy_dfi_p3_address[12]),
  290. .OCE(1'd1),
  291. .RST(sys_rst),
  292. - .OQ(ddram_a_iob[12])
  293. + .OQ(ddram_a[12])
  294. );
  295.  
  296. OSERDESE2 #(
  297. @@ -10090,7 +10010,7 @@
  298. .D8(main_a7ddrphy_dfi_p3_address[13]),
  299. .OCE(1'd1),
  300. .RST(sys_rst),
  301. - .OQ(ddram_a_iob[13])
  302. + .OQ(ddram_a[13])
  303. );
  304.  
  305. OSERDESE2 #(
  306. @@ -10112,7 +10032,7 @@
  307. .D8(main_a7ddrphy_dfi_p3_bank[0]),
  308. .OCE(1'd1),
  309. .RST(sys_rst),
  310. - .OQ(ddram_ba_iob[0])
  311. + .OQ(ddram_ba[0])
  312. );
  313.  
  314. OSERDESE2 #(
  315. @@ -10134,7 +10054,7 @@
  316. .D8(main_a7ddrphy_dfi_p3_bank[1]),
  317. .OCE(1'd1),
  318. .RST(sys_rst),
  319. - .OQ(ddram_ba_iob[1])
  320. + .OQ(ddram_ba[1])
  321. );
  322.  
  323. OSERDESE2 #(
  324. @@ -10156,7 +10076,7 @@
  325. .D8(main_a7ddrphy_dfi_p3_bank[2]),
  326. .OCE(1'd1),
  327. .RST(sys_rst),
  328. - .OQ(ddram_ba_iob[2])
  329. + .OQ(ddram_ba[2])
  330. );
  331.  
  332. OSERDESE2 #(
  333. @@ -10178,7 +10098,7 @@
  334. .D8(main_a7ddrphy_dfi_p3_ras_n),
  335. .OCE(1'd1),
  336. .RST(sys_rst),
  337. - .OQ(ddram_ras_n_iob)
  338. + .OQ(ddram_ras_n)
  339. );
  340.  
  341. OSERDESE2 #(
  342. @@ -10200,7 +10120,7 @@
  343. .D8(main_a7ddrphy_dfi_p3_cas_n),
  344. .OCE(1'd1),
  345. .RST(sys_rst),
  346. - .OQ(ddram_cas_n_iob)
  347. + .OQ(ddram_cas_n)
  348. );
  349.  
  350. OSERDESE2 #(
  351. @@ -10222,7 +10142,7 @@
  352. .D8(main_a7ddrphy_dfi_p3_we_n),
  353. .OCE(1'd1),
  354. .RST(sys_rst),
  355. - .OQ(ddram_we_n_iob)
  356. + .OQ(ddram_we_n)
  357. );
  358.  
  359. OSERDESE2 #(
  360. @@ -10244,7 +10164,7 @@
  361. .D8(main_a7ddrphy_dfi_p3_cke),
  362. .OCE(1'd1),
  363. .RST(sys_rst),
  364. - .OQ(ddram_cke_iob)
  365. + .OQ(ddram_cke)
  366. );
  367.  
  368. OSERDESE2 #(
  369. @@ -10266,7 +10186,7 @@
  370. .D8(main_a7ddrphy_dfi_p3_odt),
  371. .OCE(1'd1),
  372. .RST(sys_rst),
  373. - .OQ(ddram_odt_iob)
  374. + .OQ(ddram_odt)
  375. );
  376.  
  377. OSERDESE2 #(
  378. @@ -10288,7 +10208,7 @@
  379. .D8(main_a7ddrphy_dfi_p3_reset_n),
  380. .OCE(1'd1),
  381. .RST(sys_rst),
  382. - .OQ(ddram_reset_n_iob)
  383. + .OQ(ddram_reset_n)
  384. );
  385.  
  386. OSERDESE2 #(
  387. @@ -10310,7 +10230,7 @@
  388. .D8(main_a7ddrphy_dfi_p3_cs_n),
  389. .OCE(1'd1),
  390. .RST(sys_rst),
  391. - .OQ(ddram_cs_n_iob)
  392. + .OQ(ddram_cs_n)
  393. );
  394.  
  395. OSERDESE2 #(
  396. @@ -10332,7 +10252,7 @@
  397. .D8(main_a7ddrphy_dfi_p3_wrdata_mask[2]),
  398. .OCE(1'd1),
  399. .RST(sys_rst),
  400. - .OQ(ddram_dm_iob[0])
  401. + .OQ(ddram_dm[0])
  402. );
  403.  
  404. OSERDESE2 #(
  405. @@ -10387,7 +10307,7 @@
  406. .D8(main_a7ddrphy_dfi_p3_wrdata_mask[3]),
  407. .OCE(1'd1),
  408. .RST(sys_rst),
  409. - .OQ(ddram_dm_iob[1])
  410. + .OQ(ddram_dm[1])
  411. );
  412.  
  413. OSERDESE2 #(
  414. @@ -10459,7 +10379,7 @@
  415. .BITSLIP(1'd0),
  416. .CE1(1'd1),
  417. .CLK(sys4x_clk),
  418. - .CLKB(sys4x_clk),
  419. + .CLKB((~sys4x_clk)),
  420. .CLKDIV(sys_clk),
  421. .DDLY(main_a7ddrphy_dq_i_delayed0),
  422. .RST(sys_rst),
  423. @@ -10535,7 +10455,7 @@
  424. .BITSLIP(1'd0),
  425. .CE1(1'd1),
  426. .CLK(sys4x_clk),
  427. - .CLKB(sys4x_clk),
  428. + .CLKB((~sys4x_clk)),
  429. .CLKDIV(sys_clk),
  430. .DDLY(main_a7ddrphy_dq_i_delayed1),
  431. .RST(sys_rst),
  432. @@ -10611,7 +10531,7 @@
  433. .BITSLIP(1'd0),
  434. .CE1(1'd1),
  435. .CLK(sys4x_clk),
  436. - .CLKB(sys4x_clk),
  437. + .CLKB((~sys4x_clk)),
  438. .CLKDIV(sys_clk),
  439. .DDLY(main_a7ddrphy_dq_i_delayed2),
  440. .RST(sys_rst),
  441. @@ -10687,7 +10607,7 @@
  442. .BITSLIP(1'd0),
  443. .CE1(1'd1),
  444. .CLK(sys4x_clk),
  445. - .CLKB(sys4x_clk),
  446. + .CLKB((~sys4x_clk)),
  447. .CLKDIV(sys_clk),
  448. .DDLY(main_a7ddrphy_dq_i_delayed3),
  449. .RST(sys_rst),
  450. @@ -10763,7 +10683,7 @@
  451. .BITSLIP(1'd0),
  452. .CE1(1'd1),
  453. .CLK(sys4x_clk),
  454. - .CLKB(sys4x_clk),
  455. + .CLKB((~sys4x_clk)),
  456. .CLKDIV(sys_clk),
  457. .DDLY(main_a7ddrphy_dq_i_delayed4),
  458. .RST(sys_rst),
  459. @@ -10839,7 +10759,7 @@
  460. .BITSLIP(1'd0),
  461. .CE1(1'd1),
  462. .CLK(sys4x_clk),
  463. - .CLKB(sys4x_clk),
  464. + .CLKB((~sys4x_clk)),
  465. .CLKDIV(sys_clk),
  466. .DDLY(main_a7ddrphy_dq_i_delayed5),
  467. .RST(sys_rst),
  468. @@ -10915,7 +10835,7 @@
  469. .BITSLIP(1'd0),
  470. .CE1(1'd1),
  471. .CLK(sys4x_clk),
  472. - .CLKB(sys4x_clk),
  473. + .CLKB((~sys4x_clk)),
  474. .CLKDIV(sys_clk),
  475. .DDLY(main_a7ddrphy_dq_i_delayed6),
  476. .RST(sys_rst),
  477. @@ -10991,7 +10911,7 @@
  478. .BITSLIP(1'd0),
  479. .CE1(1'd1),
  480. .CLK(sys4x_clk),
  481. - .CLKB(sys4x_clk),
  482. + .CLKB((~sys4x_clk)),
  483. .CLKDIV(sys_clk),
  484. .DDLY(main_a7ddrphy_dq_i_delayed7),
  485. .RST(sys_rst),
  486. @@ -11067,7 +10987,7 @@
  487. .BITSLIP(1'd0),
  488. .CE1(1'd1),
  489. .CLK(sys4x_clk),
  490. - .CLKB(sys4x_clk),
  491. + .CLKB((~sys4x_clk)),
  492. .CLKDIV(sys_clk),
  493. .DDLY(main_a7ddrphy_dq_i_delayed8),
  494. .RST(sys_rst),
  495. @@ -11143,7 +11063,7 @@
  496. .BITSLIP(1'd0),
  497. .CE1(1'd1),
  498. .CLK(sys4x_clk),
  499. - .CLKB(sys4x_clk),
  500. + .CLKB((~sys4x_clk)),
  501. .CLKDIV(sys_clk),
  502. .DDLY(main_a7ddrphy_dq_i_delayed9),
  503. .RST(sys_rst),
  504. @@ -11219,7 +11139,7 @@
  505. .BITSLIP(1'd0),
  506. .CE1(1'd1),
  507. .CLK(sys4x_clk),
  508. - .CLKB(sys4x_clk),
  509. + .CLKB((~sys4x_clk)),
  510. .CLKDIV(sys_clk),
  511. .DDLY(main_a7ddrphy_dq_i_delayed10),
  512. .RST(sys_rst),
  513. @@ -11295,7 +11215,7 @@
  514. .BITSLIP(1'd0),
  515. .CE1(1'd1),
  516. .CLK(sys4x_clk),
  517. - .CLKB(sys4x_clk),
  518. + .CLKB((~sys4x_clk)),
  519. .CLKDIV(sys_clk),
  520. .DDLY(main_a7ddrphy_dq_i_delayed11),
  521. .RST(sys_rst),
  522. @@ -11371,7 +11291,7 @@
  523. .BITSLIP(1'd0),
  524. .CE1(1'd1),
  525. .CLK(sys4x_clk),
  526. - .CLKB(sys4x_clk),
  527. + .CLKB((~sys4x_clk)),
  528. .CLKDIV(sys_clk),
  529. .DDLY(main_a7ddrphy_dq_i_delayed12),
  530. .RST(sys_rst),
  531. @@ -11447,7 +11367,7 @@
  532. .BITSLIP(1'd0),
  533. .CE1(1'd1),
  534. .CLK(sys4x_clk),
  535. - .CLKB(sys4x_clk),
  536. + .CLKB((~sys4x_clk)),
  537. .CLKDIV(sys_clk),
  538. .DDLY(main_a7ddrphy_dq_i_delayed13),
  539. .RST(sys_rst),
  540. @@ -11523,7 +11443,7 @@
  541. .BITSLIP(1'd0),
  542. .CE1(1'd1),
  543. .CLK(sys4x_clk),
  544. - .CLKB(sys4x_clk),
  545. + .CLKB((~sys4x_clk)),
  546. .CLKDIV(sys_clk),
  547. .DDLY(main_a7ddrphy_dq_i_delayed14),
  548. .RST(sys_rst),
  549. @@ -11599,7 +11519,7 @@
  550. .BITSLIP(1'd0),
  551. .CE1(1'd1),
  552. .CLK(sys4x_clk),
  553. - .CLKB(sys4x_clk),
  554. + .CLKB((~sys4x_clk)),
  555. .CLKDIV(sys_clk),
  556. .DDLY(main_a7ddrphy_dq_i_delayed15),
  557. .RST(sys_rst),
  558. @@ -11761,7 +11681,6 @@
  559.  
  560. assign main_tag_port_dat_r = tag_mem[memadr_2];
  561.  
  562. -(* LOC="PLLE2_ADV_X1Y0" *)
  563. PLLE2_ADV #(
  564. .CLKFBOUT_MULT(5'd16),
  565. .CLKIN1_PERIOD(10.0),
  566. @@ -11770,7 +11689,7 @@
  567. .CLKOUT1_DIVIDE(4'd8),
  568. .CLKOUT1_PHASE(1'd0),
  569. .CLKOUT2_DIVIDE(4'd8),
  570. - .CLKOUT2_PHASE(90000),
  571. + .CLKOUT2_PHASE(7'd90),
  572. .CLKOUT3_DIVIDE(4'd8),
  573. .CLKOUT3_PHASE(1'd0),
  574. .DIVCLK_DIVIDE(1'd1),
  575. @@ -11778,7 +11697,7 @@
  576. .STARTUP_WAIT("FALSE")
  577. ) PLLE2_ADV (
  578. .CLKFBIN(builder_pll_fb),
  579. - .CLKIN1(main_pll_clkin),
  580. + .CLKIN1(main_clkin),
  581. .RST(main_reset),
  582. .CLKFBOUT(builder_pll_fb),
  583. .CLKOUT0(main_clkout0),
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