Divider - WORKING

module divider(

   input clk,
   input rst,
   input [7:0] inA,
   input [7:0] inB,
   output [7:0] rem,
   output [7:0] quot

);

reg [1:0] q;
reg [7:0] A;
reg [7:0] B;
reg [8:0] P;
reg [2:0] k;
reg [3:0] cnt;
reg [1:0] ok;

reg[3:0] state,state_nxt;
localparam s0=3'd0, s1=3'd1,s2=3'd2,s3=3'd3;

always @(posedge clk or posedge rst)
begin
    if (rst) begin
      state <= s0;
      A <= inA;
      B <= inB;
      q <= 1'b0;
      k <= 3'b0;
      P <= 5'b0;
      cnt <= 4'd0;
      ok <= 2'd0;
   end
   else begin
      case(state)
        s0:
           if(B[7] == 1'd0)
              begin
                  B[7:1] <= B[6:0];
                  B[0] <= 0;
                  P[8:0] <= {P[7:0], A[7]};
                  A[7:1] <= A[6:0];
                  A[0] <= 0;
                  k <= k + 1'b1;
                  state <= s0;
              end
           else
              state <= s1;
        s1:
        if(cnt < 8 || ok != 0)
           begin
             if(ok == 0) begin
                cnt <= cnt + 1;
                if(P[8:6] == 0 || P[8:6] == 7) begin
                   P[8:0] <= {P[7:0], A[7]};
                   A[7:1] <= A[6:0];
                   A[0] <= 0;
                end
                else if(P[8] == 1) begin
                   P[8:0] <= {P[7:0], A[7]};
                   A[7:1] <= A[6:0];
                   A[0] <= 0;
                   ok <= 2'd1;
                end
                else begin
                   P[8:0] <= {P[7:0], A[7]};
                   A[7:1] <= A[6:0];
                   A[0] <= 0;
                   ok <= 2'd2;
                end
             end
             else begin
                if(ok == 1) begin
                   ok <= 0;
                   A <= A - 1'd1;
                   P <= P + B;
                end
                else begin
                   ok <= 0;
                   A <= A + 1'd1;
                   P <= P - B;
                end
             end
           end
       else state <= s2;
       s2:
          if(P[8] == 1) begin
             P <= P + B;
             A <= A - 1'd1;
          end
          else begin
             if(k > 0) begin
                P[7:0] <= P[8:1];
                P[8] <= 0;
                k <= k - 1'd1;
             end
             else begin
                state <= s3;
             end
          end
      endcase
   end
end

assign quot = A;
assign rem = P[7:0];

endmodule