20141002_KUAS_Verilog_FullAdder(GateLevel)

/******************************************/
/** 20141002 Full Adder (Use Gate Level) **/
/** Maker  : Yan                         **/
/** E-Mail : ssas1115577@gmail.com       **/
/** Date   : 2014/10/02 pm.10:05         **/
/******************************************/

module FullAdder(input1, input2, carryIn, sum, carryOut);
    input       input1, input2, carryIn;
    output      sum, carryOut;
    wire        w1, w2, w3;

    HalfAdder   tmp1(.input1(input1), .input2(input2), .sum(w1), .carryOut(w2));
    HalfAdder   tmp2(.input1(w1), .input2(carryIn), .sum(sum), .carryOut(w3));

    or      (carryOut, w2, w3);
endmodule

module HalfAdder(input1, input2, sum, carryOut);
    input       input1, input2;
    output      sum, carryOut;

    xor     (sum, input1, input2);
    and     (carryOut, input1, input2);
endmodule