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  1. /*!
  2. \file v_data_log.c
  3. \brief 4-х канальный логгер длЯ осциллографированиЯ в реальном времени TDataLog (см. TDataLog)
  4.  
  5. \author Коллектив ООО НПФ Вектор
  6. \version v 2.01 18/09/2012
  7. */
  8.  
  9. /** \addtogroup v_data_log */
  10. /*@{*/
  11.  
  12. //
  13. // TMDX ALPHA RELEASE
  14. // Intended for product evaluation purposes
  15. //
  16. //###########################################################################
  17. //
  18. // FILE: DSP28_Device.h
  19. //
  20. // TITLE: DSP28 Device Definitions.
  21. //
  22. //###########################################################################
  23. //
  24. // Ver | dd mmm yyyy | Who | Description of changes
  25. // =====|=============|======|===============================================
  26. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  27. // 0.56| 20 May 2002 | L.H. | No change
  28. // 0.57| 24 May 2002 | L.H. | Added generic BIT# #define statements
  29. // 0.58| 29 Jun 2002 | L.H. | Added define for CPU Clock Speed and
  30. // | | | microsecond delay calculation
  31. //###########################################################################
  32.  
  33.  
  34. //---------------------------------------------------------------------------
  35. // User To Select Target Device:
  36.  
  37.  
  38.  
  39.  
  40.  
  41. //---------------------------------------------------------------------------
  42. // Used for calculating delays in micro-seconds:
  43. //
  44.  
  45.  
  46. //---------------------------------------------------------------------------
  47. // Common CPU Definitions:
  48. //
  49.  
  50. extern cregister volatile unsigned int IFR;
  51. extern cregister volatile unsigned int IER;
  52.  
  53.  
  54.  
  55.  
  56.  
  57.  
  58. //---------------------------------------------------------------------------
  59. // For Portability, User Is Recommended To Use Following Data Type Size
  60. // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
  61. //
  62.  
  63. typedef int int16;
  64. typedef long int32;
  65. typedef unsigned int Uint16;
  66. typedef unsigned long Uint32;
  67.  
  68. //---------------------------------------------------------------------------
  69. // Include All Peripheral Header Files:
  70. //
  71. extern "C" {
  72.  
  73.  
  74. extern void DSP28x_usDelay(unsigned long Count);
  75. //###########################################################################
  76. //
  77. // FILE: Example.h
  78. //
  79. // TITLE: Example program definition file
  80. //###########################################################################
  81. //
  82. // Ver | dd mmm yyyy | Who | Description of changes
  83. // =====|=============|======|===============================================
  84. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  85. // 0.56| 20 May 2002 | L.H. | No change
  86. // 0.57| 27 May 2002 | L.H. | No change
  87. // 0.58| 29 Jun 2002 | L.H. | No change
  88. //###########################################################################
  89.  
  90.  
  91.  
  92. /*---- shared global function prototypes -----------------------------------*/
  93. extern void InitAdc(void);
  94. extern void InitDevEmu(void);
  95. extern void InitDevice(void);
  96. extern void InitECan(void);
  97. extern void InitEv(void);
  98. extern void InitGpio(void);
  99. extern void InitMcbsp(void);
  100. extern void InitPieCtrl(void);
  101. extern void InitPieVectTable(void);
  102. extern void InitSci(void);
  103. extern void InitSpi(void);
  104. extern void InitSysCtrl(void);
  105. extern void InitXintf(void);
  106. extern void InitXIntrupt(void);
  107.  
  108. // CAUTION
  109. // This function MUST be executed out of RAM. Executing it
  110. // out of OTP/Flash will yield unpredictable results
  111. extern void InitFlash(void);
  112.  
  113.  
  114. extern void KickDog(void);
  115. extern void DisableWD(void);
  116.  
  117. // .c files.
  118.  
  119.  
  120. //
  121. // TMDX ALPHA RELEASE
  122. // Intended for product evaluation purposes
  123. //
  124. //###########################################################################
  125. //
  126. // FILE: DSP28_SysCtrl.h
  127. //
  128. // TITLE: DSP28 Device System Control Register Definitions.
  129. //
  130. //###########################################################################
  131. //
  132. // Ver | dd mmm yyyy | Who | Description of changes
  133. // =====|=============|======|===============================================
  134. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  135. // 0.56| 20 May 2002 | L.H. | No change
  136. // 0.57| 27 May 2002 | L.H. | No change
  137. // 0.58| 29 Jun 2002 | L.H. | No change
  138. // 0.59| 14 Oct 2002 | L.H. | Added bit definitions for the PLLCR Register,
  139. // | | | Low power mode LPMCR0 and LPMCR1 registers
  140. // | | | Added the WDINTS bit to the SCSR register
  141. //###########################################################################
  142.  
  143.  
  144. //---------------------------------------------------------------------------
  145. // System Control Individual Register Bit Definitions:
  146. //
  147. // High speed peripheral clock register bit definitions:
  148. struct HISPCP_BITS { // bits description
  149. Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
  150. Uint16 rsvd1:13; // 15:3 reserved
  151. };
  152.  
  153. union HISPCP_REG {
  154. Uint16 all;
  155. struct HISPCP_BITS bit;
  156. };
  157.  
  158. // Low speed peripheral clock register bit definitions:
  159. struct LOSPCP_BITS { // bits description
  160. Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
  161. Uint16 rsvd1:13; // 15:3 reserved
  162. };
  163.  
  164. union LOSPCP_REG {
  165. Uint16 all;
  166. struct LOSPCP_BITS bit;
  167. };
  168.  
  169. // Peripheral clock control register bit definitions:
  170. struct PCLKCR_BITS { // bits description
  171. Uint16 EVAENCLK:1; // 0 Enable high speed clk to EV-A
  172. Uint16 EVBENCLK:1; // 1 Enable high speed clk to EV-B
  173. Uint16 rsvd1:1; // 2
  174. Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
  175. Uint16 rsvd2:4; // 7:4 reserved
  176. Uint16 SPIENCLK:1; // 8 Enable low speed clk to SPI
  177. Uint16 rsvd3:1; // 9 reserved
  178. Uint16 SCIENCLKA:1; // 10 Enable low speed clk to SCI-A
  179. Uint16 SCIENCLKB:1; // 11 Enable low speed clk to SCI-B
  180. Uint16 MCBSPENCLK:1; // 12 Enable low speed clk to McBSP
  181. Uint16 rsvd4:1; // 13 reserved
  182. Uint16 ECANENCLK:1; // 14 Enable system clk to eCAN
  183. };
  184.  
  185. union PCLKCR_REG {
  186. Uint16 all;
  187. struct PCLKCR_BITS bit;
  188. };
  189.  
  190. // System control and status register bit definitions:
  191. struct SCSR_BITS { // bits description
  192. Uint16 WDOVERRIDE:1; // 0 Allow watchdog disable
  193. Uint16 WDENINT:1; // 1 Enable/disable WD interrupt
  194. Uint16 WDINTS:1; // 2 WD interrupt status bit
  195. Uint16 rsvd1:13; // 15:3 reserved
  196. };
  197.  
  198. union SCSR_REG {
  199. Uint16 all;
  200. struct SCSR_BITS bit;
  201. };
  202.  
  203.  
  204. // PLL control register bit definitions:
  205. struct PLLCR_BITS { // bits description
  206. Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
  207. Uint16 rsvd1:12; // 15:4 reserved
  208. };
  209.  
  210. union PLLCR_REG {
  211. Uint16 all;
  212. struct PLLCR_BITS bit;
  213. };
  214.  
  215. // Low Power Mode 0 control register bit definitions:
  216. struct LPMCR0_BITS { // bits description
  217. Uint16 LPM:2; // 1:0 Set the low power mode
  218. Uint16 QUALSTDBY:6; // 7:2 Qualification
  219. Uint16 rsvd1:8; // 15:8 reserved
  220. };
  221.  
  222. union LPMCR0_REG {
  223. Uint16 all;
  224. struct LPMCR0_BITS bit;
  225. };
  226.  
  227. // Low Power Mode 1 control register bit definitions:
  228. struct LPMCR1_BITS { // bits description
  229. Uint16 XINT1:1; // 0
  230. Uint16 XNMI:1; // 1
  231. Uint16 WDINT:1; // 2
  232. Uint16 T1CTRIP:1; // 3
  233. Uint16 T2CTRIP:1; // 4
  234. Uint16 T3CTRIP:1; // 5
  235. Uint16 T4CTRIP:1; // 6
  236. Uint16 C1TRIP:1; // 7
  237. Uint16 C2TRIP:1; // 8
  238. Uint16 C3TRIP:1; // 9
  239. Uint16 C4TRIP:1; // 10
  240. Uint16 C5TRIP:1; // 11
  241. Uint16 C6TRIP:1; // 12
  242. Uint16 SCIRXA:1; // 13
  243. Uint16 SCIRXB:1; // 14
  244. Uint16 CANRX:1; // 15
  245. };
  246.  
  247. union LPMCR1_REG {
  248. Uint16 all;
  249. struct LPMCR1_BITS bit;
  250. };
  251.  
  252. //---------------------------------------------------------------------------
  253. // System Control Register File:
  254. //
  255. struct SYS_CTRL_REGS {
  256. Uint16 rsvd1[10]; // 0-9
  257. union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler
  258. union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
  259. union PCLKCR_REG PCLKCR; // 12: Peripheral clock control register
  260. Uint16 rsvd2; // 13
  261. union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
  262. union LPMCR1_REG LPMCR1; // 15: Low-power mode control register 1
  263. Uint16 rsvd3; // 16
  264. union PLLCR_REG PLLCR; // 17: PLL control register
  265. union SCSR_REG SCSR; // 18: System control and status register
  266. Uint16 WDCNTR; // 19: WD counter register
  267. Uint16 rsvd4; // 20
  268. Uint16 WDKEY; // 21: WD reset key register
  269. Uint16 rsvd5[3]; // 22-24
  270.  
  271. // No bit definitions are defined for WDCR because
  272. // the proper value must be written to the WDCHK field
  273. // whenever writing to this register.
  274. Uint16 WDCR; // 25: WD timer control register
  275. Uint16 rsvd6[6]; // 26-31
  276. };
  277.  
  278.  
  279. /* --------------------------------------------------- */
  280. /* CSM Registers */
  281. /* */
  282. /* ----------------------------------------------------*/
  283.  
  284. /* CSM Status & Control register bit definitions */
  285. struct CSMSCR_BITS { // bit description
  286. Uint16 SECURE:1; // 0 Secure flag
  287. Uint16 rsvd1:14; // 14-1 reserved
  288. Uint16 FORCESEC:1; // 15 Force Secure control bit
  289.  
  290. };
  291.  
  292. /* Allow access to the bit fields or entire register */
  293. union CSMSCR_REG {
  294. Uint16 all;
  295. struct CSMSCR_BITS bit;
  296. };
  297.  
  298. /* CSM Register File */
  299. struct CSM_REGS {
  300. Uint16 KEY0; // KEY reg bits 15-0
  301. Uint16 KEY1; // KEY reg bits 31-16
  302. Uint16 KEY2; // KEY reg bits 47-32
  303. Uint16 KEY3; // KEY reg bits 63-48
  304. Uint16 KEY4; // KEY reg bits 79-64
  305. Uint16 KEY5; // KEY reg bits 95-80
  306. Uint16 KEY6; // KEY reg bits 111-96
  307. Uint16 KEY7; // KEY reg bits 127-112
  308. Uint16 rsvd1; // reserved
  309. Uint16 rsvd2; // reserved
  310. Uint16 rsvd3; // reserved
  311. Uint16 rsvd4; // reserved
  312. Uint16 rsvd5; // reserved
  313. Uint16 rsvd6; // reserved
  314. Uint16 rsvd7; // reserved
  315. union CSMSCR_REG CSMSCR; // CSM Status & Control register
  316. };
  317.  
  318. /* Password locations */
  319. struct CSM_PWL {
  320. Uint16 PSWD0; // PSWD bits 15-0
  321. Uint16 PSWD1; // PSWD bits 31-16
  322. Uint16 PSWD2; // PSWD bits 47-32
  323. Uint16 PSWD3; // PSWD bits 63-48
  324. Uint16 PSWD4; // PSWD bits 79-64
  325. Uint16 PSWD5; // PSWD bits 95-80
  326. Uint16 PSWD6; // PSWD bits 111-96
  327. Uint16 PSWD7; // PSWD bits 127-112
  328. };
  329.  
  330.  
  331.  
  332. /* Flash Registers */
  333.  
  334.  
  335.  
  336. /* Flash Option Register bit definitions */
  337. struct FOPT_BITS { // bit description
  338. Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
  339. Uint16 rsvd:15; // 1-15 reserved
  340. };
  341.  
  342. /* Allow access to the bit fields or entire register */
  343. union FOPT_REG {
  344. Uint16 all;
  345. struct FOPT_BITS bit;
  346. };
  347.  
  348. /* Flash Power Modes Register bit definitions */
  349. struct FPWR_BITS { // bit description
  350. Uint16 PWR:2; // 0-1 Power Mode bits
  351. Uint16 rsvd:14; // 2-15 reserved
  352. };
  353.  
  354. /* Allow access to the bit fields or entire register */
  355. union FPWR_REG {
  356. Uint16 all;
  357. struct FPWR_BITS bit;
  358. };
  359.  
  360.  
  361. /* Flash Status Register bit definitions */
  362. struct FSTATUS_BITS { // bit description
  363. Uint16 PWRS:2; // 0-1 Power Mode Status bits
  364. Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
  365. Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
  366. Uint16 rsvd1:4; // 4-7 reserved
  367. Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
  368. Uint16 rsvd2:7; // 9-15 reserved
  369. };
  370.  
  371. /* Allow access to the bit fields or entire register */
  372. union FSTATUS_REG {
  373. Uint16 all;
  374. struct FSTATUS_BITS bit;
  375. };
  376.  
  377. /* Flash Sleep to Standby Wait Counter Register bit definitions */
  378. struct FSTDBYWAIT_BITS { // bit description
  379. Uint16 STDBYWAIT:8; // 0-7 Bank/Pump Sleep to Standby Wait Count bits
  380. Uint16 rsvd:8; // 8-15 reserved
  381. };
  382.  
  383. /* Allow access to the bit fields or entire register */
  384. union FSTDBYWAIT_REG {
  385. Uint16 all;
  386. struct FSTDBYWAIT_BITS bit;
  387. };
  388.  
  389. /* Flash Standby to Active Wait Counter Register bit definitions */
  390. struct FACTIVEWAIT_BITS { // bit description
  391. Uint16 ACTIVEWAIT:8; // 0-7 Bank/Pump Standby to Active Wait Count bits
  392. Uint16 rsvd:8; // 8-15 reserved
  393. };
  394.  
  395. /* Allow access to the bit fields or entire register */
  396. union FACTIVEWAIT_REG {
  397. Uint16 all;
  398. struct FACTIVEWAIT_BITS bit;
  399. };
  400.  
  401. /* Bank Read Access Wait State Register bit definitions */
  402. struct FBANKWAIT_BITS { // bit description
  403. Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
  404. Uint16 rsvd1:4; // 4-7 reserved
  405. Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
  406. Uint16 rsvd2:4; // 12-15 reserved
  407. };
  408.  
  409. /* Allow access to the bit fields or entire register */
  410. union FBANKWAIT_REG {
  411. Uint16 all;
  412. struct FBANKWAIT_BITS bit;
  413. };
  414.  
  415. /* OTP Read Access Wait State Register bit definitions */
  416. struct FOTPWAIT_BITS { // bit description
  417. Uint16 OPTWAIT:5; // 0-4 OTP Read Wait State bits
  418. Uint16 rsvd:11; // 5-15 reserved
  419. };
  420.  
  421. /* Allow access to the bit fields or entire register */
  422. union FOTPWAIT_REG {
  423. Uint16 all;
  424. struct FOTPWAIT_BITS bit;
  425. };
  426.  
  427.  
  428. struct FLASH_REGS {
  429. union FOPT_REG FOPT; // Option Register
  430. Uint16 rsvd1; // reserved
  431. union FPWR_REG FPWR; // Power Modes Register
  432. union FSTATUS_REG FSTATUS; // Status Register
  433. union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register
  434. union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register
  435. union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
  436. union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
  437. };
  438.  
  439. //---------------------------------------------------------------------------
  440. // System Control External References & Function Declarations:
  441. //
  442. extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
  443. extern volatile struct CSM_REGS CsmRegs;
  444. extern volatile struct CSM_PWL CsmPwl;
  445. extern volatile struct FLASH_REGS FlashRegs;
  446.  
  447.  
  448. //===========================================================================
  449. // No more.
  450. //===========================================================================
  451. //
  452. // TMDX ALPHA RELEASE
  453. // Intended for product evaluation purposes
  454. //
  455. //###########################################################################
  456. //
  457. // FILE: DSP28_DevEmu.h
  458. //
  459. // TITLE: DSP28 Device Emulation Register Definitions.
  460. //
  461. //###########################################################################
  462. //
  463. // Ver | dd mmm yyyy | Who | Description of changes
  464. // =====|=============|======|===============================================
  465. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  466. // 0.56| 20 May 2002 | L.H. | No change
  467. // 0.57| 27 May 2002 | L.H. | No change
  468. // 0.58| 29 Jun 2002 | L.H. | No change
  469. //###########################################################################
  470.  
  471.  
  472. //---------------------------------------------------------------------------
  473. // Device Emulation Register Bit Definitions:
  474. //
  475. // Device Configuration Register Bit Definitions
  476. struct DEVICECNF_BITS { // bits description
  477. Uint16 rsvd1:3; // 2:0 reserved
  478. Uint16 VMAPS:1; // 3 VMAP Status
  479. Uint16 rsvd2:1; // 4 reserved
  480. Uint16 XRSn:1; // 5 XRSn Signal Status
  481. Uint16 rsvd3:10; // 15:6
  482. Uint16 rsvd4:3; // 18:6
  483. Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection
  484. Uint16 rsvd5:12; // 31:20 reserved
  485. };
  486.  
  487. union DEVICECNF_REG {
  488. Uint32 all;
  489. struct DEVICECNF_BITS bit;
  490. };
  491.  
  492.  
  493. // Device ID Register Bit Definitions
  494. struct DEVICEID_BITS { // bits description
  495. Uint16 PARTID:16; // 15:0 Part ID
  496. Uint16 REVID:16; // 31:16 Revision
  497. };
  498.  
  499. union DEVICEID_REG {
  500. Uint32 all;
  501. struct DEVICEID_BITS bit;
  502. };
  503.  
  504. struct DEV_EMU_REGS {
  505. union DEVICECNF_REG DEVICECNF;
  506. union DEVICEID_REG DEVICEID;
  507. Uint16 PROTSTART;
  508. Uint16 PROTRANGE;
  509. Uint16 rsvd[202];
  510. Uint16 M0RAMDFT;
  511. Uint16 M1RAMDFT;
  512. Uint16 L0RAMDFT;
  513. Uint16 L1RAMDFT;
  514. Uint16 H0RAMDFT;
  515. };
  516.  
  517. //---------------------------------------------------------------------------
  518. // Device Emulation Register References & Function Declarations:
  519. //
  520. extern volatile struct DEV_EMU_REGS DevEmuRegs;
  521.  
  522.  
  523. //===========================================================================
  524. // No more.
  525. //===========================================================================
  526. //
  527. // TMDX ALPHA RELEASE
  528. // Intended for product evaluation purposes
  529. //
  530. //###########################################################################
  531. //
  532. // FILE: DSP28_Xintf.h
  533. //
  534. // TITLE: DSP28 Device External Interface Register Definitions.
  535. //
  536. //###########################################################################
  537. //
  538. // Ver | dd mmm yyyy | Who | Description of changes
  539. // =====|=============|======|===============================================
  540. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  541. // 0.56| 20 May 2002 | L.H. | No change
  542. // 0.57| 27 May 2002 | L.H. | No change
  543. // 0.58| 29 Jun 2002 | L.H. | No change
  544. //###########################################################################
  545.  
  546.  
  547.  
  548. // XINTF timing register bit definitions:
  549. struct XTIMING_BITS { // bits description
  550. Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
  551. Uint16 XWRACTIVE:3; // 4:2 Write access active timing
  552. Uint16 XWRLEAD:2; // 6:5 Write access lead timing
  553. Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
  554. Uint16 XRDACTIVE:3; // 11:9 Read access active timing
  555. Uint16 XRDLEAD:2; // 13:12 Read access lead timing
  556. Uint16 USEREADY:1; // 14 Extend access using HW waitstates
  557. Uint16 READYMODE:1; // 15 Ready mode
  558. Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
  559. Uint16 rsvd1:4; // 21:18 reserved
  560. Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
  561. Uint16 rsvd3:9; // 31:23 reserved
  562. };
  563.  
  564. union XTIMING_REG {
  565. Uint32 all;
  566. struct XTIMING_BITS bit;
  567. };
  568.  
  569. // XINTF control register bit definitions:
  570. struct XINTCNF2_BITS { // bits description
  571. Uint16 WRBUFF:2; // 1:0 Write buffer depth
  572. Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
  573. Uint16 CLKOFF:1; // 3 Disable XCLKOUT
  574. Uint16 rsvd1:2; // 5:4 reserved
  575. Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
  576. Uint16 MPNMC:1; // 8 Micro-processor/micro-computer mode
  577. Uint16 HOLD:1; // 9 Hold enable/disable
  578. Uint16 HOLDS:1; // 10 Current state of HOLDn input
  579. Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
  580. Uint16 rsvd2:4; // 15:12 reserved
  581. Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
  582. Uint16 rsvd3:13; // 31:19 reserved
  583. };
  584.  
  585. union XINTCNF2_REG {
  586. Uint32 all;
  587. struct XINTCNF2_BITS bit;
  588. };
  589.  
  590. // XINTF bank switching register bit definitions:
  591. struct XBANK_BITS { // bits description
  592. Uint16 BANK:2; // 2:0 Zone for which banking is enabled
  593. Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
  594. Uint16 rsvd:10; // 15:6 reserved
  595. };
  596.  
  597. union XBANK_REG {
  598. Uint16 all;
  599. struct XBANK_BITS bit;
  600. };
  601.  
  602.  
  603. //---------------------------------------------------------------------------
  604. // XINTF Register File:
  605. //
  606. struct XINTF_REGS {
  607. union XTIMING_REG XTIMING0;
  608. union XTIMING_REG XTIMING1;
  609. union XTIMING_REG XTIMING2;
  610. Uint32 rsvd1[3];
  611. union XTIMING_REG XTIMING6;
  612. union XTIMING_REG XTIMING7;
  613. Uint32 rsvd2[2];
  614. union XINTCNF2_REG XINTCNF2;
  615. Uint32 rsvd3;
  616. union XBANK_REG XBANK;
  617. Uint16 rsvd4;
  618. Uint16 XREVISION;
  619. Uint16 rsvd5[5];
  620. };
  621.  
  622. //---------------------------------------------------------------------------
  623. // XINTF External References & Function Declarations:
  624. //
  625. extern volatile struct XINTF_REGS XintfRegs;
  626.  
  627.  
  628. //===========================================================================
  629. // No more.
  630. //===========================================================================
  631. //
  632. // TMDX ALPHA RELEASE
  633. // Intended for product evaluation purposes
  634. //
  635. //###########################################################################
  636. //
  637. // FILE: DSP28_CpuTimers.h
  638. //
  639. // TITLE: DSP28 CPU 32-bit Timers Register Definitions.
  640. //
  641. // NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
  642. // other realtime operating systems.
  643. //
  644. // Do not use these two timers in your application if you ever plan
  645. // on integrating DSP-BIOS or another realtime OS.
  646. //
  647. // For this reason, the code to manipulate these two timers is
  648. // commented out and not used in these examples.
  649. //
  650. //###########################################################################
  651. //
  652. // Ver | dd mmm yyyy | Who | Description of changes
  653. // =====|=============|======|===============================================
  654. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  655. // 0.56| 20 May 2002 | L.H. | No change
  656. // 0.57| 27 May 2002 | L.H. | No change
  657. // 0.58| 29 Jun 2002 | L.H. | No change
  658. //###########################################################################
  659.  
  660.  
  661. //---------------------------------------------------------------------------
  662. // CPU Timer Register Bit Definitions:
  663. //
  664. //
  665. // TCR: Control register bit definitions:
  666. struct TCR_BITS { // bits description
  667. Uint16 OUTSTS:1; // 0 Current state of TOUT
  668. Uint16 FORCE:1; // 1 Force TOUT
  669. Uint16 POL:1; // 2 Output polarity
  670. Uint16 TOG:1; // 3 Output toggle mode
  671. Uint16 TSS:1; // 4 Timer Start/Stop
  672. Uint16 TRB:1; // 5 Timer reload
  673. Uint16 FRCEN:1; // 6 Force enable
  674. Uint16 PWIDTH:3; // 9:7 BitTOUT output pulse width
  675. Uint16 SOFT:1; // 10 Emulation modes
  676. Uint16 FREE:1; // 11
  677. Uint16 rsvd:2; // 12:13 reserved
  678. Uint16 TIE:1; // 14 Output enable
  679. Uint16 TIF:1; // 15 Interrupt flag
  680. };
  681.  
  682. union TCR_REG {
  683. Uint16 all;
  684. struct TCR_BITS bit;
  685. };
  686.  
  687. // TPR: Pre-scale low bit definitions:
  688. struct TPR_BITS { // bits description
  689. Uint16 TDDR:8; // 7:0 Divide-down low
  690. Uint16 PSC:8; // 15:8 Prescale counter low
  691. };
  692.  
  693. union TPR_REG {
  694. Uint16 all;
  695. struct TPR_BITS bit;
  696. };
  697.  
  698. // TPRH: Pre-scale high bit definitions:
  699. struct TPRH_BITS { // bits description
  700. Uint16 TDDRH:8; // 7:0 Divide-down high
  701. Uint16 PSCH:8; // 15:8 Prescale counter high
  702. };
  703.  
  704. union TPRH_REG {
  705. Uint16 all;
  706. struct TPRH_BITS bit;
  707. };
  708.  
  709. // TIM, TIMH: Timer register definitions:
  710. struct TIM_REG {
  711. Uint16 LSW;
  712. Uint16 MSW;
  713. };
  714.  
  715. union TIM_GROUP {
  716. Uint32 all;
  717. struct TIM_REG half;
  718. };
  719.  
  720. // PRD, PRDH: Period register definitions:
  721. struct PRD_REG {
  722. Uint16 LSW;
  723. Uint16 MSW;
  724. };
  725.  
  726. union PRD_GROUP {
  727. Uint32 all;
  728. struct PRD_REG half;
  729. };
  730.  
  731. //---------------------------------------------------------------------------
  732. // CPU Timer Register File:
  733. //
  734. struct CPUTIMER_REGS {
  735. union TIM_GROUP TIM; // Timer counter register
  736. union PRD_GROUP PRD; // Period register
  737. union TCR_REG TCR; // Timer control register
  738. Uint16 rsvd1; // reserved
  739. union TPR_REG TPR; // Timer pre-scale low
  740. union TPRH_REG TPRH; // Timer pre-scale high
  741. };
  742.  
  743. //---------------------------------------------------------------------------
  744. // CPU Timer Support Variables:
  745. //
  746. struct CPUTIMER_VARS {
  747. volatile struct CPUTIMER_REGS *RegsAddr;
  748. Uint32 InterruptCount;
  749. float CPUFreqInMHz;
  750. float PeriodInUSec;
  751. };
  752.  
  753. //---------------------------------------------------------------------------
  754. // Function prototypes and external definitions:
  755. //
  756. void InitCpuTimers(void);
  757. void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);
  758.  
  759. extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
  760. extern struct CPUTIMER_VARS CpuTimer0;
  761.  
  762. // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
  763. //extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
  764. extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
  765.  
  766. //extern struct CPUTIMER_VARS CpuTimer1;
  767. extern struct CPUTIMER_VARS CpuTimer2;
  768.  
  769. //---------------------------------------------------------------------------
  770. // Usefull Timer Operations:
  771. //
  772. // Start Timer:
  773.  
  774. // Stop Timer:
  775.  
  776. // Reload Timer With period Value:
  777.  
  778. // Read 32-Bit Timer Value:
  779.  
  780. // Read 32-Bit Period Value:
  781.  
  782. // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
  783. // Do not use these two timers if you ever plan on integrating
  784. // DSP-BIOS or another realtime OS.
  785. //
  786. // For this reason, the code to manipulate these two timers is
  787. // commented out and not used in these examples.
  788.  
  789. // Start Timer:
  790. //#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
  791. //#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
  792.  
  793. // Stop Timer:
  794. //#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
  795. //#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
  796.  
  797. // Reload Timer With period Value:
  798. //#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
  799. //#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
  800.  
  801. // Read 32-Bit Timer Value:
  802. //#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all
  803. //#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all
  804.  
  805. // Read 32-Bit Period Value:
  806. //#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all
  807. //#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all
  808.  
  809.  
  810.  
  811.  
  812. //===========================================================================
  813. // No more.
  814. //===========================================================================
  815. //
  816. // TMDX ALPHA RELEASE
  817. // Intended for product evaluation purposes
  818. //
  819. //###########################################################################
  820. //
  821. // FILE: DSP28_PieCtrl.h
  822. //
  823. // TITLE: DSP28 Device PIE Control Register Definitions.
  824. //
  825. //###########################################################################
  826. //
  827. // Ver | dd mmm yyyy | Who | Description of changes
  828. // =====|=============|======|===============================================
  829. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  830. // 0.56| 20 May 2002 | L.H. | No change
  831. // 0.57| 27 May 2002 | L.H. | No change
  832. // 0.58| 18 Jun 2002 | L.H. | Changed PieCtrl to PieCtrlRegs
  833. //###########################################################################
  834.  
  835.  
  836.  
  837. //---------------------------------------------------------------------------
  838. // PIE Control Register Bit Definitions:
  839. //
  840. // PIECTRL: Register bit definitions:
  841. struct PIECTRL_BITS { // bits description
  842. Uint16 ENPIE:1; // 0 Enable PIE block
  843. Uint16 PIEVECT:15; // 15:1 Fetched vector address
  844. };
  845.  
  846. union PIECTRL_REG {
  847. Uint16 all;
  848. struct PIECTRL_BITS bit;
  849. };
  850.  
  851. // PIEIER: Register bit definitions:
  852. struct PIEIER_BITS { // bits description
  853. Uint16 INTx1:1; // 0 INTx.1
  854. Uint16 INTx2:1; // 1 INTx.2
  855. Uint16 INTx3:1; // 2 INTx.3
  856. Uint16 INTx4:1; // 3 INTx.4
  857. Uint16 INTx5:1; // 4 INTx.5
  858. Uint16 INTx6:1; // 5 INTx.6
  859. Uint16 INTx7:1; // 6 INTx.7
  860. Uint16 INTx8:1; // 7 INTx.8
  861. Uint16 rsvd:8; // 15:8 reserved
  862. };
  863.  
  864. union PIEIER_REG {
  865. Uint16 all;
  866. struct PIEIER_BITS bit;
  867. };
  868.  
  869. // PIEIFR: Register bit definitions:
  870. struct PIEIFR_BITS { // bits description
  871. Uint16 INTx1:1; // 0 INTx.1
  872. Uint16 INTx2:1; // 1 INTx.2
  873. Uint16 INTx3:1; // 2 INTx.3
  874. Uint16 INTx4:1; // 3 INTx.4
  875. Uint16 INTx5:1; // 4 INTx.5
  876. Uint16 INTx6:1; // 5 INTx.6
  877. Uint16 INTx7:1; // 6 INTx.7
  878. Uint16 INTx8:1; // 7 INTx.8
  879. Uint16 rsvd:8; // 15:8 reserved
  880. };
  881.  
  882. union PIEIFR_REG {
  883. Uint16 all;
  884. struct PIEIFR_BITS bit;
  885. };
  886.  
  887. // PIEACK: Register bit definitions:
  888. struct PIEACK_BITS { // bits description
  889. Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
  890. Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
  891. Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
  892. Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
  893. Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
  894. Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
  895. Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
  896. Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
  897. Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
  898. Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
  899. Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
  900. Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
  901. Uint16 rsvd:4; // 15:12 reserved
  902. };
  903.  
  904. union PIEACK_REG {
  905. Uint16 all;
  906. struct PIEACK_BITS bit;
  907. };
  908.  
  909. //---------------------------------------------------------------------------
  910. // PIE Control Register File:
  911. //
  912. struct PIE_CTRL_REGS {
  913. union PIECTRL_REG PIECRTL; // PIE control register
  914. union PIEACK_REG PIEACK; // PIE acknowledge
  915. union PIEIER_REG PIEIER1; // PIE INT1 IER register
  916. union PIEIFR_REG PIEIFR1; // PIE INT1 IFR register
  917. union PIEIER_REG PIEIER2; // PIE INT2 IER register
  918. union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
  919. union PIEIER_REG PIEIER3; // PIE INT3 IER register
  920. union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
  921. union PIEIER_REG PIEIER4; // PIE INT4 IER register
  922. union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
  923. union PIEIER_REG PIEIER5; // PIE INT5 IER register
  924. union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
  925. union PIEIER_REG PIEIER6; // PIE INT6 IER register
  926. union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
  927. union PIEIER_REG PIEIER7; // PIE INT7 IER register
  928. union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
  929. union PIEIER_REG PIEIER8; // PIE INT8 IER register
  930. union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
  931. union PIEIER_REG PIEIER9; // PIE INT9 IER register
  932. union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
  933. union PIEIER_REG PIEIER10; // PIE INT10 IER register
  934. union PIEIFR_REG PIEIFR10; // PIE INT10 IFR register
  935. union PIEIER_REG PIEIER11; // PIE INT11 IER register
  936. union PIEIFR_REG PIEIFR11; // PIE INT11 IFR register
  937. union PIEIER_REG PIEIER12; // PIE INT12 IER register
  938. union PIEIFR_REG PIEIFR12; // PIE INT12 IFR register
  939. };
  940.  
  941.  
  942. //---------------------------------------------------------------------------
  943. // PIE Control Registers External References & Function Declarations:
  944. //
  945. extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
  946.  
  947.  
  948. //===========================================================================
  949. // No more.
  950. //===========================================================================
  951. //
  952. // TMDX ALPHA RELEASE
  953. // Intended for product evaluation purposes
  954. //
  955. //###########################################################################
  956. //
  957. // FILE: DSP28_PieVect.h
  958. //
  959. // TITLE: DSP28 Devices PIE Vector Table Definitions.
  960. //
  961. //###########################################################################
  962. //
  963. // Ver | dd mmm yyyy | Who | Description of changes
  964. // =====|=============|======|===============================================
  965. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  966. // 0.56| 20 May 2002 | L.H. | No change
  967. // 0.57| 27 May 2002 | L.H. | No change
  968. // 0.58| 29 Jun 2002 | L.H. | No change
  969. //###########################################################################
  970.  
  971.  
  972.  
  973. //---------------------------------------------------------------------------
  974. // PIE Interrupt Vector Table Definition:
  975. //
  976. // Create a user type called PINT (pointer to interrupt):
  977.  
  978. typedef interrupt void(*PINT)(void);
  979.  
  980. // Define Vector Table:
  981. struct PIE_VECT_TABLE {
  982.  
  983. // Reset is never fetched from this table.
  984. // It will always be fetched from 0x3FFFC0 in either
  985. // boot ROM or XINTF Zone 7 depending on the state of
  986. // the XMP/MC input signal. On the F2810 it is always
  987. // fetched from boot ROM.
  988.  
  989. PINT PIE1_RESERVED;
  990. PINT PIE2_RESERVED;
  991. PINT PIE3_RESERVED;
  992. PINT PIE4_RESERVED;
  993. PINT PIE5_RESERVED;
  994. PINT PIE6_RESERVED;
  995. PINT PIE7_RESERVED;
  996. PINT PIE8_RESERVED;
  997. PINT PIE9_RESERVED;
  998. PINT PIE10_RESERVED;
  999. PINT PIE11_RESERVED;
  1000. PINT PIE12_RESERVED;
  1001. PINT PIE13_RESERVED;
  1002.  
  1003. // Non-Peripheral Interrupts:
  1004. PINT XINT13; // XINT13
  1005. PINT TINT2; // CPU-Timer2
  1006. PINT DATALOG; // Datalogging interrupt
  1007. PINT RTOSINT; // RTOS interrupt
  1008. PINT EMUINT; // Emulation interrupt
  1009. PINT XNMI; // Non-maskable interrupt
  1010. PINT ILLEGAL; // Illegal operation TRAP
  1011. PINT USER0; // User Defined trap 0
  1012. PINT USER1; // User Defined trap 1
  1013. PINT USER2; // User Defined trap 2
  1014. PINT USER3; // User Defined trap 3
  1015. PINT USER4; // User Defined trap 4
  1016. PINT USER5; // User Defined trap 5
  1017. PINT USER6; // User Defined trap 6
  1018. PINT USER7; // User Defined trap 7
  1019. PINT USER8; // User Defined trap 8
  1020. PINT USER9; // User Defined trap 9
  1021. PINT USER10; // User Defined trap 10
  1022. PINT USER11; // User Defined trap 11
  1023.  
  1024. // Group 1 PIE Peripheral Vectors:
  1025. PINT PDPINTA; // EV-A
  1026. PINT PDPINTB; // EV-B
  1027. PINT rsvd1_3;
  1028. PINT XINT1;
  1029. PINT XINT2;
  1030. PINT ADCINT; // ADC
  1031. PINT TINT0; // Timer 0
  1032. PINT WAKEINT; // WD
  1033.  
  1034. // Group 2 PIE Peripheral Vectors:
  1035. PINT CMP1INT; // EV-A
  1036. PINT CMP2INT; // EV-A
  1037. PINT CMP3INT; // EV-A
  1038. PINT T1PINT; // EV-A
  1039. PINT T1CINT; // EV-A
  1040. PINT T1UFINT; // EV-A
  1041. PINT T1OFINT; // EV-A
  1042. PINT rsvd2_8;
  1043.  
  1044. // Group 3 PIE Peripheral Vectors:
  1045. PINT T2PINT; // EV-A
  1046. PINT T2CINT; // EV-A
  1047. PINT T2UFINT; // EV-A
  1048. PINT T2OFINT; // EV-A
  1049. PINT CAPINT1; // EV-A
  1050. PINT CAPINT2; // EV-A
  1051. PINT CAPINT3; // EV-A
  1052. PINT rsvd3_8;
  1053.  
  1054. // Group 4 PIE Peripheral Vectors:
  1055. PINT CMP4INT; // EV-B
  1056. PINT CMP5INT; // EV-B
  1057. PINT CMP6INT; // EV-B
  1058. PINT T3PINT; // EV-B
  1059. PINT T3CINT; // EV-B
  1060. PINT T3UFINT; // EV-B
  1061. PINT T3OFINT; // EV-B
  1062. PINT rsvd4_8;
  1063.  
  1064. // Group 5 PIE Peripheral Vectors:
  1065. PINT T4PINT; // EV-B
  1066. PINT T4CINT; // EV-B
  1067. PINT T4UFINT; // EV-B
  1068. PINT T4OFINT; // EV-B
  1069. PINT CAPINT4; // EV-B
  1070. PINT CAPINT5; // EV-B
  1071. PINT CAPINT6; // EV-B
  1072. PINT rsvd5_8;
  1073.  
  1074. // Group 6 PIE Peripheral Vectors:
  1075. PINT SPIRXINTA; // SPI-A
  1076. PINT SPITXINTA; // SPI-A
  1077. PINT rsvd6_3;
  1078. PINT rsvd6_4;
  1079. PINT MRINTA; // McBSP-A
  1080. PINT MXINTA; // McBSP-A
  1081. PINT rsvd6_7;
  1082. PINT rsvd6_8;
  1083.  
  1084. // Group 7 PIE Peripheral Vectors:
  1085. PINT rsvd7_1;
  1086. PINT rsvd7_2;
  1087. PINT rsvd7_3;
  1088. PINT rsvd7_4;
  1089. PINT rsvd7_5;
  1090. PINT rsvd7_6;
  1091. PINT rsvd7_7;
  1092. PINT rsvd7_8;
  1093.  
  1094. // Group 8 PIE Peripheral Vectors:
  1095. PINT rsvd8_1;
  1096. PINT rsvd8_2;
  1097. PINT rsvd8_3;
  1098. PINT rsvd8_4;
  1099. PINT rsvd8_5;
  1100. PINT rsvd8_6;
  1101. PINT rsvd8_7;
  1102. PINT rsvd8_8;
  1103.  
  1104. // Group 9 PIE Peripheral Vectors:
  1105. PINT RXAINT; // SCI-A
  1106. PINT TXAINT; // SCI-A
  1107. PINT RXBINT; // SCI-B
  1108. PINT TXBINT; // SCI-B
  1109. PINT ECAN0INTA; // eCAN
  1110. PINT ECAN1INTA; // eCAN
  1111. PINT rsvd9_7;
  1112. PINT rsvd9_8;
  1113.  
  1114. // Group 10 PIE Peripheral Vectors:
  1115. PINT rsvd10_1;
  1116. PINT rsvd10_2;
  1117. PINT rsvd10_3;
  1118. PINT rsvd10_4;
  1119. PINT rsvd10_5;
  1120. PINT rsvd10_6;
  1121. PINT rsvd10_7;
  1122. PINT rsvd10_8;
  1123.  
  1124. // Group 11 PIE Peripheral Vectors:
  1125. PINT rsvd11_1;
  1126. PINT rsvd11_2;
  1127. PINT rsvd11_3;
  1128. PINT rsvd11_4;
  1129. PINT rsvd11_5;
  1130. PINT rsvd11_6;
  1131. PINT rsvd11_7;
  1132. PINT rsvd11_8;
  1133.  
  1134. // Group 12 PIE Peripheral Vectors:
  1135. PINT rsvd12_1;
  1136. PINT rsvd12_2;
  1137. PINT rsvd12_3;
  1138. PINT rsvd12_4;
  1139. PINT rsvd12_5;
  1140. PINT rsvd12_6;
  1141. PINT rsvd12_7;
  1142. PINT rsvd12_8;
  1143. };
  1144.  
  1145. //---------------------------------------------------------------------------
  1146. // PIE Interrupt Vector Table External References & Function Declarations:
  1147. //
  1148. extern struct PIE_VECT_TABLE PieVectTable;
  1149.  
  1150.  
  1151.  
  1152. //===========================================================================
  1153. // No more.
  1154. //===========================================================================
  1155.  
  1156. //###########################################################################
  1157. //
  1158. // FILE: DSP28_DefaultIsr.h
  1159. //
  1160. // TITLE: DSP28 Devices Default Interrupt Service Routines Definitions.
  1161. //
  1162. //###########################################################################
  1163. //
  1164. // Ver | dd mmm yyyy | Who | Description of changes
  1165. // =====|=============|======|===============================================
  1166. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  1167. // 0.56| 20 May 2002 | L.H. | No change
  1168. // 0.57| 27 May 2002 | L.H. | No change
  1169. // 0.58| 29 Jun 2002 | L.H. | No change
  1170. //###########################################################################
  1171.  
  1172.  
  1173. //---------------------------------------------------------------------------
  1174. // Default Interrupt Service Routine Declarations:
  1175. //
  1176. // The following function prototypes are for the
  1177. // default ISR routines used with the default PIE vector table.
  1178. // This default vector table is found in the DSP28_PieVect.h
  1179. // file.
  1180. //
  1181.  
  1182. // Non-Peripheral Interrupts:
  1183. interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
  1184. interrupt void INT14_ISR(void); // CPU-Timer2
  1185. interrupt void DATALOG_ISR(void); // Datalogging interrupt
  1186. interrupt void RTOSINT_ISR(void); // RTOS interrupt
  1187. interrupt void EMUINT_ISR(void); // Emulation interrupt
  1188. interrupt void NMI_ISR(void); // Non-maskable interrupt
  1189. interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
  1190. interrupt void USER0_ISR(void); // User Defined trap 0
  1191. interrupt void USER1_ISR(void); // User Defined trap 1
  1192. interrupt void USER2_ISR(void); // User Defined trap 2
  1193. interrupt void USER3_ISR(void); // User Defined trap 3
  1194. interrupt void USER4_ISR(void); // User Defined trap 4
  1195. interrupt void USER5_ISR(void); // User Defined trap 5
  1196. interrupt void USER6_ISR(void); // User Defined trap 6
  1197. interrupt void USER7_ISR(void); // User Defined trap 7
  1198. interrupt void USER8_ISR(void); // User Defined trap 8
  1199. interrupt void USER9_ISR(void); // User Defined trap 9
  1200. interrupt void USER10_ISR(void); // User Defined trap 10
  1201. interrupt void USER11_ISR(void); // User Defined trap 11
  1202.  
  1203. // Group 1 PIE Interrupt Service Routines:
  1204. interrupt void PDPINTA_ISR(void); // EV-A
  1205. interrupt void PDPINTB_ISR(void); // EV-B
  1206. interrupt void XINT1_ISR(void);
  1207. interrupt void XINT2_ISR(void);
  1208. interrupt void ADCINT_ISR(void); // ADC
  1209. interrupt void TINT0_ISR(void); // Timer 0
  1210. interrupt void WAKEINT_ISR(void); // WD
  1211.  
  1212. // Group 2 PIE Interrupt Service Routines:
  1213. interrupt void CMP1INT_ISR(void); // EV-A
  1214. interrupt void CMP2INT_ISR(void); // EV-A
  1215. interrupt void CMP3INT_ISR(void); // EV-A
  1216. interrupt void T1PINT_ISR(void); // EV-A
  1217. interrupt void T1CINT_ISR(void); // EV-A
  1218. interrupt void T1UFINT_ISR(void); // EV-A
  1219. interrupt void T1OFINT_ISR(void); // EV-A
  1220.  
  1221. // Group 3 PIE Interrupt Service Routines:
  1222. interrupt void T2PINT_ISR(void); // EV-A
  1223. interrupt void T2CINT_ISR(void); // EV-A
  1224. interrupt void T2UFINT_ISR(void); // EV-A
  1225. interrupt void T2OFINT_ISR(void); // EV-A
  1226. interrupt void CAPINT1_ISR(void); // EV-A
  1227. interrupt void CAPINT2_ISR(void); // EV-A
  1228. interrupt void CAPINT3_ISR(void); // EV-A
  1229.  
  1230. // Group 4 PIE Interrupt Service Routines:
  1231. interrupt void CMP4INT_ISR(void); // EV-B
  1232. interrupt void CMP5INT_ISR(void); // EV-B
  1233. interrupt void CMP6INT_ISR(void); // EV-B
  1234. interrupt void T3PINT_ISR(void); // EV-B
  1235. interrupt void T3CINT_ISR(void); // EV-B
  1236. interrupt void T3UFINT_ISR(void); // EV-B
  1237. interrupt void T3OFINT_ISR(void); // EV-B
  1238.  
  1239. // Group 5 PIE Interrupt Service Routines:
  1240. interrupt void T4PINT_ISR(void); // EV-B
  1241. interrupt void T4CINT_ISR(void); // EV-B
  1242. interrupt void T4UFINT_ISR(void); // EV-B
  1243. interrupt void T4OFINT_ISR(void); // EV-B
  1244. interrupt void CAPINT4_ISR(void); // EV-B
  1245. interrupt void CAPINT5_ISR(void); // EV-B
  1246. interrupt void CAPINT6_ISR(void); // EV-B
  1247.  
  1248. // Group 6 PIE Interrupt Service Routines:
  1249. interrupt void SPIRXINTA_ISR(void); // SPI
  1250. interrupt void SPITXINTA_ISR(void); // SPI
  1251. interrupt void MRINTA_ISR(void); // McBSP
  1252. interrupt void MXINTA_ISR(void); // McBSP
  1253.  
  1254.  
  1255. // Group 9 PIE Interrupt Service Routines:
  1256. interrupt void SCIRXINTA_ISR(void); // SCI-A
  1257. interrupt void SCITXINTA_ISR(void); // SCI-A
  1258. interrupt void SCIRXINTB_ISR(void); // SCI-B
  1259. interrupt void SCITXINTB_ISR(void); // SCI-B
  1260. interrupt void ECAN0INTA_ISR(void); // eCAN
  1261. interrupt void ECAN1INTA_ISR(void); // eCAN
  1262.  
  1263.  
  1264. // Catch-all for Reserved Locations For testing purposes:
  1265. interrupt void PIE_RESERVED(void); // Reserved for test
  1266. interrupt void rsvd_ISR(void); // for test
  1267.  
  1268.  
  1269. //
  1270. // TMDX BETA RELEASE
  1271. // Intended for product evaluation purposes
  1272. //
  1273. //###########################################################################
  1274. //
  1275. // FILE: DSP28_SWPrioritizedIsrLevels.h
  1276. //
  1277. // TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine
  1278. // Level definitions.
  1279. //
  1280. //###########################################################################
  1281. //
  1282. // Ver | dd mmm yyyy | Who | Description of changes
  1283. // =====|=============|======|===============================================
  1284. // 0.1 | 30 Jan 2002 | A.T. | Original Release
  1285. //###########################################################################
  1286.  
  1287.  
  1288.  
  1289. //-------------------------------------------------------------------------------
  1290. // Interrupt Enable Register Allocation For F2810/12 Devices:
  1291. //-------------------------------------------------------------------------------
  1292. // Interrupts can be enabled/disabled using the CPU interrupt enable register
  1293. // (IER) and the PIE interrupt enable registers (PIIER1 to PIEIER12). The table
  1294. // below lists the allocation of the various interrupts to these registers:
  1295. //
  1296. //-----------------------------------------------------------------------------------
  1297. // CPU | PIEIER1 to PIEIER12 |
  1298. // IER | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
  1299. // =====|=========|=========|=========|=========|=========|=========|=======|=======|
  1300. // INT1 |PDPINTA |PDPINTB | resvd | XINT1 | XINT2 |ADCINT | TINT0 |WAKEINT|
  1301. // | (EV-A) | (EV-B) | | | | | | |
  1302. // INT2 |CMP1INT |CMP2INT |CMP3INT |T1PINT |T1CINT |T1UFINT |T1OFINT| resvd |
  1303. // | (EV-A) | (EV-A) |(EV-A) |(EV-A) |(EV-A) |(EV-A) |(EV-A) | |
  1304. // INT3 |T2PINT |T2CINT |T2UFINT |T2OFINT |CAPINT1 |CAPINT2 |CAPINT3| resvd |
  1305. // | (EV-A) | (EV-A) |(EV-A) |(EV-A) |(EV-A) |(EV-A) |(EV-A) | |
  1306. // INT4 |CMP4INT |CMP5INT |CMP6INT |T3PINT |T3CINT |T3UFINT |T3OFINT| resvd |
  1307. // | (EV-B) | (EV-B) |(EV-B) |(EV-B) |(EV-B) |(EV-B) |(EV-B) | |
  1308. // INT5 |T4PINT |T4CINT |T4UFINT |T4OFINT |CAPINT4 |CAPINT5 |CAPINT6| resvd |
  1309. // | (EV-B) | (EV-B) |(EV-B) |(EV-B) |(EV-B) |(EV-B) |(EV-B) | |
  1310. // INT6 |SPIRXINTA|SPITXINTA| resvd | resvd | MRINTA | MXINTA | resvd | resvd |
  1311. // | (SPI-A) | (SPI-A) | | |(McBSP-A)|(McBSP-A)| | |
  1312. // INT7 | resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
  1313. // INT8 | resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
  1314. // INT9 |SCIRXINTA|SCITXINTA|SCIRXINTB|SCITXINTB|ECAN0INTA|ECAN1INTA| resvd | resvd |
  1315. // | (SCI-A) | (SCI-A) |(SCI-B) |(SCI-B) |(ECAN-A) |(ECAN-A) | | |
  1316. // INT10| resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
  1317. // INT11| resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
  1318. // INT12| resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
  1319. //-------------------------------------------------------------------------------
  1320. // INT13| INT13
  1321. // INT14| INT14
  1322. // INT15| DATALOG
  1323. // INT16| RTOSINT
  1324. //-------------------------------------------------------------------------------
  1325. //
  1326. //-------------------------------------------------------------------------------
  1327. // Set "Global" Interrupt Priority Level (IER register):
  1328. //-------------------------------------------------------------------------------
  1329. // The user must set the appropriate priority level for each of the CPU
  1330. // interrupts. This is termed as the "global" priority. The priority level
  1331. // must be a number between 1 (highest) to 16 (lowest). A value of 0 must
  1332. // be entered for reserved interrupts or interrupts that are not used. This
  1333. // will also reduce code size by not including ISR's that are not used.
  1334. //
  1335. // Note: The priority levels below are used to calculate the IER register
  1336. // interrupt masks MINT1 to MINT16.
  1337. //
  1338. //
  1339. // Note: The priority levels shown here may not make sense in a
  1340. // real application. This is for demonstration purposes only!!!
  1341. //
  1342. // The user should change these to values that make sense for
  1343. // their application.
  1344. //
  1345. // 0 = not used
  1346. // 1 = highest priority
  1347. // ...
  1348. // 16 = lowest priority
  1349.  
  1350. //-------------------------------------------------------------------------------
  1351. // Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers):
  1352. //-------------------------------------------------------------------------------
  1353. // The user must set the appropriate priority level for each of the PIE
  1354. // interrupts. This is termed as the "group" priority. The priority level
  1355. // must be a number between 1 (highest) to 8 (lowest). A value of 0 must
  1356. // be entered for reserved interrupts or interrupts that are not used. This
  1357. // will also reduce code size by not including ISR's that are not used:
  1358. //
  1359. // Note: The priority levels below are used to calculate the following
  1360. // PIEIER register interrupt masks:
  1361. // MG11 to MG18
  1362. // MG21 to MG28
  1363. // MG31 to MG38
  1364. // MG41 to MG48
  1365. // MG51 to MG58
  1366. // MG61 to MG68
  1367. // MG71 to MG78
  1368. // MG81 to MG88
  1369. // MG91 to MG98
  1370. // MG101 to MG108
  1371. // MG111 to MG118
  1372. // MG121 to MG128
  1373. //
  1374. // Note: The priority levels shown here may not make sense in a
  1375. // real application. This is for demonstration purposes only!!!
  1376. //
  1377. // The user should change these to values that make sense for
  1378. // their application.
  1379. //
  1380. // 0 = not used
  1381. // 1 = highest priority
  1382. // ...
  1383. // 8 = lowest priority
  1384. //
  1385.  
  1386.  
  1387.  
  1388.  
  1389.  
  1390.  
  1391.  
  1392.  
  1393.  
  1394.  
  1395.  
  1396.  
  1397.  
  1398. // There should be no need to modify code below this line
  1399. //-------------------------------------------------------------------------------
  1400. // Automatically generate IER interrupt masks MINT1 to MINT16:
  1401. //
  1402.  
  1403. // Beginning of MINT1:
  1404.  
  1405.  
  1406.  
  1407.  
  1408.  
  1409.  
  1410.  
  1411.  
  1412.  
  1413.  
  1414.  
  1415.  
  1416.  
  1417.  
  1418.  
  1419.  
  1420. // End Of MINT1.
  1421.  
  1422. // Beginning of MINT2:
  1423.  
  1424.  
  1425.  
  1426.  
  1427.  
  1428.  
  1429.  
  1430.  
  1431.  
  1432.  
  1433.  
  1434.  
  1435.  
  1436.  
  1437.  
  1438.  
  1439. // End Of MINT2.
  1440.  
  1441. // Beginning of MINT3:
  1442.  
  1443.  
  1444.  
  1445.  
  1446.  
  1447.  
  1448.  
  1449.  
  1450.  
  1451.  
  1452.  
  1453.  
  1454.  
  1455.  
  1456.  
  1457.  
  1458. // End Of MINT3.
  1459.  
  1460. // Beginning of MINT4:
  1461.  
  1462.  
  1463.  
  1464.  
  1465.  
  1466.  
  1467.  
  1468.  
  1469.  
  1470.  
  1471.  
  1472.  
  1473.  
  1474.  
  1475.  
  1476.  
  1477. // End Of MINT4.
  1478.  
  1479. // Beginning of MINT5:
  1480.  
  1481.  
  1482.  
  1483.  
  1484.  
  1485.  
  1486.  
  1487.  
  1488.  
  1489.  
  1490.  
  1491.  
  1492.  
  1493.  
  1494.  
  1495.  
  1496. // End Of MINT5.
  1497.  
  1498. // Beginning of MINT6:
  1499.  
  1500.  
  1501.  
  1502.  
  1503.  
  1504.  
  1505.  
  1506.  
  1507.  
  1508.  
  1509.  
  1510.  
  1511.  
  1512.  
  1513.  
  1514.  
  1515. // End Of MINT6.
  1516.  
  1517. // Beginning of MINT7:
  1518.  
  1519.  
  1520.  
  1521.  
  1522.  
  1523.  
  1524.  
  1525.  
  1526.  
  1527.  
  1528.  
  1529.  
  1530.  
  1531.  
  1532.  
  1533.  
  1534. // End Of MINT7.
  1535.  
  1536. // Beginning of MINT8:
  1537.  
  1538.  
  1539.  
  1540.  
  1541.  
  1542.  
  1543.  
  1544.  
  1545.  
  1546.  
  1547.  
  1548.  
  1549.  
  1550.  
  1551.  
  1552.  
  1553. // End Of MINT8.
  1554.  
  1555. // Beginning of MINT9:
  1556.  
  1557.  
  1558.  
  1559.  
  1560.  
  1561.  
  1562.  
  1563.  
  1564.  
  1565.  
  1566.  
  1567.  
  1568.  
  1569.  
  1570.  
  1571.  
  1572. // End Of MINT9.
  1573.  
  1574. // Beginning of MINT10:
  1575.  
  1576.  
  1577.  
  1578.  
  1579.  
  1580.  
  1581.  
  1582.  
  1583.  
  1584.  
  1585.  
  1586.  
  1587.  
  1588.  
  1589.  
  1590.  
  1591. // End Of MINT10.
  1592.  
  1593. // Beginning of MINT11:
  1594.  
  1595.  
  1596.  
  1597.  
  1598.  
  1599.  
  1600.  
  1601.  
  1602.  
  1603.  
  1604.  
  1605.  
  1606.  
  1607.  
  1608.  
  1609.  
  1610. // End Of MINT11.
  1611.  
  1612. // Beginning of MINT12:
  1613.  
  1614.  
  1615.  
  1616.  
  1617.  
  1618.  
  1619.  
  1620.  
  1621.  
  1622.  
  1623.  
  1624.  
  1625.  
  1626.  
  1627.  
  1628.  
  1629. // End Of MINT12.
  1630.  
  1631. // Beginning of MINT13:
  1632.  
  1633.  
  1634.  
  1635.  
  1636.  
  1637.  
  1638.  
  1639.  
  1640.  
  1641.  
  1642.  
  1643.  
  1644.  
  1645.  
  1646.  
  1647.  
  1648. // End Of MINT13.
  1649.  
  1650. // Beginning of MINT14:
  1651.  
  1652.  
  1653.  
  1654.  
  1655.  
  1656.  
  1657.  
  1658.  
  1659.  
  1660.  
  1661.  
  1662.  
  1663.  
  1664.  
  1665.  
  1666.  
  1667. // End Of MINT14.
  1668.  
  1669. // Beginning of MINT15:
  1670.  
  1671.  
  1672.  
  1673.  
  1674.  
  1675.  
  1676.  
  1677.  
  1678.  
  1679.  
  1680.  
  1681.  
  1682.  
  1683.  
  1684.  
  1685.  
  1686. // End Of MINT15.
  1687.  
  1688. // Beginning of MINT16:
  1689.  
  1690.  
  1691.  
  1692.  
  1693.  
  1694.  
  1695.  
  1696.  
  1697.  
  1698.  
  1699.  
  1700.  
  1701.  
  1702.  
  1703.  
  1704.  
  1705. // End Of MINT16.
  1706.  
  1707. //-------------------------------------------------------------------------------
  1708. // Automatically generate PIEIER1 interrupt masks MG11 to MG18:
  1709.  
  1710. // Beginning of MG11:
  1711.  
  1712.  
  1713.  
  1714.  
  1715.  
  1716.  
  1717.  
  1718. // End of MG11:
  1719.  
  1720. // Beginning of MG12:
  1721. // End of MG12:
  1722.  
  1723. // Beginning of MG13:
  1724. // End of MG13:
  1725.  
  1726. // Beginning of MG14:
  1727. // End of MG14:
  1728.  
  1729. // Beginning of MG15:
  1730. // End of MG15:
  1731.  
  1732. // Beginning of MG16:
  1733. // End of MG16:
  1734.  
  1735. // Beginning of MG17:
  1736. // End of MG17:
  1737.  
  1738. // Beginning of MG18:
  1739. // End of MG18:
  1740.  
  1741. //-------------------------------------------------------------------------------
  1742. // Automatically generate PIEIER1 interrupt masks MG21 to MG28:
  1743. //
  1744.  
  1745. // Beginning of MG21:
  1746. // End of MG21:
  1747.  
  1748. // Beginning of MG22:
  1749. // End of MG22:
  1750.  
  1751. // Beginning of MG23:
  1752. // End of MG23:
  1753.  
  1754. // Beginning of MG24:
  1755. // End of MG24:
  1756.  
  1757. // Beginning of MG25:
  1758. // End of MG25:
  1759.  
  1760. // Beginning of MG26:
  1761. // End of MG26:
  1762.  
  1763. // Beginning of MG27:
  1764. // End of MG27:
  1765.  
  1766. // Beginning of MG28:
  1767. // End of MG28:
  1768.  
  1769. //-------------------------------------------------------------------------------
  1770. // Automatically generate PIEIER1 interrupt masks MG31 to MG38:
  1771. //
  1772.  
  1773. // Beginning of MG31:
  1774. // End of MG31:
  1775.  
  1776. // Beginning of MG32:
  1777. // End of MG32:
  1778.  
  1779. // Beginning of MG33:
  1780. // End of MG33:
  1781.  
  1782. // Beginning of MG34:
  1783. // End of MG34:
  1784.  
  1785. // Beginning of MG35:
  1786. // End of MG35:
  1787.  
  1788. // Beginning of MG36:
  1789. // End of MG36:
  1790.  
  1791. // Beginning of MG37:
  1792. // End of MG37:
  1793.  
  1794. // Beginning of MG38:
  1795. // End of MG38:
  1796.  
  1797. //-------------------------------------------------------------------------------
  1798. // Automatically generate PIEIER1 interrupt masks MG41 to MG48:
  1799. //
  1800.  
  1801. // Beginning of MG41:
  1802. // End of MG41:
  1803.  
  1804. // Beginning of MG42:
  1805. // End of MG42:
  1806.  
  1807. // Beginning of MG43:
  1808. // End of MG43:
  1809.  
  1810. // Beginning of MG44:
  1811. // End of MG44:
  1812.  
  1813. // Beginning of MG45:
  1814. // End of MG45:
  1815.  
  1816. // Beginning of MG46:
  1817. // End of MG46:
  1818.  
  1819. // Beginning of MG47:
  1820. // End of MG47:
  1821.  
  1822. // Beginning of MG48:
  1823. // End of MG48:
  1824.  
  1825. //-------------------------------------------------------------------------------
  1826. // Automatically generate PIEIER1 interrupt masks MG51 to MG58:
  1827. //
  1828.  
  1829. // Beginning of MG51:
  1830. // End of MG51:
  1831.  
  1832. // Beginning of MG52:
  1833. // End of MG52:
  1834.  
  1835. // Beginning of MG53:
  1836. // End of MG53:
  1837.  
  1838. // Beginning of MG54:
  1839. // End of MG54:
  1840.  
  1841. // Beginning of MG55:
  1842. // End of MG55:
  1843.  
  1844. // Beginning of MG56:
  1845. // End of MG56:
  1846.  
  1847. // Beginning of MG57:
  1848. // End of MG57:
  1849.  
  1850. // Beginning of MG58:
  1851. // End of MG58:
  1852.  
  1853. //-------------------------------------------------------------------------------
  1854. // Automatically generate PIEIER1 interrupt masks MG61 to MG68:
  1855. //
  1856.  
  1857. // Beginning of MG61:
  1858. // End of MG61:
  1859.  
  1860. // Beginning of MG62:
  1861. // End of MG62:
  1862.  
  1863. // Beginning of MG63:
  1864. // End of MG63:
  1865.  
  1866. // Beginning of MG64:
  1867. // End of MG64:
  1868.  
  1869. // Beginning of MG65:
  1870. // End of MG65:
  1871.  
  1872. // Beginning of MG66:
  1873. // End of MG66:
  1874.  
  1875. // Beginning of MG67:
  1876. // End of MG67:
  1877.  
  1878. // Beginning of MG68:
  1879. // End of MG68:
  1880.  
  1881. //-------------------------------------------------------------------------------
  1882. // Automatically generate PIEIER1 interrupt masks MG71 to MG78:
  1883. //
  1884.  
  1885. // Beginning of MG71:
  1886. // End of MG71:
  1887.  
  1888. // Beginning of MG72:
  1889. // End of MG72:
  1890.  
  1891. // Beginning of MG73:
  1892. // End of MG73:
  1893.  
  1894. // Beginning of MG74:
  1895. // End of MG74:
  1896.  
  1897. // Beginning of MG75:
  1898. // End of MG75:
  1899.  
  1900. // Beginning of MG76:
  1901. // End of MG76:
  1902.  
  1903. // Beginning of MG77:
  1904. // End of MG77:
  1905.  
  1906. // Beginning of MG78:
  1907. // End of MG78:
  1908.  
  1909. //-------------------------------------------------------------------------------
  1910. // Automatically generate PIEIER1 interrupt masks MG81 to MG88:
  1911. //
  1912.  
  1913. // Beginning of MG81:
  1914. // End of MG81:
  1915.  
  1916. // Beginning of MG82:
  1917. // End of MG82:
  1918.  
  1919. // Beginning of MG83:
  1920. // End of MG83:
  1921.  
  1922. // Beginning of MG84:
  1923. // End of MG84:
  1924.  
  1925. // Beginning of MG85:
  1926. // End of MG85:
  1927.  
  1928. // Beginning of MG86:
  1929. // End of MG86:
  1930.  
  1931. // Beginning of MG87:
  1932. // End of MG87:
  1933.  
  1934. // Beginning of MG88:
  1935. // End of MG88:
  1936.  
  1937. //-------------------------------------------------------------------------------
  1938. // Automatically generate PIEIER1 interrupt masks MG91 to MG98:
  1939. //
  1940.  
  1941. // Beginning of MG91:
  1942. // End of MG91:
  1943.  
  1944. // Beginning of MG92:
  1945. // End of MG92:
  1946.  
  1947. // Beginning of MG93:
  1948. // End of MG93:
  1949.  
  1950. // Beginning of MG94:
  1951. // End of MG94:
  1952.  
  1953. // Beginning of MG95:
  1954. // End of MG95:
  1955.  
  1956. // Beginning of MG96:
  1957. // End of MG96:
  1958.  
  1959. // Beginning of MG97:
  1960. // End of MG97:
  1961.  
  1962. // Beginning of MG98:
  1963. // End of MG98:
  1964.  
  1965. //-------------------------------------------------------------------------------
  1966. // Automatically generate PIEIER1 interrupt masks MG101 to MG108:
  1967. //
  1968.  
  1969. // Beginning of MG101:
  1970. // End of MG101:
  1971.  
  1972. // Beginning of MG102:
  1973. // End of MG102:
  1974.  
  1975. // Beginning of MG103:
  1976. // End of MG103:
  1977.  
  1978. // Beginning of MG104:
  1979. // End of MG104:
  1980.  
  1981. // Beginning of MG105:
  1982. // End of MG105:
  1983.  
  1984. // Beginning of MG106:
  1985. // End of MG106:
  1986.  
  1987. // Beginning of MG107:
  1988. // End of MG107:
  1989.  
  1990. // Beginning of MG108:
  1991. // End of MG108:
  1992.  
  1993. //-------------------------------------------------------------------------------
  1994. // Automatically generate PIEIER1 interrupt masks MG111 to MG118:
  1995. //
  1996.  
  1997. // Beginning of MG111:
  1998. // End of MG111:
  1999.  
  2000. // Beginning of MG112:
  2001. // End of MG112:
  2002.  
  2003. // Beginning of MG113:
  2004. // End of MG113:
  2005.  
  2006. // Beginning of MG114:
  2007. // End of MG114:
  2008.  
  2009. // Beginning of MG115:
  2010. // End of MG115:
  2011.  
  2012. // Beginning of MG116:
  2013. // End of MG116:
  2014.  
  2015. // Beginning of MG117:
  2016. // End of MG117:
  2017.  
  2018. // Beginning of MG118:
  2019. // End of MG118:
  2020.  
  2021. //-------------------------------------------------------------------------------
  2022. // Automatically generate PIEIER1 interrupt masks MG121 to MG128:
  2023. //
  2024.  
  2025. // Beginning of MG121:
  2026. // End of MG121:
  2027.  
  2028. // Beginning of MG121:
  2029. // End of MG122:
  2030.  
  2031. // Beginning of MG123:
  2032. // End of MG123:
  2033.  
  2034. // Beginning of MG124:
  2035. // End of MG124:
  2036.  
  2037. // Beginning of MG125:
  2038. // End of MG125:
  2039.  
  2040. // Beginning of MG126:
  2041. // End of MG126:
  2042.  
  2043. // Beginning of MG127:
  2044. // End of MG127:
  2045.  
  2046. // Beginning of MG128:
  2047. // End of MG128:
  2048.  
  2049.  
  2050. //===========================================================================
  2051. // No more.
  2052. //===========================================================================
  2053. //
  2054. // TMDX ALPHA RELEASE
  2055. // Intended for product evaluation purposes
  2056. //
  2057. //###########################################################################
  2058. //
  2059. // FILE: DSP28_Spi.h
  2060. //
  2061. // TITLE: DSP28 Device SPI Register Definitions.
  2062. //
  2063. //###########################################################################
  2064. //
  2065. // Ver | dd mmm yyyy | Who | Description of changes
  2066. // =====|=============|======|===============================================
  2067. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  2068. // 0.56| 20 May 2002 | L.H. | No change
  2069. // 0.57| 27 May 2002 | L.H. | No change
  2070. // 0.58| 28 Jun 2002 | L.H. | Removed spib register def.
  2071. //###########################################################################
  2072.  
  2073.  
  2074. //---------------------------------------------------------------------------
  2075. // SPI Individual Register Bit Definitions:
  2076. //
  2077. // SPI FIFO Transmit register bit definitions:
  2078. struct SPIFFTX_BITS { // bit description
  2079. Uint16 TXFFIL:5; // 4:0 Interrupt level
  2080. Uint16 TXFFIENA:1; // 5 Interrupt enable
  2081. Uint16 TXFFINTINTCLR:1; // 6 Clear INT flag
  2082. Uint16 TXFFINT:1; // 7 INT flag
  2083. Uint16 TXFFST:5; // 12:8 FIFO status
  2084. Uint16 TXFIFORESET:1; // 14 Enhancement enable
  2085. Uint16 rsvd:1; // 15 reserved
  2086. };
  2087.  
  2088. union SPIFFTX_REG {
  2089. Uint16 all;
  2090. struct SPIFFTX_BITS bit;
  2091. };
  2092.  
  2093. //--------------------------------------------
  2094. // SPI FIFO recieve register bit definitions:
  2095. //
  2096. //
  2097. struct SPIFFRX_BITS { // bits description
  2098. Uint16 RXFFIL:5; // 4:0 Interrupt level
  2099. Uint16 RXFFIENA:1; // 5 Interrupt enable
  2100. Uint16 RXFFINTCLR:1; // 6 Clear INT flag
  2101. Uint16 RXFFINT:1; // 7 INT flag
  2102. Uint16 RXFFST:5; // 12:8 FIFO status
  2103. Uint16 RXFIFORESET:1; // 13 FIFO reset
  2104. Uint16 RXFFOVFCLR:1; // 14 Clear overflow
  2105. Uint16 RXFFOVF:1; // 15 FIFO overflow
  2106.  
  2107. };
  2108.  
  2109. union SPIFFRX_REG {
  2110. Uint16 all;
  2111. struct SPIFFRX_BITS bit;
  2112. };
  2113.  
  2114. //--------------------------------------------
  2115. // SPI FIFO control register bit definitions:
  2116. //
  2117. //
  2118. struct SPIFFCT_BITS { // bits description
  2119. Uint16 TXDLY:8; // 7:0 FIFO transmit delay
  2120. Uint16 rsvd:8; // 15:8 reserved
  2121. };
  2122.  
  2123. union SPIFFCT_REG {
  2124. Uint16 all;
  2125. struct SPIFFCT_BITS bit;
  2126. };
  2127.  
  2128. //---------------------------------------------
  2129. // SPI configuration register bit definitions:
  2130. //
  2131. //
  2132. struct SPICCR_BITS { // bits description
  2133. Uint16 SPICHAR:4; // 3:0 Character length control
  2134. Uint16 SPILBK:1; // 4 Loop-back enable/disable
  2135. Uint16 rsvd1:1; // 5 reserved
  2136. Uint16 CLKPOLARITY:1; // 6 Clock polarity
  2137. Uint16 RESET:1; // 7 SPI SW Reset
  2138. Uint16 rsvd2:8; // 15:8 reserved
  2139. };
  2140.  
  2141. union SPICCR_REG {
  2142. Uint16 all;
  2143. struct SPICCR_BITS bit;
  2144. };
  2145.  
  2146. //-------------------------------------------------
  2147. // SPI operation control register bit definitions:
  2148. //
  2149. //
  2150. struct SPICTL_BITS { // bits description
  2151. Uint16 SPIINTENA:1; // 0 Interrupt enable
  2152. Uint16 TALK:1; // 1 Master/Slave transmit enable
  2153. Uint16 MASTER_SLAVE:1; // 2 Network control mode
  2154. Uint16 CLK_PHASE:1; // 3 Clock phase select
  2155. Uint16 OVERRUN:1; // 4 Overrun interrupt enable
  2156. Uint16 rsvd:11; // 15:5 reserved
  2157. };
  2158.  
  2159. union SPICTL_REG {
  2160. Uint16 all;
  2161. struct SPICTL_BITS bit;
  2162. };
  2163.  
  2164. //--------------------------------------
  2165. // SPI status register bit definitions:
  2166. //
  2167. //
  2168. struct SPISTS_BITS { // bits description
  2169. Uint16 rsvd1:5; // 4:0 reserved
  2170. Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
  2171. Uint16 INT_FLAG:1; // 6 SPI interrupt flag
  2172. Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
  2173. Uint16 rsvd2:8; // 15:8 reserved
  2174. };
  2175.  
  2176. union SPISTS_REG {
  2177. Uint16 all;
  2178. struct SPISTS_BITS bit;
  2179. };
  2180.  
  2181. //------------------------------------------------
  2182. // SPI priority control register bit definitions:
  2183. //
  2184. //
  2185. struct SPIPRI_BITS { // bits description
  2186. Uint16 rsvd1:4; // 3:0 reserved
  2187. Uint16 FREE:1; // 4 Free emulation mode control
  2188. Uint16 SOFT:1; // 5 Soft emulation mode control
  2189. Uint16 PRIORITY:1; // 6 Interrupt priority select
  2190. Uint16 rsvd2:9; // 15:7 reserved
  2191. };
  2192.  
  2193. union SPIPRI_REG {
  2194. Uint16 all;
  2195. struct SPIPRI_BITS bit;
  2196. };
  2197.  
  2198. //---------------------------------------------------------------------------
  2199. // SPI Register File:
  2200. //
  2201. struct SPI_REGS {
  2202. union SPICCR_REG SPICCR; // Configuration register
  2203. union SPICTL_REG SPICTL; // Operation control register
  2204. union SPISTS_REG SPISTS; // Status register
  2205. Uint16 rsvd1; // reserved
  2206. Uint16 SPIBRR; // Baud Rate
  2207. Uint16 rsvd2; // reserved
  2208. Uint16 SPIRXEMU; // Emulation buffer
  2209. Uint16 SPIRXBUF; // Serial input buffer
  2210. Uint16 SPITXBUF; // Serial output buffer
  2211. Uint16 SPIDAT; // Serial data
  2212. union SPIFFTX_REG SPIFFTX; // FIFO transmit register
  2213. union SPIFFRX_REG SPIFFRX; // FIFO recieve register
  2214. union SPIFFCT_REG SPIFFCT; // FIFO control register
  2215. Uint16 rsvd3[2]; // reserved
  2216. union SPIPRI_REG SPIPRI; // FIFO Priority control
  2217. };
  2218.  
  2219. //---------------------------------------------------------------------------
  2220. // SPI External References & Function Declarations:
  2221. //
  2222. extern volatile struct SPI_REGS SpiaRegs;
  2223.  
  2224.  
  2225. //===========================================================================
  2226. // No more.
  2227. //===========================================================================
  2228. //
  2229. // TMDX ALPHA RELEASE
  2230. // Intended for product evaluation purposes
  2231. //
  2232. //###########################################################################
  2233. //
  2234. // FILE: DSP28_Sci.h
  2235. //
  2236. // TITLE: DSP28 Device SCI Register Definitions.
  2237. //
  2238. //###########################################################################
  2239. //
  2240. // Ver | dd mmm yyyy | Who | Description of changes
  2241. // =====|=============|======|===============================================
  2242. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  2243. // 0.56| 20 May 2002 | L.H. | No change
  2244. // 0.57| 27 May 2002 | L.H. | No change
  2245. // 0.58| 29 Jun 2002 | L.H. | No change
  2246. //###########################################################################
  2247.  
  2248.  
  2249. //---------------------------------------------------------------------------
  2250. // SCI Individual Register Bit Definitions
  2251.  
  2252. //----------------------------------------------------------
  2253. // SCICCR communication control register bit definitions:
  2254. //
  2255.  
  2256. struct SCICCR_BITS { // bit description
  2257. Uint16 SCICHAR:3; // 2:0 Character length control
  2258. Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
  2259. Uint16 LOOPBKENA:1; // 4 Loop Back enable
  2260. Uint16 PARITYENA:1; // 5 Parity enable
  2261. Uint16 PARITY:1; // 6 Even or Odd Parity
  2262. Uint16 STOPBITS:1; // 7 Number of Stop Bits
  2263. Uint16 rsvd1:8; // 15:8 reserved
  2264. };
  2265.  
  2266. union SCICCR_REG {
  2267. Uint16 all;
  2268. struct SCICCR_BITS bit;
  2269. };
  2270.  
  2271. //-------------------------------------------
  2272. // SCICTL1 control register 1 bit definitions:
  2273. //
  2274.  
  2275. struct SCICTL1_BITS { // bit description
  2276. Uint16 RXENA:1; // 0 SCI receiver enable
  2277. Uint16 TXENA:1; // 1 SCI transmitter enable
  2278. Uint16 SLEEP:1; // 2 SCI sleep
  2279. Uint16 TXWAKE:1; // 3 Transmitter wakeup method
  2280. Uint16 rsvd:1; // 4 reserved
  2281. Uint16 SWRESET:1; // 5 Software reset
  2282. Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
  2283. Uint16 rsvd1:9; // 15:7 reserved
  2284.  
  2285. };
  2286.  
  2287. union SCICTL1_REG {
  2288. Uint16 all;
  2289. struct SCICTL1_BITS bit;
  2290. };
  2291.  
  2292. //---------------------------------------------
  2293. // SCICTL2 control register 2 bit definitions:
  2294. //
  2295.  
  2296. struct SCICTL2_BITS { // bit description
  2297. Uint16 TXINTENA:1; // 0 Transmit interrupt enable
  2298. Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
  2299. Uint16 rsvd:4; // 5:2 reserved
  2300. Uint16 TXEMPTY:1; // 6 Transmitter empty flag
  2301. Uint16 TXRDY:1; // 7 Transmitter ready flag
  2302. Uint16 rsvd1:8; // 15:8 reserved
  2303.  
  2304. };
  2305.  
  2306. union SCICTL2_REG {
  2307. Uint16 all;
  2308. struct SCICTL2_BITS bit;
  2309. };
  2310.  
  2311. //---------------------------------------------------
  2312. // SCIRXST Receiver status register bit definitions:
  2313. //
  2314.  
  2315. struct SCIRXST_BITS { // bit description
  2316. Uint16 rsvd:1; // 0 reserved
  2317. Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
  2318. Uint16 PE:1; // 2 Parity error flag
  2319. Uint16 OE:1; // 3 Overrun error flag
  2320. Uint16 FE:1; // 4 Framing error flag
  2321. Uint16 BRKDT:1; // 5 Break-detect flag
  2322. Uint16 RXRDY:1; // 6 Receiver ready flag
  2323. Uint16 RXERR:1; // 7 Receiver error flag
  2324.  
  2325. };
  2326.  
  2327. union SCIRXST_REG {
  2328. Uint16 all;
  2329. struct SCIRXST_BITS bit;
  2330. };
  2331.  
  2332. //----------------------------------------------------
  2333. // SCIRXBUF Receiver Data Buffer with FIFO bit definitions:
  2334. //
  2335.  
  2336. struct SCIRXBUF_BITS { // bits description
  2337. Uint16 RXDT:8; // 7:0 Receive word
  2338. Uint16 rsvd:6; // 13:8 reserved
  2339. Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
  2340. Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
  2341. };
  2342.  
  2343. union SCIRXBUF_REG {
  2344. Uint16 all;
  2345. struct SCIRXBUF_BITS bit;
  2346. };
  2347.  
  2348. //--------------------------------------------------
  2349. // SCIPRI Priority control register bit definitions:
  2350. //
  2351. //
  2352.  
  2353. struct SCIPRI_BITS { // bit description
  2354. Uint16 rsvd:3; // 2:0 reserved
  2355. Uint16 FREE:1; // 3 Free emulation suspend mode
  2356. Uint16 SOFT:1; // 4 Soft emulation suspend mode
  2357. Uint16 rsvd1:3; // 7:5 reserved
  2358. };
  2359.  
  2360. union SCIPRI_REG {
  2361. Uint16 all;
  2362. struct SCIPRI_BITS bit;
  2363. };
  2364.  
  2365. //-------------------------------------------------
  2366. // SCI FIFO Transmit register bit definitions:
  2367. //
  2368. //
  2369.  
  2370. struct SCIFFTX_BITS { // bit description
  2371. Uint16 TXFFILIL:5; // 4:0 Interrupt level
  2372. Uint16 TXFFIENA:1; // 5 Interrupt enable
  2373. Uint16 TXINTCLR:1; // 6 Clear INT flag
  2374. Uint16 TXFFINT:1; // 7 INT flag
  2375. Uint16 TXFFST:5; // 12:8 FIFO status
  2376. Uint16 TXFIFOXRESET:1; // 13 FIFO reset
  2377. Uint16 SCIFFENA:1; // 14 Enhancement enable
  2378. Uint16 resvd:1; // 15 reserved
  2379.  
  2380. };
  2381.  
  2382. union SCIFFTX_REG {
  2383. Uint16 all;
  2384. struct SCIFFTX_BITS bit;
  2385. };
  2386.  
  2387. //------------------------------------------------
  2388. // SCI FIFO recieve register bit definitions:
  2389. //
  2390. //
  2391.  
  2392. struct SCIFFRX_BITS { // bits description
  2393. Uint16 RXFFIL:5; // 4:0 Interrupt level
  2394. Uint16 RXFFIENA:1; // 5 Interrupt enable
  2395. Uint16 RXFFINTCLR:1; // 6 Clear INT flag
  2396. Uint16 RXFFINT:1; // 7 INT flag
  2397. Uint16 RXFIFST:5; // 12:8 FIFO status
  2398. Uint16 RXFIFORESET:1; // 13 FIFO reset
  2399. Uint16 RXOVF_CLR:1; // 14 Clear overflow
  2400. Uint16 RXFFOVF:1; // 15 FIFO overflow
  2401.  
  2402. };
  2403.  
  2404. union SCIFFRX_REG {
  2405. Uint16 all;
  2406. struct SCIFFRX_BITS bit;
  2407. };
  2408.  
  2409. // SCI FIFO control register bit definitions:
  2410. struct SCIFFCT_BITS { // bits description
  2411. Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
  2412. Uint16 rsvd:5; // 12:8 reserved
  2413. Uint16 CDC:1; // 13 Auto baud mode enable
  2414. Uint16 ABDCLR:1; // 14 Auto baud clear
  2415. Uint16 ABD:1; // 15 Auto baud detect
  2416. };
  2417.  
  2418. union SCIFFCT_REG {
  2419. Uint16 all;
  2420. struct SCIFFCT_BITS bit;
  2421. };
  2422.  
  2423. //---------------------------------------------------------------------------
  2424. // SCI Register File:
  2425. //
  2426. struct SCI_REGS {
  2427. union SCICCR_REG SCICCR; // Communications control register
  2428. union SCICTL1_REG SCICTL1; // Control register 1
  2429. Uint16 SCIHBAUD; // Baud rate (high) register
  2430. Uint16 SCILBAUD; // Baud rate (low) register
  2431. union SCICTL2_REG SCICTL2; // Control register 2
  2432. union SCIRXST_REG SCIRXST; // Recieve status register
  2433. Uint16 SCIRXEMU; // Recieve emulation buffer register
  2434. union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
  2435. Uint16 rsvd1; // reserved
  2436. Uint16 SCITXBUF; // Transmit data buffer
  2437. union SCIFFTX_REG SCIFFTX; // FIFO transmit register
  2438. union SCIFFRX_REG SCIFFRX; // FIFO recieve register
  2439. union SCIFFCT_REG SCIFFCT; // FIFO control register
  2440. Uint16 rsvd2; // reserved
  2441. Uint16 rsvd3; // reserved
  2442. union SCIPRI_REG SCIPRI; // FIFO Priority control
  2443. };
  2444.  
  2445. //---------------------------------------------------------------------------
  2446. // SCI External References & Function Declarations:
  2447. //
  2448. extern volatile struct SCI_REGS SciaRegs;
  2449. extern volatile struct SCI_REGS ScibRegs;
  2450.  
  2451.  
  2452. //===========================================================================
  2453. // No more.
  2454. //===========================================================================
  2455. //
  2456. // TMDX ALPHA RELEASE
  2457. // Intended for product evaluation purposes
  2458. //
  2459. //###########################################################################
  2460. //
  2461. // FILE: DSP28_Mcbsp.h
  2462. //
  2463. // TITLE: DSP28 Device McBSP Register Definitions.
  2464. //
  2465. //###########################################################################
  2466. //
  2467. // Ver | dd mmm yyyy | Who | Description of changes
  2468. // =====|=============|======|===============================================
  2469. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  2470. // 0.56| 20 May 2002 | L.H. | No change
  2471. // 0.57| 27 May 2002 | L.H. | No change
  2472. // 0.58| 29 Jun 2002 | L.H. | No change
  2473. //###########################################################################
  2474.  
  2475.  
  2476. //---------------------------------------------------------------------------
  2477. // McBSP Individual Register Bit Definitions:
  2478. //
  2479. // McBSP DRR2 register bit definitions:
  2480. struct DRR2_BITS { // bit description
  2481. Uint16 HWLB:8; // 16:23 High word low byte
  2482. Uint16 HWHB:8; // 24:31 High word high byte
  2483. };
  2484.  
  2485. union DRR2_REG {
  2486. Uint16 all;
  2487. struct DRR2_BITS bit;
  2488. };
  2489.  
  2490. // McBSP DRR1 register bit definitions:
  2491. struct DRR1_BITS { // bit description
  2492. Uint16 LWLB:8; // 16:23 Low word low byte
  2493. Uint16 LWHB:8; // 24:31 low word high byte
  2494. };
  2495.  
  2496. union DRR1_REG {
  2497. Uint16 all;
  2498. struct DRR1_BITS bit;
  2499. };
  2500.  
  2501. // McBSP DXR2 register bit definitions:
  2502. struct DXR2_BITS { // bit description
  2503. Uint16 HWLB:8; // 16:23 High word low byte
  2504. Uint16 HWHB:8; // 24:31 High word high byte
  2505. };
  2506.  
  2507. union DXR2_REG {
  2508. Uint16 all;
  2509. struct DXR2_BITS bit;
  2510. };
  2511.  
  2512. // McBSP DXR1 register bit definitions:
  2513. struct DXR1_BITS { // bit description
  2514. Uint16 LWLB:8; // 16:23 Low word low byte
  2515. Uint16 LWHB:8; // 24:31 low word high byte
  2516. };
  2517.  
  2518. union DXR1_REG {
  2519. Uint16 all;
  2520. struct DXR1_BITS bit;
  2521. };
  2522.  
  2523. // SPCR2 control register bit definitions:
  2524. struct SPCR2_BITS { // bit description
  2525. Uint16 XRST:1; // 0 transmit reset
  2526. Uint16 XRDY:1; // 1 transmit ready
  2527. Uint16 XEMPTY:1; // 2 Transmit empty
  2528. Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag
  2529. Uint16 XINTM:2; // 5:4 Transmit interrupt types
  2530. Uint16 GRST:1; // 6 CLKG reset
  2531. Uint16 FRST:1; // 7 Frame sync reset
  2532. Uint16 SOFT:1; // 8 SOFT bit
  2533. Uint16 FREE:1; // 9 FREE bit
  2534. Uint16 rsvd:6; // 15:10 reserved
  2535. };
  2536.  
  2537. union SPCR2_REG {
  2538. Uint16 all;
  2539. struct SPCR2_BITS bit;
  2540. };
  2541.  
  2542. // SPCR1 control register bit definitions:
  2543. struct SPCR1_BITS { // bit description
  2544. Uint16 RRST:1; // 0 Receive reset
  2545. Uint16 RRDY:1; // 1 Receive ready
  2546. Uint16 REMPTY:1; // 2 Receive empty
  2547. Uint16 RSYNCERR:1; // 7 Receive syn errorINT flag
  2548. Uint16 RINTM:2; // 5:4 Receive interrupt types
  2549. Uint16 ABIS:1; // 6 ABIS mode select
  2550. Uint16 DXENA:1; // 7 DX hi-z enable
  2551. Uint16 rsvd:3; // 10:8 reserved
  2552. Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit
  2553. Uint16 RJUST:2; // 13:14 Right justified
  2554. Uint16 DLB:1; // 15 Digital loop back reserved
  2555. };
  2556.  
  2557. union SPCR1_REG {
  2558. Uint16 all;
  2559. struct SPCR1_BITS bit;
  2560. };
  2561.  
  2562. // RCR2 control register bit definitions:
  2563. struct RCR2_BITS { // bit description
  2564. Uint16 RDATDLY:2; // 1:0 Receive data delay
  2565. Uint16 RFIG:1; // 2 Receive frame sync ignore
  2566. Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
  2567. Uint16 RWDLEN2:3; // 7:5 Receive word length
  2568. Uint16 RFRLEN2:7; // 14:8 Receive Frame sync
  2569. Uint16 RPHASE:1; // 15 Receive Phase
  2570. };
  2571.  
  2572. union RCR2_REG {
  2573. Uint16 all;
  2574. struct RCR2_BITS bit;
  2575. };
  2576.  
  2577. // RCR1 control register bit definitions:
  2578. struct RCR1_BITS { // bit description
  2579. Uint16 rsvd1:5; // 4:0 reserved
  2580. Uint16 RWDLEN1:3; // 7:5 Receive word length
  2581. Uint16 RFRLEN1:7; // 14:8 Receive Frame sync
  2582. Uint16 rsvd2:1; // 15 reserved
  2583. };
  2584.  
  2585. union RCR1_REG {
  2586. Uint16 all;
  2587. struct RCR1_BITS bit;
  2588. };
  2589.  
  2590. // XCR2 control register bit definitions:
  2591.  
  2592. struct XCR2_BITS { // bit description
  2593. Uint16 XDATDLY:2; // 1:0 Transmit data delay
  2594. Uint16 XFIG:1; // 2 Transmit frame sync ignore
  2595. Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
  2596. Uint16 XWDLEN2:3; // 7:5 Transmit word length
  2597. Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync
  2598. Uint16 XPHASE:1; // 15 Transmit Phase
  2599. };
  2600.  
  2601. union XCR2_REG {
  2602. Uint16 all;
  2603. struct XCR2_BITS bit;
  2604. };
  2605.  
  2606. // XCR1 control register bit definitions:
  2607. struct XCR1_BITS { // bit description
  2608. Uint16 rsvd1:5; // 4:0 reserved
  2609. Uint16 XWDLEN1:3; // 7:5 Transmit word length
  2610. Uint16 XFRLEN1:7; // 14:8 Transmit Frame sync
  2611. Uint16 rsvd2:1; // 15 reserved
  2612. };
  2613.  
  2614. union XCR1_REG {
  2615. Uint16 all;
  2616. struct XCR1_BITS bit;
  2617. };
  2618.  
  2619. // SRGR2 Sample rate generator control register bit definitions:
  2620. struct SRGR2_BITS { // bit description
  2621. Uint16 FPER:12; // 11:0 Frame period
  2622. Uint16 FSGM:1; // 12 Frame sync generator mode
  2623. Uint16 CLKSM:1; // 13 Sample rate generator mode
  2624. Uint16 CLKSP:1; // 14 Reserved in this McBSP
  2625. Uint16 GYSNC:1; // 15 CLKG sync
  2626. };
  2627.  
  2628. union SRGR2_REG {
  2629. Uint16 all;
  2630. struct SRGR2_BITS bit;
  2631. };
  2632.  
  2633. // SRGR1 control register bit definitions:
  2634. struct SRGR1_BITS { // bit description
  2635. Uint16 CLKGDV:8; // 7:0 CLKG divider
  2636. Uint16 FWID:8; // 15:8 Frame width
  2637. };
  2638.  
  2639. union SRGR1_REG {
  2640. Uint16 all;
  2641. struct SRGR1_BITS bit;
  2642. };
  2643.  
  2644. // MCR2 Multichannel control register bit definitions:
  2645. struct MCR2_BITS { // bit description
  2646. Uint16 XMCM:2; // 1:0 Transmit multichannel mode
  2647. Uint16 XCBLK:3; // 2:4 Transmit current block
  2648. Uint16 XPABLK:2; // 5:6 Transmit partition A Block
  2649. Uint16 XPBBLK:2; // 7:8 Transmit partition B Block
  2650. Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode
  2651. Uint16 rsvd:6; // 15:10 reserved
  2652. };
  2653.  
  2654. union MCR2_REG {
  2655. Uint16 all;
  2656. struct MCR2_BITS bit;
  2657. };
  2658.  
  2659. // MCR1 Multichannel control register bit definitions:
  2660. struct MCR1_BITS { // bit description
  2661. Uint16 RMCM:1; // 0 Receive multichannel mode
  2662. Uint16 rsvd:1; // 1 reserved
  2663. Uint16 RCBLK:3; // 4:2 Receive current block
  2664. Uint16 RPABLK:2; // 6:5 Receive partition A Block
  2665. Uint16 RPBBLK:2; // 7:8 Receive partition B Block
  2666. Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
  2667. Uint16 rsvd1:6; // 15:10 reserved
  2668. };
  2669.  
  2670. union MCR1_REG {
  2671. Uint16 all;
  2672. struct MCR1_BITS bit;
  2673. };
  2674.  
  2675. // RCERA control register bit definitions:
  2676. struct RCERA_BITS { // bit description
  2677. Uint16 RCEA0:1; // 0 Receive Channel enable bit
  2678. Uint16 RCEA1:1; // 1 Receive Channel enable bit
  2679. Uint16 RCEA2:1; // 2 Receive Channel enable bit
  2680. Uint16 RCEA3:1; // 3 Receive Channel enable bit
  2681. Uint16 RCEA4:1; // 4 Receive Channel enable bit
  2682. Uint16 RCEA5:1; // 5 Receive Channel enable bit
  2683. Uint16 RCEA6:1; // 6 Receive Channel enable bit
  2684. Uint16 RCEA7:1; // 7 Receive Channel enable bit
  2685. Uint16 RCEA8:1; // 8 Receive Channel enable bit
  2686. Uint16 RCEA9:1; // 9 Receive Channel enable bit
  2687. Uint16 RCEA10:1; // 10 Receive Channel enable bit
  2688. Uint16 RCEA11:1; // 11 Receive Channel enable bit
  2689. Uint16 RCEA12:1; // 12 Receive Channel enable bit
  2690. Uint16 RCEA13:1; // 13 Receive Channel enable bit
  2691. Uint16 RCEA14:1; // 14 Receive Channel enable bit
  2692. Uint16 RCEA15:1; // 15 Receive Channel enable bit
  2693. };
  2694.  
  2695. union RCERA_REG {
  2696. Uint16 all;
  2697. struct RCERA_BITS bit;
  2698. };
  2699.  
  2700. // RCERB control register bit definitions:
  2701. struct RCERB_BITS { // bit description
  2702. Uint16 RCEB0:1; // 0 Receive Channel enable bit
  2703. Uint16 RCEB1:1; // 1 Receive Channel enable bit
  2704. Uint16 RCEB2:1; // 2 Receive Channel enable bit
  2705. Uint16 RCEB3:1; // 3 Receive Channel enable bit
  2706. Uint16 RCEB4:1; // 4 Receive Channel enable bit
  2707. Uint16 RCEB5:1; // 5 Receive Channel enable bit
  2708. Uint16 RCEB6:1; // 6 Receive Channel enable bit
  2709. Uint16 RCEB7:1; // 7 Receive Channel enable bit
  2710. Uint16 RCEB8:1; // 8 Receive Channel enable bit
  2711. Uint16 RCEB9:1; // 9 Receive Channel enable bit
  2712. Uint16 RCEB10:1; // 10 Receive Channel enable bit
  2713. Uint16 RCEB11:1; // 11 Receive Channel enable bit
  2714. Uint16 RCEB12:1; // 12 Receive Channel enable bit
  2715. Uint16 RCEB13:1; // 13 Receive Channel enable bit
  2716. Uint16 RCEB14:1; // 14 Receive Channel enable bit
  2717. Uint16 RCEB15:1; // 15 Receive Channel enable bit
  2718. };
  2719.  
  2720. union RCERB_REG {
  2721. Uint16 all;
  2722. struct RCERB_BITS bit;
  2723. };
  2724.  
  2725. // XCERA control register bit definitions:
  2726. struct XCERA_BITS { // bit description
  2727. Uint16 XCEA0:1; // 0 Receive Channel enable bit
  2728. Uint16 XCEA1:1; // 1 Receive Channel enable bit
  2729. Uint16 XCEA2:1; // 2 Receive Channel enable bit
  2730. Uint16 XCEA3:1; // 3 Receive Channel enable bit
  2731. Uint16 XCEA4:1; // 4 Receive Channel enable bit
  2732. Uint16 XCEA5:1; // 5 Receive Channel enable bit
  2733. Uint16 XCEA6:1; // 6 Receive Channel enable bit
  2734. Uint16 XCEA7:1; // 7 Receive Channel enable bit
  2735. Uint16 XCEA8:1; // 8 Receive Channel enable bit
  2736. Uint16 XCEA9:1; // 9 Receive Channel enable bit
  2737. Uint16 XCEA10:1; // 10 Receive Channel enable bit
  2738. Uint16 XCEA11:1; // 11 Receive Channel enable bit
  2739. Uint16 XCEA12:1; // 12 Receive Channel enable bit
  2740. Uint16 XCEA13:1; // 13 Receive Channel enable bit
  2741. Uint16 XCEA14:1; // 14 Receive Channel enable bit
  2742. Uint16 XCEA15:1; // 15 Receive Channel enable bit
  2743. };
  2744.  
  2745. union XCERA_REG {
  2746. Uint16 all;
  2747. struct XCERA_BITS bit;
  2748. };
  2749.  
  2750. // XCERB control register bit definitions:
  2751. struct XCERB_BITS { // bit description
  2752. Uint16 XCEB0:1; // 0 Receive Channel enable bit
  2753. Uint16 XCEB1:1; // 1 Receive Channel enable bit
  2754. Uint16 XCEB2:1; // 2 Receive Channel enable bit
  2755. Uint16 XCEB3:1; // 3 Receive Channel enable bit
  2756. Uint16 XCEB4:1; // 4 Receive Channel enable bit
  2757. Uint16 XCEB5:1; // 5 Receive Channel enable bit
  2758. Uint16 XCEB6:1; // 6 Receive Channel enable bit
  2759. Uint16 XCEB7:1; // 7 Receive Channel enable bit
  2760. Uint16 XCEB8:1; // 8 Receive Channel enable bit
  2761. Uint16 XCEB9:1; // 9 Receive Channel enable bit
  2762. Uint16 XCEB10:1; // 10 Receive Channel enable bit
  2763. Uint16 XCEB11:1; // 11 Receive Channel enable bit
  2764. Uint16 XCEB12:1; // 12 Receive Channel enable bit
  2765. Uint16 XCEB13:1; // 13 Receive Channel enable bit
  2766. Uint16 XCEB14:1; // 14 Receive Channel enable bit
  2767. Uint16 XCEB15:1; // 15 Receive Channel enable bit
  2768. };
  2769.  
  2770. union XCERB_REG {
  2771. Uint16 all;
  2772. struct XCERB_BITS bit;
  2773. };
  2774.  
  2775. // PCR1 control register bit definitions:
  2776. struct PCR1_BITS { // bit description
  2777. Uint16 CLKRP:1; // 0 Receive Clock polarity
  2778. Uint16 CLKXP:1; // 1 Transmit clock polarity
  2779. Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
  2780. Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
  2781. Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
  2782. Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
  2783. Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
  2784. Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
  2785. Uint16 CLKRM:1; // 8 Receiver Clock Mode
  2786. Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
  2787. Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
  2788. Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
  2789. Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in this 28x-McBSP
  2790. Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in this 28x-McBSP
  2791. Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
  2792. Uint16 rsvd:1 ; // 15 reserved
  2793. };
  2794.  
  2795. union PCR1_REG {
  2796. Uint16 all;
  2797. struct PCR1_BITS bit;
  2798. };
  2799.  
  2800. // RCERC control register bit definitions:
  2801. struct RCERC_BITS { // bit description
  2802. Uint16 RCEC0:1; // 0 Receive Channel enable bit
  2803. Uint16 RCEC1:1; // 1 Receive Channel enable bit
  2804. Uint16 RCEC2:1; // 2 Receive Channel enable bit
  2805. Uint16 RCEC3:1; // 3 Receive Channel enable bit
  2806. Uint16 RCEC4:1; // 4 Receive Channel enable bit
  2807. Uint16 RCEC5:1; // 5 Receive Channel enable bit
  2808. Uint16 RCEC6:1; // 6 Receive Channel enable bit
  2809. Uint16 RCEC7:1; // 7 Receive Channel enable bit
  2810. Uint16 RCEC8:1; // 8 Receive Channel enable bit
  2811. Uint16 RCEC9:1; // 9 Receive Channel enable bit
  2812. Uint16 RCEC10:1; // 10 Receive Channel enable bit
  2813. Uint16 RCEC11:1; // 11 Receive Channel enable bit
  2814. Uint16 RCEC12:1; // 12 Receive Channel enable bit
  2815. Uint16 RCEC13:1; // 13 Receive Channel enable bit
  2816. Uint16 RCEC14:1; // 14 Receive Channel enable bit
  2817. Uint16 RCEC15:1; // 15 Receive Channel enable bit
  2818. };
  2819.  
  2820. union RCERC_REG {
  2821. Uint16 all;
  2822. struct RCERC_BITS bit;
  2823. };
  2824.  
  2825. // RCERD control register bit definitions:
  2826. struct RCERD_BITS { // bit description
  2827. Uint16 RCED0:1; // 0 Receive Channel enable bit
  2828. Uint16 RCED1:1; // 1 Receive Channel enable bit
  2829. Uint16 RCED2:1; // 2 Receive Channel enable bit
  2830. Uint16 RCED3:1; // 3 Receive Channel enable bit
  2831. Uint16 RCED4:1; // 4 Receive Channel enable bit
  2832. Uint16 RCED5:1; // 5 Receive Channel enable bit
  2833. Uint16 RCED6:1; // 6 Receive Channel enable bit
  2834. Uint16 RCED7:1; // 7 Receive Channel enable bit
  2835. Uint16 RCED8:1; // 8 Receive Channel enable bit
  2836. Uint16 RCED9:1; // 9 Receive Channel enable bit
  2837. Uint16 RCED10:1; // 10 Receive Channel enable bit
  2838. Uint16 RCED11:1; // 11 Receive Channel enable bit
  2839. Uint16 RCED12:1; // 12 Receive Channel enable bit
  2840. Uint16 RCED13:1; // 13 Receive Channel enable bit
  2841. Uint16 RCED14:1; // 14 Receive Channel enable bit
  2842. Uint16 RCED15:1; // 15 Receive Channel enable bit
  2843. };
  2844.  
  2845. union RCERD_REG {
  2846. Uint16 all;
  2847. struct RCERD_BITS bit;
  2848. };
  2849.  
  2850. // XCERC control register bit definitions:
  2851. struct XCERC_BITS { // bit description
  2852. Uint16 XCEC0:1; // 0 Receive Channel enable bit
  2853. Uint16 XCEC1:1; // 1 Receive Channel enable bit
  2854. Uint16 XCEC2:1; // 2 Receive Channel enable bit
  2855. Uint16 XCEC3:1; // 3 Receive Channel enable bit
  2856. Uint16 XCEC4:1; // 4 Receive Channel enable bit
  2857. Uint16 XCEC5:1; // 5 Receive Channel enable bit
  2858. Uint16 XCEC6:1; // 6 Receive Channel enable bit
  2859. Uint16 XCEC7:1; // 7 Receive Channel enable bit
  2860. Uint16 XCEC8:1; // 8 Receive Channel enable bit
  2861. Uint16 XCEC9:1; // 9 Receive Channel enable bit
  2862. Uint16 XCEC10:1; // 10 Receive Channel enable bit
  2863. Uint16 XCEC11:1; // 11 Receive Channel enable bit
  2864. Uint16 XCEC12:1; // 12 Receive Channel enable bit
  2865. Uint16 XCEC13:1; // 13 Receive Channel enable bit
  2866. Uint16 XCEC14:1; // 14 Receive Channel enable bit
  2867. Uint16 XCEC15:1; // 15 Receive Channel enable bit
  2868. };
  2869.  
  2870. union XCERC_REG {
  2871. Uint16 all;
  2872. struct XCERC_BITS bit;
  2873. };
  2874.  
  2875. // XCERD control register bit definitions:
  2876. struct XCERD_BITS { // bit description
  2877. Uint16 XCED0:1; // 0 Receive Channel enable bit
  2878. Uint16 XCED1:1; // 1 Receive Channel enable bit
  2879. Uint16 XCED2:1; // 2 Receive Channel enable bit
  2880. Uint16 XCED3:1; // 3 Receive Channel enable bit
  2881. Uint16 XCED4:1; // 4 Receive Channel enable bit
  2882. Uint16 XCED5:1; // 5 Receive Channel enable bit
  2883. Uint16 XCED6:1; // 6 Receive Channel enable bit
  2884. Uint16 XCED7:1; // 7 Receive Channel enable bit
  2885. Uint16 XCED8:1; // 8 Receive Channel enable bit
  2886. Uint16 XCED9:1; // 9 Receive Channel enable bit
  2887. Uint16 XCED10:1; // 10 Receive Channel enable bit
  2888. Uint16 XCED11:1; // 11 Receive Channel enable bit
  2889. Uint16 XCED12:1; // 12 Receive Channel enable bit
  2890. Uint16 XCED13:1; // 13 Receive Channel enable bit
  2891. Uint16 XCED14:1; // 14 Receive Channel enable bit
  2892. Uint16 XCED15:1; // 15 Receive Channel enable bit
  2893. };
  2894.  
  2895. union XCERD_REG {
  2896. Uint16 all;
  2897. struct XCERD_BITS bit;
  2898. };
  2899.  
  2900. // RCERE control register bit definitions:
  2901. struct RCERE_BITS { // bit description
  2902. Uint16 RCEE0:1; // 0 Receive Channel enable bit
  2903. Uint16 RCEE1:1; // 1 Receive Channel enable bit
  2904. Uint16 RCEE2:1; // 2 Receive Channel enable bit
  2905. Uint16 RCEE3:1; // 3 Receive Channel enable bit
  2906. Uint16 RCEE4:1; // 4 Receive Channel enable bit
  2907. Uint16 RCEE5:1; // 5 Receive Channel enable bit
  2908. Uint16 RCEE6:1; // 6 Receive Channel enable bit
  2909. Uint16 RCEE7:1; // 7 Receive Channel enable bit
  2910. Uint16 RCEE8:1; // 8 Receive Channel enable bit
  2911. Uint16 RCEE9:1; // 9 Receive Channel enable bit
  2912. Uint16 RCEE10:1; // 10 Receive Channel enable bit
  2913. Uint16 RCEE11:1; // 11 Receive Channel enable bit
  2914. Uint16 RCEE12:1; // 12 Receive Channel enable bit
  2915. Uint16 RCEE13:1; // 13 Receive Channel enable bit
  2916. Uint16 RCEE14:1; // 14 Receive Channel enable bit
  2917. Uint16 RCEE15:1; // 15 Receive Channel enable bit
  2918. };
  2919.  
  2920. union RCERE_REG {
  2921. Uint16 all;
  2922. struct RCERE_BITS bit;
  2923. };
  2924.  
  2925. // RCERF control register bit definitions:
  2926. struct RCERF_BITS { // bit description
  2927. Uint16 RCEF0:1; // 0 Receive Channel enable bit
  2928. Uint16 RCEF1:1; // 1 Receive Channel enable bit
  2929. Uint16 RCEF2:1; // 2 Receive Channel enable bit
  2930. Uint16 RCEF3:1; // 3 Receive Channel enable bit
  2931. Uint16 RCEF4:1; // 4 Receive Channel enable bit
  2932. Uint16 RCEF5:1; // 5 Receive Channel enable bit
  2933. Uint16 RCEF6:1; // 6 Receive Channel enable bit
  2934. Uint16 RCEF7:1; // 7 Receive Channel enable bit
  2935. Uint16 RCEF8:1; // 8 Receive Channel enable bit
  2936. Uint16 RCEF9:1; // 9 Receive Channel enable bit
  2937. Uint16 RCEF10:1; // 10 Receive Channel enable bit
  2938. Uint16 RCEF11:1; // 11 Receive Channel enable bit
  2939. Uint16 RCEF12:1; // 12 Receive Channel enable bit
  2940. Uint16 RCEF13:1; // 13 Receive Channel enable bit
  2941. Uint16 RCEF14:1; // 14 Receive Channel enable bit
  2942. Uint16 RCEF15:1; // 15 Receive Channel enable bit
  2943. };
  2944.  
  2945. union RCERF_REG {
  2946. Uint16 all;
  2947. struct RCERF_BITS bit;
  2948. };
  2949.  
  2950. // XCERE control register bit definitions:
  2951. struct XCERE_BITS { // bit description
  2952. Uint16 XCEE0:1; // 0 Receive Channel enable bit
  2953. Uint16 XCEE1:1; // 1 Receive Channel enable bit
  2954. Uint16 XCEE2:1; // 2 Receive Channel enable bit
  2955. Uint16 XCEE3:1; // 3 Receive Channel enable bit
  2956. Uint16 XCEE4:1; // 4 Receive Channel enable bit
  2957. Uint16 XCEE5:1; // 5 Receive Channel enable bit
  2958. Uint16 XCEE6:1; // 6 Receive Channel enable bit
  2959. Uint16 XCEE7:1; // 7 Receive Channel enable bit
  2960. Uint16 XCEE8:1; // 8 Receive Channel enable bit
  2961. Uint16 XCEE9:1; // 9 Receive Channel enable bit
  2962. Uint16 XCEE10:1; // 10 Receive Channel enable bit
  2963. Uint16 XCEE11:1; // 11 Receive Channel enable bit
  2964. Uint16 XCEE12:1; // 12 Receive Channel enable bit
  2965. Uint16 XCEE13:1; // 13 Receive Channel enable bit
  2966. Uint16 XCEE14:1; // 14 Receive Channel enable bit
  2967. Uint16 XCEE15:1; // 15 Receive Channel enable bit
  2968. };
  2969.  
  2970. union XCERE_REG {
  2971. Uint16 all;
  2972. struct XCERE_BITS bit;
  2973. };
  2974.  
  2975. // XCERF control register bit definitions:
  2976. struct XCERF_BITS { // bit description
  2977. Uint16 XCEF0:1; // 0 Receive Channel enable bit
  2978. Uint16 XCEF1:1; // 1 Receive Channel enable bit
  2979. Uint16 XCEF2:1; // 2 Receive Channel enable bit
  2980. Uint16 XCEF3:1; // 3 Receive Channel enable bit
  2981. Uint16 XCEF4:1; // 4 Receive Channel enable bit
  2982. Uint16 XCEF5:1; // 5 Receive Channel enable bit
  2983. Uint16 XCEF6:1; // 6 Receive Channel enable bit
  2984. Uint16 XCEF7:1; // 7 Receive Channel enable bit
  2985. Uint16 XCEF8:1; // 8 Receive Channel enable bit
  2986. Uint16 XCEF9:1; // 9 Receive Channel enable bit
  2987. Uint16 XCEF10:1; // 10 Receive Channel enable bit
  2988. Uint16 XCEF11:1; // 11 Receive Channel enable bit
  2989. Uint16 XCEF12:1; // 12 Receive Channel enable bit
  2990. Uint16 XCEF13:1; // 13 Receive Channel enable bit
  2991. Uint16 XCEF14:1; // 14 Receive Channel enable bit
  2992. Uint16 XCEF15:1; // 15 Receive Channel enable bit
  2993. };
  2994.  
  2995. union XCERF_REG {
  2996. Uint16 all;
  2997. struct XCERF_BITS bit;
  2998. };
  2999.  
  3000. // RCERG control register bit definitions:
  3001. struct RCERG_BITS { // bit description
  3002. Uint16 RCEG0:1; // 0 Receive Channel enable bit
  3003. Uint16 RCEG1:1; // 1 Receive Channel enable bit
  3004. Uint16 RCEG2:1; // 2 Receive Channel enable bit
  3005. Uint16 RCEG3:1; // 3 Receive Channel enable bit
  3006. Uint16 RCEG4:1; // 4 Receive Channel enable bit
  3007. Uint16 RCEG5:1; // 5 Receive Channel enable bit
  3008. Uint16 RCEG6:1; // 6 Receive Channel enable bit
  3009. Uint16 RCEG7:1; // 7 Receive Channel enable bit
  3010. Uint16 RCEG8:1; // 8 Receive Channel enable bit
  3011. Uint16 RCEG9:1; // 9 Receive Channel enable bit
  3012. Uint16 RCEG10:1; // 10 Receive Channel enable bit
  3013. Uint16 RCEG11:1; // 11 Receive Channel enable bit
  3014. Uint16 RCEG12:1; // 12 Receive Channel enable bit
  3015. Uint16 RCEG13:1; // 13 Receive Channel enable bit
  3016. Uint16 RCEG14:1; // 14 Receive Channel enable bit
  3017. Uint16 RCEG15:1; // 15 Receive Channel enable bit
  3018. };
  3019.  
  3020. union RCERG_REG {
  3021. Uint16 all;
  3022. struct RCERG_BITS bit;
  3023. };
  3024.  
  3025. // RCERH control register bit definitions:
  3026. struct RCERH_BITS { // bit description
  3027. Uint16 RCEH0:1; // 0 Receive Channel enable bit
  3028. Uint16 RCEH1:1; // 1 Receive Channel enable bit
  3029. Uint16 RCEH2:1; // 2 Receive Channel enable bit
  3030. Uint16 RCEH3:1; // 3 Receive Channel enable bit
  3031. Uint16 RCEH4:1; // 4 Receive Channel enable bit
  3032. Uint16 RCEH5:1; // 5 Receive Channel enable bit
  3033. Uint16 RCEH6:1; // 6 Receive Channel enable bit
  3034. Uint16 RCEH7:1; // 7 Receive Channel enable bit
  3035. Uint16 RCEH8:1; // 8 Receive Channel enable bit
  3036. Uint16 RCEH9:1; // 9 Receive Channel enable bit
  3037. Uint16 RCEH10:1; // 10 Receive Channel enable bit
  3038. Uint16 RCEH11:1; // 11 Receive Channel enable bit
  3039. Uint16 RCEH12:1; // 12 Receive Channel enable bit
  3040. Uint16 RCEH13:1; // 13 Receive Channel enable bit
  3041. Uint16 RCEH14:1; // 14 Receive Channel enable bit
  3042. Uint16 RCEH15:1; // 15 Receive Channel enable bit
  3043. };
  3044.  
  3045. union RCERH_REG {
  3046. Uint16 all;
  3047. struct RCERH_BITS bit;
  3048. };
  3049.  
  3050. // XCERG control register bit definitions:
  3051. struct XCERG_BITS { // bit description
  3052. Uint16 XCEG0:1; // 0 Receive Channel enable bit
  3053. Uint16 XCEG1:1; // 1 Receive Channel enable bit
  3054. Uint16 XCEG2:1; // 2 Receive Channel enable bit
  3055. Uint16 XCEG3:1; // 3 Receive Channel enable bit
  3056. Uint16 XCEG4:1; // 4 Receive Channel enable bit
  3057. Uint16 XCEG5:1; // 5 Receive Channel enable bit
  3058. Uint16 XCEG6:1; // 6 Receive Channel enable bit
  3059. Uint16 XCEG7:1; // 7 Receive Channel enable bit
  3060. Uint16 XCEG8:1; // 8 Receive Channel enable bit
  3061. Uint16 XCEG9:1; // 9 Receive Channel enable bit
  3062. Uint16 XCEG10:1; // 10 Receive Channel enable bit
  3063. Uint16 XCEG11:1; // 11 Receive Channel enable bit
  3064. Uint16 XCEG12:1; // 12 Receive Channel enable bit
  3065. Uint16 XCEG13:1; // 13 Receive Channel enable bit
  3066. Uint16 XCEG14:1; // 14 Receive Channel enable bit
  3067. Uint16 XCEG15:1; // 15 Receive Channel enable bit
  3068. };
  3069.  
  3070. union XCERG_REG {
  3071. Uint16 all;
  3072. struct XCERG_BITS bit;
  3073. };
  3074.  
  3075. // XCERH control register bit definitions:
  3076. struct XCERH_BITS { // bit description
  3077. Uint16 XCEH0:1; // 0 Receive Channel enable bit
  3078. Uint16 XCEH1:1; // 1 Receive Channel enable bit
  3079. Uint16 XCEH2:1; // 2 Receive Channel enable bit
  3080. Uint16 XCEH3:1; // 3 Receive Channel enable bit
  3081. Uint16 XCEH4:1; // 4 Receive Channel enable bit
  3082. Uint16 XCEH5:1; // 5 Receive Channel enable bit
  3083. Uint16 XCEH6:1; // 6 Receive Channel enable bit
  3084. Uint16 XCEH7:1; // 7 Receive Channel enable bit
  3085. Uint16 XCEH8:1; // 8 Receive Channel enable bit
  3086. Uint16 XCEH9:1; // 9 Receive Channel enable bit
  3087. Uint16 XCEH10:1; // 10 Receive Channel enable bit
  3088. Uint16 XCEH11:1; // 11 Receive Channel enable bit
  3089. Uint16 XCEH12:1; // 12 Receive Channel enable bit
  3090. Uint16 XCEH13:1; // 13 Receive Channel enable bit
  3091. Uint16 XCEH14:1; // 14 Receive Channel enable bit
  3092. Uint16 XCEH15:1; // 15 Receive Channel enable bit
  3093. };
  3094.  
  3095. union XCERH_REG {
  3096. Uint16 all;
  3097. struct XCERH_BITS bit;
  3098. };
  3099.  
  3100. // McBSP FIFO Transmit register bit definitions:
  3101. struct MFFTX_BITS { // bit description
  3102. Uint16 IL:5; // 4:0 Interrupt level
  3103. Uint16 TXFFIENA:1; // 5 Interrupt enable
  3104. Uint16 INT_CLR:1; // 6 Clear INT flag
  3105. Uint16 INT:1; // 7 INT flag
  3106. Uint16 ST:5; // 12:8 FIFO status
  3107. Uint16 XRESET:1; // 13 FIFO reset
  3108. Uint16 MFFENA:1; // 14 Enhancement enable
  3109. Uint16 rsvd:1; // 15 reserved
  3110. };
  3111.  
  3112. union MFFTX_REG {
  3113. Uint16 all;
  3114. struct MFFTX_BITS bit;
  3115. };
  3116.  
  3117. // McBSP FIFO recieve register bit definitions:
  3118. struct MFFRX_BITS { // bits description
  3119. Uint16 IL:5; // 4:0 Interrupt level
  3120. Uint16 RXFFIENA:1; // 5 Interrupt enable
  3121. Uint16 INT_CLR:1; // 6 Clear INT flag
  3122. Uint16 INT:1; // 7 INT flag
  3123. Uint16 ST:5; // 12:8 FIFO status
  3124. Uint16 RRESET:1; // 13 FIFO reset
  3125. Uint16 OVF_CLR:1; // 14 Clear overflow
  3126. Uint16 OVF:1; // 15 FIFO overflow
  3127. };
  3128.  
  3129. union MFFRX_REG {
  3130. Uint16 all;
  3131. struct MFFRX_BITS bit;
  3132. };
  3133.  
  3134. // McBSP FIFO control register bit definitions:
  3135. struct MFFCT_BITS { // bits description
  3136. Uint16 TXDLY:8; // 7:0 FIFO transmit delay
  3137. Uint16 rsvd:7; // 15:7 reserved
  3138. Uint16 IACKM:1; // 15 is IACK mode enable bit
  3139. };
  3140.  
  3141. union MFFCT_REG {
  3142. Uint16 all;
  3143. struct MFFCT_BITS bit;
  3144. };
  3145.  
  3146. // McBSP FIFO INTERRUPT control register bit definitions:
  3147. struct MFFINT_BITS { // bits description
  3148. Uint16 XINT:1; // 0 XINT interrupt enable
  3149. Uint16 XEVTA:1; // 1 XEVTA interrupt enable
  3150. Uint16 RINT:1; // 2 RINT interrupt enable
  3151. Uint16 REVTA:1; // 3 REVTA interrupt enable
  3152. Uint16 rsvd:12; // 15:4 reserved
  3153. };
  3154.  
  3155. union MFFINT_REG {
  3156. Uint16 all;
  3157. struct MFFINT_BITS bit;
  3158. };
  3159.  
  3160. // McBSP FIFO INTERRUPT status register bit definitions:
  3161. struct MFFST_BITS { // bits description
  3162. Uint16 EOBX:1; // 0 EOBX flag
  3163. Uint16 FSX:1; // 1 FSX flag
  3164. Uint16 EOBR:1; // 2 EOBR flag
  3165. Uint16 FSR:1; // 3 FSR flag
  3166. Uint16 rsvd:12; // 15:4 reserved
  3167. };
  3168.  
  3169. union MFFST_REG {
  3170. Uint16 all;
  3171. struct MFFST_BITS bit;
  3172. };
  3173.  
  3174.  
  3175. //---------------------------------------------------------------------------
  3176. // McBSP Register File:
  3177. //
  3178. struct MCBSP_REGS {
  3179. union DRR2_REG DRR2; // 0, MCBSP Data receive register bits 31-16
  3180. union DRR1_REG DRR1; // 1, MCBSP Data receive register bits 15-0
  3181. union DXR2_REG DXR2; // 2, MCBSP Data transmit register bits 31-16
  3182. union DXR1_REG DXR1; // 3, MCBSP Data transmit register bits 15-0
  3183. union SPCR2_REG SPCR2; // 4, MCBSP control register bits 31-16
  3184. union SPCR1_REG SPCR1; // 5, MCBSP control register bits 15-0
  3185. union RCR2_REG RCR2; // 6, MCBSP receive control register bits 31-16
  3186. union RCR1_REG RCR1; // 7, MCBSP receive control register bits 15-0
  3187. union XCR2_REG XCR2; // 8, MCBSP transmit control register bits 31-16
  3188. union XCR1_REG XCR1; // 9, MCBSP transmit control register bits 15-0
  3189. union SRGR2_REG SRGR2; // 10, MCBSP sample rate gen register bits 31-16
  3190. union SRGR1_REG SRGR1; // 11, MCBSP sample rate gen register bits 15-0
  3191. union MCR2_REG MCR2; // 12, MCBSP multichannel register bits 31-16
  3192. union MCR1_REG MCR1; // 13, MCBSP multichannel register bits 15-0
  3193. union RCERA_REG RCERA; // 14, MCBSP Receive channel enable partition A
  3194. union RCERB_REG RCERB; // 15, MCBSP Receive channel enable partition B
  3195. union XCERA_REG XCERA; // 16, MCBSP Transmit channel enable partition A
  3196. union XCERB_REG XCERB; // 17, MCBSP Transmit channel enable partition B
  3197. union PCR1_REG PCR1; // 18, MCBSP Pin control register bits 15-0
  3198. union RCERC_REG RCERC; // 19, MCBSP Receive channel enable partition C
  3199. union RCERD_REG RCERD; // 20, MCBSP Receive channel enable partition D
  3200. union XCERC_REG XCERC; // 21, MCBSP Transmit channel enable partition C
  3201. union XCERD_REG XCERD; // 23, MCBSP Transmit channel enable partition D
  3202. union RCERE_REG RCERE; // 24, MCBSP Receive channel enable partition E
  3203. union RCERF_REG RCERF; // 25, MCBSP Receive channel enable partition F
  3204. union XCERE_REG XCERE; // 26, MCBSP Transmit channel enable partition E
  3205. union XCERF_REG XCERF; // 27, MCBSP Transmit channel enable partition F
  3206. union RCERG_REG RCERG; // 28, MCBSP Receive channel enable partition G
  3207. union RCERH_REG RCERH; // 29, MCBSP Receive channel enable partition H
  3208. union XCERG_REG XCERG; // 30, MCBSP Transmit channel enable partition G
  3209. union XCERH_REG XCERH; // 31, MCBSP Transmit channel enable partition H
  3210. Uint16 rsvd1; // 32, reserved
  3211. union MFFTX_REG MFFTX; // 33, MCBSP Transmit FIFO register bits
  3212. union MFFRX_REG MFFRX; // 34, MCBSP Receive FIFO register bits
  3213. union MFFCT_REG MFFCT; // 35, MCBSP FIFO control register bits
  3214. union MFFINT_REG MFFINT; // 36, MCBSP Interrupt register bits
  3215. union MFFST_REG MFFST; // 37, MCBSP Status register bits
  3216. };
  3217.  
  3218. //---------------------------------------------------------------------------
  3219. // McBSP External References & Function Declarations:
  3220. //
  3221. extern volatile struct MCBSP_REGS McbspaRegs;
  3222.  
  3223.  
  3224. //===========================================================================
  3225. // No more.
  3226. //===========================================================================
  3227. //
  3228. // TMDX ALPHA RELEASE
  3229. // Intended for product evaluation purposes
  3230. //
  3231. //###########################################################################
  3232. //
  3233. // FILE: DSP28_ECan.h
  3234. //
  3235. // TITLE: DSP28 Device eCAN Register Definitions.
  3236. //
  3237. //###########################################################################
  3238. //
  3239. // Ver | dd mmm yyyy | Who | Description of changes
  3240. // =====|=============|======|===============================================
  3241. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  3242. // 0.56| 20 May 2002 | L.H. | No change
  3243. // 0.57| 27 May 2002 | L.H. | No change
  3244. // 0.58| 29 Jun 2002 | L.H. | No change
  3245. //###########################################################################
  3246.  
  3247.  
  3248. /* --------------------------------------------------- */
  3249. /* eCAN Control & Status Registers */
  3250. /* ----------------------------------------------------*/
  3251.  
  3252. /* eCAN Mailbox enable register (CANME) bit definitions */
  3253. struct CANME_BITS { // bit description
  3254. Uint16 ME0:1; // 0 Enable Mailbox 0
  3255. Uint16 ME1:1; // 1 Enable Mailbox 1
  3256. Uint16 ME2:1; // 2 Enable Mailbox 2
  3257. Uint16 ME3:1; // 3 Enable Mailbox 3
  3258. Uint16 ME4:1; // 4 Enable Mailbox 4
  3259. Uint16 ME5:1; // 5 Enable Mailbox 5
  3260. Uint16 ME6:1; // 6 Enable Mailbox 6
  3261. Uint16 ME7:1; // 7 Enable Mailbox 7
  3262. Uint16 ME8:1; // 8 Enable Mailbox 8
  3263. Uint16 ME9:1; // 9 Enable Mailbox 9
  3264. Uint16 ME10:1; // 10 Enable Mailbox 10
  3265. Uint16 ME11:1; // 11 Enable Mailbox 11
  3266. Uint16 ME12:1; // 12 Enable Mailbox 12
  3267. Uint16 ME13:1; // 13 Enable Mailbox 13
  3268. Uint16 ME14:1; // 14 Enable Mailbox 14
  3269. Uint16 ME15:1; // 15 Enable Mailbox 15
  3270. Uint16 ME16:1; // 16 Enable Mailbox 16
  3271. Uint16 ME17:1; // 17 Enable Mailbox 17
  3272. Uint16 ME18:1; // 18 Enable Mailbox 18
  3273. Uint16 ME19:1; // 19 Enable Mailbox 19
  3274. Uint16 ME20:1; // 20 Enable Mailbox 20
  3275. Uint16 ME21:1; // 21 Enable Mailbox 21
  3276. Uint16 ME22:1; // 22 Enable Mailbox 22
  3277. Uint16 ME23:1; // 23 Enable Mailbox 23
  3278. Uint16 ME24:1; // 24 Enable Mailbox 24
  3279. Uint16 ME25:1; // 25 Enable Mailbox 25
  3280. Uint16 ME26:1; // 26 Enable Mailbox 26
  3281. Uint16 ME27:1; // 27 Enable Mailbox 27
  3282. Uint16 ME28:1; // 28 Enable Mailbox 28
  3283. Uint16 ME29:1; // 29 Enable Mailbox 29
  3284. Uint16 ME30:1; // 30 Enable Mailbox 30
  3285. Uint16 ME31:1; // 31 Enable Mailbox 31
  3286.  
  3287. };
  3288.  
  3289. /* Allow access to the bit fields or entire register */
  3290. union CANME_REG {
  3291. Uint32 all;
  3292. struct CANME_BITS bit;
  3293. };
  3294.  
  3295. /* eCAN Mailbox direction register (CANMD) bit definitions */
  3296. struct CANMD_BITS { // bit description
  3297. Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx
  3298. Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx
  3299. Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx
  3300. Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx
  3301. Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx
  3302. Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx
  3303. Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx
  3304. Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx
  3305. Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx
  3306. Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx
  3307. Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx
  3308. Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx
  3309. Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx
  3310. Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx
  3311. Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx
  3312. Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx
  3313. Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx
  3314. Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx
  3315. Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx
  3316. Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx
  3317. Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx
  3318. Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx
  3319. Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx
  3320. Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx
  3321. Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx
  3322. Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx
  3323. Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx
  3324. Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx
  3325. Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx
  3326. Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx
  3327. Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx
  3328. Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx
  3329.  
  3330. };
  3331.  
  3332. /* Allow access to the bit fields or entire register */
  3333. union CANMD_REG {
  3334. Uint32 all;
  3335. struct CANMD_BITS bit;
  3336. };
  3337.  
  3338. /* eCAN Transmit Request Set register (CANTRS) bit definitions */
  3339. struct CANTRS_BITS { // bit description
  3340. Uint16 TRS0:1; // 0 TRS for Mailbox 0
  3341. Uint16 TRS1:1; // 1 TRS for Mailbox 1
  3342. Uint16 TRS2:1; // 2 TRS for Mailbox 2
  3343. Uint16 TRS3:1; // 3 TRS for Mailbox 3
  3344. Uint16 TRS4:1; // 4 TRS for Mailbox 4
  3345. Uint16 TRS5:1; // 5 TRS for Mailbox 5
  3346. Uint16 TRS6:1; // 6 TRS for Mailbox 6
  3347. Uint16 TRS7:1; // 7 TRS for Mailbox 7
  3348. Uint16 TRS8:1; // 8 TRS for Mailbox 8
  3349. Uint16 TRS9:1; // 9 TRS for Mailbox 9
  3350. Uint16 TRS10:1; // 10 TRS for Mailbox 10
  3351. Uint16 TRS11:1; // 11 TRS for Mailbox 11
  3352. Uint16 TRS12:1; // 12 TRS for Mailbox 12
  3353. Uint16 TRS13:1; // 13 TRS for Mailbox 13
  3354. Uint16 TRS14:1; // 14 TRS for Mailbox 14
  3355. Uint16 TRS15:1; // 15 TRS for Mailbox 15
  3356. Uint16 TRS16:1; // 16 TRS for Mailbox 16
  3357. Uint16 TRS17:1; // 17 TRS for Mailbox 17
  3358. Uint16 TRS18:1; // 18 TRS for Mailbox 18
  3359. Uint16 TRS19:1; // 19 TRS for Mailbox 19
  3360. Uint16 TRS20:1; // 20 TRS for Mailbox 20
  3361. Uint16 TRS21:1; // 21 TRS for Mailbox 21
  3362. Uint16 TRS22:1; // 22 TRS for Mailbox 22
  3363. Uint16 TRS23:1; // 23 TRS for Mailbox 23
  3364. Uint16 TRS24:1; // 24 TRS for Mailbox 24
  3365. Uint16 TRS25:1; // 25 TRS for Mailbox 25
  3366. Uint16 TRS26:1; // 26 TRS for Mailbox 26
  3367. Uint16 TRS27:1; // 27 TRS for Mailbox 27
  3368. Uint16 TRS28:1; // 28 TRS for Mailbox 28
  3369. Uint16 TRS29:1; // 29 TRS for Mailbox 29
  3370. Uint16 TRS30:1; // 30 TRS for Mailbox 30
  3371. Uint16 TRS31:1; // 31 TRS for Mailbox 31
  3372.  
  3373. };
  3374.  
  3375. /* Allow access to the bit fields or entire register */
  3376. union CANTRS_REG {
  3377. Uint32 all;
  3378. struct CANTRS_BITS bit;
  3379. };
  3380.  
  3381. /* eCAN Transmit Request Reset register (CANTRR) bit definitions */
  3382. struct CANTRR_BITS { // bit description
  3383. Uint16 TRR0:1; // 0 TRR for Mailbox 0
  3384. Uint16 TRR1:1; // 1 TRR for Mailbox 1
  3385. Uint16 TRR2:1; // 2 TRR for Mailbox 2
  3386. Uint16 TRR3:1; // 3 TRR for Mailbox 3
  3387. Uint16 TRR4:1; // 4 TRR for Mailbox 4
  3388. Uint16 TRR5:1; // 5 TRR for Mailbox 5
  3389. Uint16 TRR6:1; // 6 TRR for Mailbox 6
  3390. Uint16 TRR7:1; // 7 TRR for Mailbox 7
  3391. Uint16 TRR8:1; // 8 TRR for Mailbox 8
  3392. Uint16 TRR9:1; // 9 TRR for Mailbox 9
  3393. Uint16 TRR10:1; // 10 TRR for Mailbox 10
  3394. Uint16 TRR11:1; // 11 TRR for Mailbox 11
  3395. Uint16 TRR12:1; // 12 TRR for Mailbox 12
  3396. Uint16 TRR13:1; // 13 TRR for Mailbox 13
  3397. Uint16 TRR14:1; // 14 TRR for Mailbox 14
  3398. Uint16 TRR15:1; // 15 TRR for Mailbox 15
  3399. Uint16 TRR16:1; // 16 TRR for Mailbox 16
  3400. Uint16 TRR17:1; // 17 TRR for Mailbox 17
  3401. Uint16 TRR18:1; // 18 TRR for Mailbox 18
  3402. Uint16 TRR19:1; // 19 TRR for Mailbox 19
  3403. Uint16 TRR20:1; // 20 TRR for Mailbox 20
  3404. Uint16 TRR21:1; // 21 TRR for Mailbox 21
  3405. Uint16 TRR22:1; // 22 TRR for Mailbox 22
  3406. Uint16 TRR23:1; // 23 TRR for Mailbox 23
  3407. Uint16 TRR24:1; // 24 TRR for Mailbox 24
  3408. Uint16 TRR25:1; // 25 TRR for Mailbox 25
  3409. Uint16 TRR26:1; // 26 TRR for Mailbox 26
  3410. Uint16 TRR27:1; // 27 TRR for Mailbox 27
  3411. Uint16 TRR28:1; // 28 TRR for Mailbox 28
  3412. Uint16 TRR29:1; // 29 TRR for Mailbox 29
  3413. Uint16 TRR30:1; // 30 TRR for Mailbox 30
  3414. Uint16 TRR31:1; // 31 TRR for Mailbox 31
  3415.  
  3416. };
  3417.  
  3418. /* Allow access to the bit fields or entire register */
  3419. union CANTRR_REG {
  3420. Uint32 all;
  3421. struct CANTRR_BITS bit;
  3422. };
  3423.  
  3424. /* eCAN Transmit Acknowledge register (CANTA) bit definitions */
  3425. struct CANTA_BITS { // bit description
  3426. Uint16 TA0:1; // 0 TA for Mailbox 0
  3427. Uint16 TA1:1; // 1 TA for Mailbox 1
  3428. Uint16 TA2:1; // 2 TA for Mailbox 2
  3429. Uint16 TA3:1; // 3 TA for Mailbox 3
  3430. Uint16 TA4:1; // 4 TA for Mailbox 4
  3431. Uint16 TA5:1; // 5 TA for Mailbox 5
  3432. Uint16 TA6:1; // 6 TA for Mailbox 6
  3433. Uint16 TA7:1; // 7 TA for Mailbox 7
  3434. Uint16 TA8:1; // 8 TA for Mailbox 8
  3435. Uint16 TA9:1; // 9 TA for Mailbox 9
  3436. Uint16 TA10:1; // 10 TA for Mailbox 10
  3437. Uint16 TA11:1; // 11 TA for Mailbox 11
  3438. Uint16 TA12:1; // 12 TA for Mailbox 12
  3439. Uint16 TA13:1; // 13 TA for Mailbox 13
  3440. Uint16 TA14:1; // 14 TA for Mailbox 14
  3441. Uint16 TA15:1; // 15 TA for Mailbox 15
  3442. Uint16 TA16:1; // 16 TA for Mailbox 16
  3443. Uint16 TA17:1; // 17 TA for Mailbox 17
  3444. Uint16 TA18:1; // 18 TA for Mailbox 18
  3445. Uint16 TA19:1; // 19 TA for Mailbox 19
  3446. Uint16 TA20:1; // 20 TA for Mailbox 20
  3447. Uint16 TA21:1; // 21 TA for Mailbox 21
  3448. Uint16 TA22:1; // 22 TA for Mailbox 22
  3449. Uint16 TA23:1; // 23 TA for Mailbox 23
  3450. Uint16 TA24:1; // 24 TA for Mailbox 24
  3451. Uint16 TA25:1; // 25 TA for Mailbox 25
  3452. Uint16 TA26:1; // 26 TA for Mailbox 26
  3453. Uint16 TA27:1; // 27 TA for Mailbox 27
  3454. Uint16 TA28:1; // 28 TA for Mailbox 28
  3455. Uint16 TA29:1; // 29 TA for Mailbox 29
  3456. Uint16 TA30:1; // 30 TA for Mailbox 30
  3457. Uint16 TA31:1; // 31 TA for Mailbox 31
  3458.  
  3459. };
  3460.  
  3461. /* Allow access to the bit fields or entire register */
  3462. union CANTA_REG {
  3463. Uint32 all;
  3464. struct CANTA_BITS bit;
  3465. };
  3466.  
  3467. /* eCAN Transmit Abort Acknowledge register (CANAA) bit definitions */
  3468. struct CANAA_BITS { // bit description
  3469. Uint16 AA0:1; // 0 AA for Mailbox 0
  3470. Uint16 AA1:1; // 1 AA for Mailbox 1
  3471. Uint16 AA2:1; // 2 AA for Mailbox 2
  3472. Uint16 AA3:1; // 3 AA for Mailbox 3
  3473. Uint16 AA4:1; // 4 AA for Mailbox 4
  3474. Uint16 AA5:1; // 5 AA for Mailbox 5
  3475. Uint16 AA6:1; // 6 AA for Mailbox 6
  3476. Uint16 AA7:1; // 7 AA for Mailbox 7
  3477. Uint16 AA8:1; // 8 AA for Mailbox 8
  3478. Uint16 AA9:1; // 9 AA for Mailbox 9
  3479. Uint16 AA10:1; // 10 AA for Mailbox 10
  3480. Uint16 AA11:1; // 11 AA for Mailbox 11
  3481. Uint16 AA12:1; // 12 AA for Mailbox 12
  3482. Uint16 AA13:1; // 13 AA for Mailbox 13
  3483. Uint16 AA14:1; // 14 AA for Mailbox 14
  3484. Uint16 AA15:1; // 15 AA for Mailbox 15
  3485. Uint16 AA16:1; // 16 AA for Mailbox 16
  3486. Uint16 AA17:1; // 17 AA for Mailbox 17
  3487. Uint16 AA18:1; // 18 AA for Mailbox 18
  3488. Uint16 AA19:1; // 19 AA for Mailbox 19
  3489. Uint16 AA20:1; // 20 AA for Mailbox 20
  3490. Uint16 AA21:1; // 21 AA for Mailbox 21
  3491. Uint16 AA22:1; // 22 AA for Mailbox 22
  3492. Uint16 AA23:1; // 23 AA for Mailbox 23
  3493. Uint16 AA24:1; // 24 AA for Mailbox 24
  3494. Uint16 AA25:1; // 25 AA for Mailbox 25
  3495. Uint16 AA26:1; // 26 AA for Mailbox 26
  3496. Uint16 AA27:1; // 27 AA for Mailbox 27
  3497. Uint16 AA28:1; // 28 AA for Mailbox 28
  3498. Uint16 AA29:1; // 29 AA for Mailbox 29
  3499. Uint16 AA30:1; // 30 AA for Mailbox 30
  3500. Uint16 AA31:1; // 31 AA for Mailbox 31
  3501.  
  3502. };
  3503.  
  3504. /* Allow access to the bit fields or entire register */
  3505. union CANAA_REG {
  3506. Uint32 all;
  3507. struct CANAA_BITS bit;
  3508. };
  3509.  
  3510. /* eCAN Received Message Pending register (CANRMP) bit definitions */
  3511. struct CANRMP_BITS { // bit description
  3512. Uint16 RMP0:1; // 0 RMP for Mailbox 0
  3513. Uint16 RMP1:1; // 1 RMP for Mailbox 1
  3514. Uint16 RMP2:1; // 2 RMP for Mailbox 2
  3515. Uint16 RMP3:1; // 3 RMP for Mailbox 3
  3516. Uint16 RMP4:1; // 4 RMP for Mailbox 4
  3517. Uint16 RMP5:1; // 5 RMP for Mailbox 5
  3518. Uint16 RMP6:1; // 6 RMP for Mailbox 6
  3519. Uint16 RMP7:1; // 7 RMP for Mailbox 7
  3520. Uint16 RMP8:1; // 8 RMP for Mailbox 8
  3521. Uint16 RMP9:1; // 9 RMP for Mailbox 9
  3522. Uint16 RMP10:1; // 10 RMP for Mailbox 10
  3523. Uint16 RMP11:1; // 11 RMP for Mailbox 11
  3524. Uint16 RMP12:1; // 12 RMP for Mailbox 12
  3525. Uint16 RMP13:1; // 13 RMP for Mailbox 13
  3526. Uint16 RMP14:1; // 14 RMP for Mailbox 14
  3527. Uint16 RMP15:1; // 15 RMP for Mailbox 15
  3528. Uint16 RMP16:1; // 16 RMP for Mailbox 16
  3529. Uint16 RMP17:1; // 17 RMP for Mailbox 17
  3530. Uint16 RMP18:1; // 18 RMP for Mailbox 18
  3531. Uint16 RMP19:1; // 19 RMP for Mailbox 19
  3532. Uint16 RMP20:1; // 20 RMP for Mailbox 20
  3533. Uint16 RMP21:1; // 21 RMP for Mailbox 21
  3534. Uint16 RMP22:1; // 22 RMP for Mailbox 22
  3535. Uint16 RMP23:1; // 23 RMP for Mailbox 23
  3536. Uint16 RMP24:1; // 24 RMP for Mailbox 24
  3537. Uint16 RMP25:1; // 25 RMP for Mailbox 25
  3538. Uint16 RMP26:1; // 26 RMP for Mailbox 26
  3539. Uint16 RMP27:1; // 27 RMP for Mailbox 27
  3540. Uint16 RMP28:1; // 28 RMP for Mailbox 28
  3541. Uint16 RMP29:1; // 29 RMP for Mailbox 29
  3542. Uint16 RMP30:1; // 30 RMP for Mailbox 30
  3543. Uint16 RMP31:1; // 31 RMP for Mailbox 31
  3544.  
  3545. };
  3546.  
  3547. /* Allow access to the bit fields or entire register */
  3548. union CANRMP_REG {
  3549. Uint32 all;
  3550. struct CANRMP_BITS bit;
  3551. };
  3552.  
  3553. /* eCAN Received Message Lost register (CANRML) bit definitions */
  3554. struct CANRML_BITS { // bit description
  3555. Uint16 RML0:1; // 0 RML for Mailbox 0
  3556. Uint16 RML1:1; // 1 RML for Mailbox 1
  3557. Uint16 RML2:1; // 2 RML for Mailbox 2
  3558. Uint16 RML3:1; // 3 RML for Mailbox 3
  3559. Uint16 RML4:1; // 4 RML for Mailbox 4
  3560. Uint16 RML5:1; // 5 RML for Mailbox 5
  3561. Uint16 RML6:1; // 6 RML for Mailbox 6
  3562. Uint16 RML7:1; // 7 RML for Mailbox 7
  3563. Uint16 RML8:1; // 8 RML for Mailbox 8
  3564. Uint16 RML9:1; // 9 RML for Mailbox 9
  3565. Uint16 RML10:1; // 10 RML for Mailbox 10
  3566. Uint16 RML11:1; // 11 RML for Mailbox 11
  3567. Uint16 RML12:1; // 12 RML for Mailbox 12
  3568. Uint16 RML13:1; // 13 RML for Mailbox 13
  3569. Uint16 RML14:1; // 14 RML for Mailbox 14
  3570. Uint16 RML15:1; // 15 RML for Mailbox 15
  3571. Uint16 RML16:1; // 16 RML for Mailbox 16
  3572. Uint16 RML17:1; // 17 RML for Mailbox 17
  3573. Uint16 RML18:1; // 18 RML for Mailbox 18
  3574. Uint16 RML19:1; // 19 RML for Mailbox 19
  3575. Uint16 RML20:1; // 20 RML for Mailbox 20
  3576. Uint16 RML21:1; // 21 RML for Mailbox 21
  3577. Uint16 RML22:1; // 22 RML for Mailbox 22
  3578. Uint16 RML23:1; // 23 RML for Mailbox 23
  3579. Uint16 RML24:1; // 24 RML for Mailbox 24
  3580. Uint16 RML25:1; // 25 RML for Mailbox 25
  3581. Uint16 RML26:1; // 26 RML for Mailbox 26
  3582. Uint16 RML27:1; // 27 RML for Mailbox 27
  3583. Uint16 RML28:1; // 28 RML for Mailbox 28
  3584. Uint16 RML29:1; // 29 RML for Mailbox 29
  3585. Uint16 RML30:1; // 30 RML for Mailbox 30
  3586. Uint16 RML31:1; // 31 RML for Mailbox 31
  3587.  
  3588. };
  3589.  
  3590. /* Allow access to the bit fields or entire register */
  3591. union CANRML_REG {
  3592. Uint32 all;
  3593. struct CANRML_BITS bit;
  3594. };
  3595.  
  3596. /* eCAN Remote Frame Pending register (CANRFP) bit definitions */
  3597. struct CANRFP_BITS { // bit description
  3598. Uint16 RFP0:1; // 0 RFP for Mailbox 0
  3599. Uint16 RFP1:1; // 1 RFP for Mailbox 1
  3600. Uint16 RFP2:1; // 2 RFP for Mailbox 2
  3601. Uint16 RFP3:1; // 3 RFP for Mailbox 3
  3602. Uint16 RFP4:1; // 4 RFP for Mailbox 4
  3603. Uint16 RFP5:1; // 5 RFP for Mailbox 5
  3604. Uint16 RFP6:1; // 6 RFP for Mailbox 6
  3605. Uint16 RFP7:1; // 7 RFP for Mailbox 7
  3606. Uint16 RFP8:1; // 8 RFP for Mailbox 8
  3607. Uint16 RFP9:1; // 9 RFP for Mailbox 9
  3608. Uint16 RFP10:1; // 10 RFP for Mailbox 10
  3609. Uint16 RFP11:1; // 11 RFP for Mailbox 11
  3610. Uint16 RFP12:1; // 12 RFP for Mailbox 12
  3611. Uint16 RFP13:1; // 13 RFP for Mailbox 13
  3612. Uint16 RFP14:1; // 14 RFP for Mailbox 14
  3613. Uint16 RFP15:1; // 15 RFP for Mailbox 15
  3614. Uint16 RFP16:1; // 16 RFP for Mailbox 16
  3615. Uint16 RFP17:1; // 17 RFP for Mailbox 17
  3616. Uint16 RFP18:1; // 18 RFP for Mailbox 18
  3617. Uint16 RFP19:1; // 19 RFP for Mailbox 19
  3618. Uint16 RFP20:1; // 20 RFP for Mailbox 20
  3619. Uint16 RFP21:1; // 21 RFP for Mailbox 21
  3620. Uint16 RFP22:1; // 22 RFP for Mailbox 22
  3621. Uint16 RFP23:1; // 23 RFP for Mailbox 23
  3622. Uint16 RFP24:1; // 24 RFP for Mailbox 24
  3623. Uint16 RFP25:1; // 25 RFP for Mailbox 25
  3624. Uint16 RFP26:1; // 26 RFP for Mailbox 26
  3625. Uint16 RFP27:1; // 27 RFP for Mailbox 27
  3626. Uint16 RFP28:1; // 28 RFP for Mailbox 28
  3627. Uint16 RFP29:1; // 29 RFP for Mailbox 29
  3628. Uint16 RFP30:1; // 30 RFP for Mailbox 30
  3629. Uint16 RFP31:1; // 31 RFP for Mailbox 31
  3630.  
  3631. };
  3632.  
  3633. /* Allow access to the bit fields or entire register */
  3634. union CANRFP_REG {
  3635. Uint32 all;
  3636. struct CANRFP_BITS bit;
  3637. };
  3638.  
  3639. /* eCAN Global Acceptance Mask register (CANGAM) bit definitions */
  3640. struct CANGAM_BITS { // bits description
  3641. Uint16 GAM150:16; // 15:0
  3642. Uint16 GAM2816:13; // 28:16
  3643. Uint16 rsvd:2; // 30:29
  3644. Uint16 AMI:1; // 31 AMI bit
  3645. };
  3646.  
  3647. /* Allow access to the bit fields or entire register */
  3648. union CANGAM_REG {
  3649. Uint32 all;
  3650. struct CANGAM_BITS bit;
  3651. };
  3652.  
  3653.  
  3654. /* eCAN Master Control register (CANMC) bit definitions */
  3655. struct CANMC_BITS { // bits description
  3656. Uint16 MBNR:5; // 4:0 MBX # for CDR bit
  3657. Uint16 SRES:1; // 5 Soft reset
  3658. Uint16 STM:1; // 6 Self-test mode
  3659. Uint16 ABO:1; // 7 Auto bus-on
  3660. Uint16 CDR:1; // 8 Change data request
  3661. Uint16 WUBA:1; // 9 Wake-up on bus activity
  3662. Uint16 DBO:1; // 10 Data-byte order
  3663. Uint16 PDR:1; // 11 Power-down mode request
  3664. Uint16 CCR:1; // 12 Change configuration request
  3665. Uint16 SCM:1; // 13 SCC compatibility mode
  3666. Uint16 LNTM:1; // 14 LNT MSB clear bit
  3667. Uint16 LNTC:1; // 15 LNT clear bit thru mailbox 16
  3668. Uint16 SUSP:1; // 16 SUSPEND free/soft bit
  3669. Uint16 rsvd:15; // 31:17 reserved
  3670. };
  3671.  
  3672. /* Allow access to the bit fields or entire register */
  3673. union CANMC_REG {
  3674. Uint32 all;
  3675. struct CANMC_BITS bit;
  3676. };
  3677.  
  3678. /* eCAN Bit -timing configuration register (CANBTC) bit definitions */
  3679. struct CANBTC_BITS { // bits description
  3680. Uint16 TSEG2:3; // 2:0 TSEG2
  3681. Uint16 TSEG1:4; // 6:3 TSEG1
  3682. Uint16 SAM:1; // 7 Sample-point setting
  3683. Uint16 SJW:2; // 9:8 Synchroniztion Jump Width
  3684. Uint16 ERM:1; // 10 Edge resynchroniztion mode
  3685. Uint16 rsvd1:5; // 15:11 reserved
  3686. Uint16 BRP:8; // 23:16 Time quantum prescaler
  3687. Uint16 rsvd2:8; // 31:24 reserved
  3688. };
  3689.  
  3690. /* Allow access to the bit fields or entire register */
  3691. union CANBTC_REG {
  3692. Uint32 all;
  3693. struct CANBTC_BITS bit;
  3694. };
  3695.  
  3696. /* eCAN Error & Status register (CANES) bit definitions */
  3697. struct CANES_BITS { // bits description
  3698. Uint16 TM:1; // 0 TM
  3699. Uint16 RM:1; // 1 RM
  3700. Uint16 rsvd1:1; // 2 reserved
  3701. Uint16 PDA:1; // 3 Power-down acknowledge
  3702. Uint16 CCE:1; // 4 Change Configuration Enable
  3703. Uint16 SMA:1; // 5 Suspend Mode Acknowledge
  3704. Uint16 rsvd2:10; // 15:6 reserved
  3705. Uint16 EW:1; // 16 EW
  3706. Uint16 EP:1; // 17 EP
  3707. Uint16 BO:1; // 18 BO
  3708. Uint16 ACKE:1; // 19 ACKE
  3709. Uint16 SE:1; // 20 SE
  3710. Uint16 CRCE:1; // 21 CRCE
  3711. Uint16 SA1:1; // 22 SA1
  3712. Uint16 BE:1; // 23 BE
  3713. Uint16 FE:1; // 24 FE
  3714. Uint16 rsvd3:7; // 31:25 reserved
  3715. };
  3716.  
  3717. /* Allow access to the bit fields or entire register */
  3718. union CANES_REG {
  3719. Uint32 all;
  3720. struct CANES_BITS bit;
  3721. };
  3722.  
  3723.  
  3724. /* eCAN Transmit Error Counter register (CANTEC) bit definitions */
  3725. struct CANTEC_BITS { // bits description
  3726. Uint16 TEC:8; // 7:0 TEC
  3727. Uint16 rsvd1:8; // 15:8 reserved
  3728. Uint16 rsvd2:16; // 31:16 reserved
  3729. };
  3730.  
  3731. /* Allow access to the bit fields or entire register */
  3732. union CANTEC_REG {
  3733. Uint32 all;
  3734. struct CANTEC_BITS bit;
  3735. };
  3736.  
  3737. /* eCAN Receive Error Counter register (CANREC) bit definitions */
  3738. struct CANREC_BITS { // bits description
  3739. Uint16 REC:8; // 7:0 REC
  3740. Uint16 rsvd1:8; // 15:8 reserved
  3741. Uint16 rsvd2:16; // 31:16 reserved
  3742. };
  3743.  
  3744. /* Allow access to the bit fields or entire register */
  3745. union CANREC_REG {
  3746. Uint32 all;
  3747. struct CANREC_BITS bit;
  3748. };
  3749.  
  3750. /* eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions */
  3751. struct CANGIF0_BITS { // bits description
  3752. Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector
  3753. Uint16 rsvd1:3; // 7:5 reserved
  3754. Uint16 WLIF0:1; // 8 WLIF0
  3755. Uint16 EPIF0:1; // 9 EPIF0
  3756. Uint16 BOIF0:1; // 10 BOIF0
  3757. Uint16 RMLIF0:1; // 11 RMLIF0
  3758. Uint16 WUIF0:1; // 12 WUIF0
  3759. Uint16 WDIF0:1; // 13 WDIF0
  3760. Uint16 AAIF0:1; // 14 AAIF0
  3761. Uint16 GMIF0:1; // 15 GMIF0
  3762. Uint16 TCOIF0:1; // 16 TCOIF0
  3763. Uint16 MAIF0:1; // 17 MAIF0
  3764. Uint16 rsvd2:14; // 31:18 reserved
  3765. };
  3766.  
  3767. /* Allow access to the bit fields or entire register */
  3768. union CANGIF0_REG {
  3769. Uint32 all;
  3770. struct CANGIF0_BITS bit;
  3771. };
  3772.  
  3773. /* eCAN Global Interrupt Mask register (CANGIM) bit definitions */
  3774. struct CANGIM_BITS { // bits description
  3775. Uint16 I0EN:1; // 0 Interrupt 0 enable
  3776. Uint16 I1EN:1; // 1 Interrupt 1 enable
  3777. Uint16 SIL:1; // 2 System Interrupt Level
  3778. Uint16 rsvd1:5; // 7:3 reserved
  3779. Uint16 WLIM:1; // 8 WLIM
  3780. Uint16 EPIM:1; // 9 EPIM
  3781. Uint16 BOIM:1; // 10 BOIM
  3782. Uint16 RMLIM:1; // 11 RMLIM
  3783. Uint16 WUIM:1; // 12 WUIM
  3784. Uint16 WDIM:1; // 13 WDIM
  3785. Uint16 AAIM:1; // 14 AAIM
  3786. Uint16 rsvd2:1; // 15 reserved
  3787. Uint16 TCOIM:1; // 16 TCOIM
  3788. Uint16 MAIM:1; // 17 MAIM
  3789. Uint16 rsvd3:14; // 31:18 reserved
  3790. };
  3791.  
  3792. /* Allow access to the bit fields or entire register */
  3793. union CANGIM_REG {
  3794. Uint32 all;
  3795. struct CANGIM_BITS bit;
  3796. };
  3797.  
  3798.  
  3799. /* eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions */
  3800. struct CANGIF1_BITS { // bits description
  3801. Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector
  3802. Uint16 rsvd1:3; // 7:5 reserved
  3803. Uint16 WLIF1:1; // 8 WLIF1
  3804. Uint16 EPIF1:1; // 9 EPIF1
  3805. Uint16 BOIF1:1; // 11 BOIF1
  3806. Uint16 RMLIF1:1; // 11 RMLIF1
  3807. Uint16 WUIF1:1; // 12 WUIF1
  3808. Uint16 WDIF1:1; // 13 WDIF1
  3809. Uint16 AAIF1:1; // 14 AAIF1
  3810. Uint16 GMIF1:1; // 15 GMIF1
  3811. Uint16 TCOIF1:1; // 16 TCOIF1
  3812. Uint16 MAIF1:1; // 17 MAIF1
  3813. Uint16 rsvd2:14; // 31:18 reserved
  3814. };
  3815.  
  3816. /* Allow access to the bit fields or entire register */
  3817. union CANGIF1_REG {
  3818. Uint32 all;
  3819. struct CANGIF1_BITS bit;
  3820. };
  3821.  
  3822.  
  3823. /* eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions */
  3824. struct CANMIM_BITS { // bit description
  3825. Uint16 MIM0:1; // 0 MIM for Mailbox 0
  3826. Uint16 MIM1:1; // 1 MIM for Mailbox 1
  3827. Uint16 MIM2:1; // 2 MIM for Mailbox 2
  3828. Uint16 MIM3:1; // 3 MIM for Mailbox 3
  3829. Uint16 MIM4:1; // 4 MIM for Mailbox 4
  3830. Uint16 MIM5:1; // 5 MIM for Mailbox 5
  3831. Uint16 MIM6:1; // 6 MIM for Mailbox 6
  3832. Uint16 MIM7:1; // 7 MIM for Mailbox 7
  3833. Uint16 MIM8:1; // 8 MIM for Mailbox 8
  3834. Uint16 MIM9:1; // 9 MIM for Mailbox 9
  3835. Uint16 MIM10:1; // 10 MIM for Mailbox 10
  3836. Uint16 MIM11:1; // 11 MIM for Mailbox 11
  3837. Uint16 MIM12:1; // 12 MIM for Mailbox 12
  3838. Uint16 MIM13:1; // 13 MIM for Mailbox 13
  3839. Uint16 MIM14:1; // 14 MIM for Mailbox 14
  3840. Uint16 MIM15:1; // 15 MIM for Mailbox 15
  3841. Uint16 MIM16:1; // 16 MIM for Mailbox 16
  3842. Uint16 MIM17:1; // 17 MIM for Mailbox 17
  3843. Uint16 MIM18:1; // 18 MIM for Mailbox 18
  3844. Uint16 MIM19:1; // 19 MIM for Mailbox 19
  3845. Uint16 MIM20:1; // 20 MIM for Mailbox 20
  3846. Uint16 MIM21:1; // 21 MIM for Mailbox 21
  3847. Uint16 MIM22:1; // 22 MIM for Mailbox 22
  3848. Uint16 MIM23:1; // 23 MIM for Mailbox 23
  3849. Uint16 MIM24:1; // 24 MIM for Mailbox 24
  3850. Uint16 MIM25:1; // 25 MIM for Mailbox 25
  3851. Uint16 MIM26:1; // 26 MIM for Mailbox 26
  3852. Uint16 MIM27:1; // 27 MIM for Mailbox 27
  3853. Uint16 MIM28:1; // 28 MIM for Mailbox 28
  3854. Uint16 MIM29:1; // 29 MIM for Mailbox 29
  3855. Uint16 MIM30:1; // 30 MIM for Mailbox 30
  3856. Uint16 MIM31:1; // 31 MIM for Mailbox 31
  3857.  
  3858. };
  3859.  
  3860. /* Allow access to the bit fields or entire register */
  3861. union CANMIM_REG {
  3862. Uint32 all;
  3863. struct CANMIM_BITS bit;
  3864. };
  3865.  
  3866. /* eCAN Mailbox Interrupt Level register (CANMIL) bit definitions */
  3867. struct CANMIL_BITS { // bit description
  3868. Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6
  3869. Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6
  3870. Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6
  3871. Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6
  3872. Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6
  3873. Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6
  3874. Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6
  3875. Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6
  3876. Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6
  3877. Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6
  3878. Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6
  3879. Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6
  3880. Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6
  3881. Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6
  3882. Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6
  3883. Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6
  3884. Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6
  3885. Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6
  3886. Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6
  3887. Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6
  3888. Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6
  3889. Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6
  3890. Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6
  3891. Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6
  3892. Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6
  3893. Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6
  3894. Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6
  3895. Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6
  3896. Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6
  3897. Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6
  3898. Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6
  3899. Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6
  3900.  
  3901. };
  3902.  
  3903. /* Allow access to the bit fields or entire register */
  3904. union CANMIL_REG {
  3905. Uint32 all;
  3906. struct CANMIL_BITS bit;
  3907. };
  3908.  
  3909.  
  3910. /* eCAN Overwrite Protection Control register (CANOPC) bit definitions */
  3911. struct CANOPC_BITS { // bit description
  3912. Uint16 OPC0:1; // 0 OPC for Mailbox 0
  3913. Uint16 OPC1:1; // 1 OPC for Mailbox 1
  3914. Uint16 OPC2:1; // 2 OPC for Mailbox 2
  3915. Uint16 OPC3:1; // 3 OPC for Mailbox 3
  3916. Uint16 OPC4:1; // 4 OPC for Mailbox 4
  3917. Uint16 OPC5:1; // 5 OPC for Mailbox 5
  3918. Uint16 OPC6:1; // 6 OPC for Mailbox 6
  3919. Uint16 OPC7:1; // 7 OPC for Mailbox 7
  3920. Uint16 OPC8:1; // 8 OPC for Mailbox 8
  3921. Uint16 OPC9:1; // 9 OPC for Mailbox 9
  3922. Uint16 OPC10:1; // 10 OPC for Mailbox 10
  3923. Uint16 OPC11:1; // 11 OPC for Mailbox 11
  3924. Uint16 OPC12:1; // 12 OPC for Mailbox 12
  3925. Uint16 OPC13:1; // 13 OPC for Mailbox 13
  3926. Uint16 OPC14:1; // 14 OPC for Mailbox 14
  3927. Uint16 OPC15:1; // 15 OPC for Mailbox 15
  3928. Uint16 OPC16:1; // 16 OPC for Mailbox 16
  3929. Uint16 OPC17:1; // 17 OPC for Mailbox 17
  3930. Uint16 OPC18:1; // 18 OPC for Mailbox 18
  3931. Uint16 OPC19:1; // 19 OPC for Mailbox 19
  3932. Uint16 OPC20:1; // 20 OPC for Mailbox 20
  3933. Uint16 OPC21:1; // 21 OPC for Mailbox 21
  3934. Uint16 OPC22:1; // 22 OPC for Mailbox 22
  3935. Uint16 OPC23:1; // 23 OPC for Mailbox 23
  3936. Uint16 OPC24:1; // 24 OPC for Mailbox 24
  3937. Uint16 OPC25:1; // 25 OPC for Mailbox 25
  3938. Uint16 OPC26:1; // 26 OPC for Mailbox 26
  3939. Uint16 OPC27:1; // 27 OPC for Mailbox 27
  3940. Uint16 OPC28:1; // 28 OPC for Mailbox 28
  3941. Uint16 OPC29:1; // 29 OPC for Mailbox 29
  3942. Uint16 OPC30:1; // 30 OPC for Mailbox 30
  3943. Uint16 OPC31:1; // 31 OPC for Mailbox 31
  3944.  
  3945. };
  3946.  
  3947. /* Allow access to the bit fields or entire register */
  3948. union CANOPC_REG {
  3949. Uint32 all;
  3950. struct CANOPC_BITS bit;
  3951. };
  3952.  
  3953.  
  3954. /* eCAN TX I/O Control Register (CANTIOC) bit definitions */
  3955. struct CANTIOC_BITS { // bits description
  3956. Uint16 TXIN:1; // 0 TXIN
  3957. Uint16 TXOUT:1; // 1 TXOUT
  3958. Uint16 TXDIR:1; // 2 TXDIR
  3959. Uint16 TXFUNC:1; // 3 TXFUNC
  3960. Uint16 rsvd1:12; // 15:4 reserved
  3961. Uint16 rsvd2:16; // 31:16 reserved
  3962. };
  3963.  
  3964. /* Allow access to the bit fields or entire register */
  3965. union CANTIOC_REG {
  3966. Uint32 all;
  3967. struct CANTIOC_BITS bit;
  3968. };
  3969.  
  3970. /* eCAN RX I/O Control Register (CANRIOC) bit definitions */
  3971. struct CANRIOC_BITS { // bits description
  3972. Uint16 RXIN:1; // 0 RXIN
  3973. Uint16 RXOUT:1; // 1 RXOUT
  3974. Uint16 RXDIR:1; // 2 RXDIR
  3975. Uint16 RXFUNC:1; // 3 RXFUNC
  3976. Uint16 rsvd1:12; // 15:4 reserved
  3977. Uint16 rsvd2:16; // 31:16 reserved
  3978. };
  3979.  
  3980. /* Allow access to the bit fields or entire register */
  3981. union CANRIOC_REG {
  3982. Uint32 all;
  3983. struct CANRIOC_BITS bit;
  3984. };
  3985.  
  3986.  
  3987. /* eCAN Local Network Timer register (CANLNT) bit definitions */
  3988. struct CANLNT_BITS { // bit description
  3989. Uint16 LNT0:1; // 0 LNT for Mailbox 0
  3990. Uint16 LNT1:1; // 1 LNT for Mailbox 1
  3991. Uint16 LNT2:1; // 2 LNT for Mailbox 2
  3992. Uint16 LNT3:1; // 3 LNT for Mailbox 3
  3993. Uint16 LNT4:1; // 4 LNT for Mailbox 4
  3994. Uint16 LNT5:1; // 5 LNT for Mailbox 5
  3995. Uint16 LNT6:1; // 6 LNT for Mailbox 6
  3996. Uint16 LNT7:1; // 7 LNT for Mailbox 7
  3997. Uint16 LNT8:1; // 8 LNT for Mailbox 8
  3998. Uint16 LNT9:1; // 9 LNT for Mailbox 9
  3999. Uint16 LNT10:1; // 10 LNT for Mailbox 10
  4000. Uint16 LNT11:1; // 11 LNT for Mailbox 11
  4001. Uint16 LNT12:1; // 12 LNT for Mailbox 12
  4002. Uint16 LNT13:1; // 13 LNT for Mailbox 13
  4003. Uint16 LNT14:1; // 14 LNT for Mailbox 14
  4004. Uint16 LNT15:1; // 15 LNT for Mailbox 15
  4005. Uint16 LNT16:1; // 16 LNT for Mailbox 16
  4006. Uint16 LNT17:1; // 17 LNT for Mailbox 17
  4007. Uint16 LNT18:1; // 18 LNT for Mailbox 18
  4008. Uint16 LNT19:1; // 19 LNT for Mailbox 19
  4009. Uint16 LNT20:1; // 20 LNT for Mailbox 20
  4010. Uint16 LNT21:1; // 21 LNT for Mailbox 21
  4011. Uint16 LNT22:1; // 22 LNT for Mailbox 22
  4012. Uint16 LNT23:1; // 23 LNT for Mailbox 23
  4013. Uint16 LNT24:1; // 24 LNT for Mailbox 24
  4014. Uint16 LNT25:1; // 25 LNT for Mailbox 25
  4015. Uint16 LNT26:1; // 26 LNT for Mailbox 26
  4016. Uint16 LNT27:1; // 27 LNT for Mailbox 27
  4017. Uint16 LNT28:1; // 28 LNT for Mailbox 28
  4018. Uint16 LNT29:1; // 29 LNT for Mailbox 29
  4019. Uint16 LNT30:1; // 30 LNT for Mailbox 30
  4020. Uint16 LNT31:1; // 31 LNT for Mailbox 31
  4021.  
  4022. };
  4023.  
  4024. /* Allow access to the bit fields or entire register */
  4025. union CANLNT_REG {
  4026. Uint32 all;
  4027. struct CANLNT_BITS bit;
  4028. };
  4029.  
  4030.  
  4031.  
  4032. /* eCAN Time-out Control register (CANTOC) bit definitions */
  4033. struct CANTOC_BITS { // bit description
  4034. Uint16 TOC0:1; // 0 TOC for Mailbox 0
  4035. Uint16 TOC1:1; // 1 TOC for Mailbox 1
  4036. Uint16 TOC2:1; // 2 TOC for Mailbox 2
  4037. Uint16 TOC3:1; // 3 TOC for Mailbox 3
  4038. Uint16 TOC4:1; // 4 TOC for Mailbox 4
  4039. Uint16 TOC5:1; // 5 TOC for Mailbox 5
  4040. Uint16 TOC6:1; // 6 TOC for Mailbox 6
  4041. Uint16 TOC7:1; // 7 TOC for Mailbox 7
  4042. Uint16 TOC8:1; // 8 TOC for Mailbox 8
  4043. Uint16 TOC9:1; // 9 TOC for Mailbox 9
  4044. Uint16 TOC10:1; // 10 TOC for Mailbox 10
  4045. Uint16 TOC11:1; // 11 TOC for Mailbox 11
  4046. Uint16 TOC12:1; // 12 TOC for Mailbox 12
  4047. Uint16 TOC13:1; // 13 TOC for Mailbox 13
  4048. Uint16 TOC14:1; // 14 TOC for Mailbox 14
  4049. Uint16 TOC15:1; // 15 TOC for Mailbox 15
  4050. Uint16 TOC16:1; // 16 TOC for Mailbox 16
  4051. Uint16 TOC17:1; // 17 TOC for Mailbox 17
  4052. Uint16 TOC18:1; // 18 TOC for Mailbox 18
  4053. Uint16 TOC19:1; // 19 TOC for Mailbox 19
  4054. Uint16 TOC20:1; // 20 TOC for Mailbox 20
  4055. Uint16 TOC21:1; // 21 TOC for Mailbox 21
  4056. Uint16 TOC22:1; // 22 TOC for Mailbox 22
  4057. Uint16 TOC23:1; // 23 TOC for Mailbox 23
  4058. Uint16 TOC24:1; // 24 TOC for Mailbox 24
  4059. Uint16 TOC25:1; // 25 TOC for Mailbox 25
  4060. Uint16 TOC26:1; // 26 TOC for Mailbox 26
  4061. Uint16 TOC27:1; // 27 TOC for Mailbox 27
  4062. Uint16 TOC28:1; // 28 TOC for Mailbox 28
  4063. Uint16 TOC29:1; // 29 TOC for Mailbox 29
  4064. Uint16 TOC30:1; // 30 TOC for Mailbox 30
  4065. Uint16 TOC31:1; // 31 TOC for Mailbox 31
  4066.  
  4067. };
  4068.  
  4069. /* Allow access to the bit fields or entire register */
  4070. union CANTOC_REG {
  4071. Uint32 all;
  4072. struct CANTOC_BITS bit;
  4073. };
  4074.  
  4075.  
  4076. /* eCAN Time-out Status register (CANTOS) bit definitions */
  4077. struct CANTOS_BITS { // bit description
  4078. Uint16 TOS0:1; // 0 TOS for Mailbox 0
  4079. Uint16 TOS1:1; // 1 TOS for Mailbox 1
  4080. Uint16 TOS2:1; // 2 TOS for Mailbox 2
  4081. Uint16 TOS3:1; // 3 TOS for Mailbox 3
  4082. Uint16 TOS4:1; // 4 TOS for Mailbox 4
  4083. Uint16 TOS5:1; // 5 TOS for Mailbox 5
  4084. Uint16 TOS6:1; // 6 TOS for Mailbox 6
  4085. Uint16 TOS7:1; // 7 TOS for Mailbox 7
  4086. Uint16 TOS8:1; // 8 TOS for Mailbox 8
  4087. Uint16 TOS9:1; // 9 TOS for Mailbox 9
  4088. Uint16 TOS10:1; // 10 TOS for Mailbox 10
  4089. Uint16 TOS11:1; // 11 TOS for Mailbox 11
  4090. Uint16 TOS12:1; // 12 TOS for Mailbox 12
  4091. Uint16 TOS13:1; // 13 TOS for Mailbox 13
  4092. Uint16 TOS14:1; // 14 TOS for Mailbox 14
  4093. Uint16 TOS15:1; // 15 TOS for Mailbox 15
  4094. Uint16 TOS16:1; // 16 TOS for Mailbox 16
  4095. Uint16 TOS17:1; // 17 TOS for Mailbox 17
  4096. Uint16 TOS18:1; // 18 TOS for Mailbox 18
  4097. Uint16 TOS19:1; // 19 TOS for Mailbox 19
  4098. Uint16 TOS20:1; // 20 TOS for Mailbox 20
  4099. Uint16 TOS21:1; // 21 TOS for Mailbox 21
  4100. Uint16 TOS22:1; // 22 TOS for Mailbox 22
  4101. Uint16 TOS23:1; // 23 TOS for Mailbox 23
  4102. Uint16 TOS24:1; // 24 TOS for Mailbox 24
  4103. Uint16 TOS25:1; // 25 TOS for Mailbox 25
  4104. Uint16 TOS26:1; // 26 TOS for Mailbox 26
  4105. Uint16 TOS27:1; // 27 TOS for Mailbox 27
  4106. Uint16 TOS28:1; // 28 TOS for Mailbox 28
  4107. Uint16 TOS29:1; // 29 TOS for Mailbox 29
  4108. Uint16 TOS30:1; // 30 TOS for Mailbox 30
  4109. Uint16 TOS31:1; // 31 TOS for Mailbox 31
  4110.  
  4111. };
  4112.  
  4113. /* Allow access to the bit fields or entire register */
  4114. union CANTOS_REG {
  4115. Uint32 all;
  4116. struct CANTOS_BITS bit;
  4117. };
  4118.  
  4119. /**************************************/
  4120. /* eCAN Control & Status register file */
  4121. /**************************************/
  4122.  
  4123. struct ECAN_REGS {
  4124. union CANME_REG CANME; // Mailbox Enable
  4125. union CANMD_REG CANMD; // Mailbox Direction
  4126. union CANTRS_REG CANTRS; // Transmit Request Set
  4127. union CANTRR_REG CANTRR; // Transmit Request Reset
  4128. union CANTA_REG CANTA; // Transmit Acknowledge
  4129. union CANAA_REG CANAA; // Abort Acknowledge
  4130. union CANRMP_REG CANRMP; // Received Message Pending
  4131. union CANRML_REG CANRML; // Received Message Lost
  4132. union CANRFP_REG CANRFP; // Remote Frame Pending
  4133. union CANGAM_REG CANGAM; // Global Acceptance Mask
  4134. union CANMC_REG CANMC; // Master Control
  4135. union CANBTC_REG CANBTC; // Bit Timing
  4136. union CANES_REG CANES; // Error Status
  4137. union CANTEC_REG CANTEC; // Transmit Error Counter
  4138. union CANREC_REG CANREC; // Receive Error Counter
  4139. union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0
  4140. union CANGIM_REG CANGIM; // Global Interrupt Mask 0
  4141. union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1
  4142. union CANMIM_REG CANMIM; // Mailbox Interrupt Mask
  4143. union CANMIL_REG CANMIL; // Mailbox Interrupt Level
  4144. union CANOPC_REG CANOPC; // Overwrite Protection Control
  4145. union CANTIOC_REG CANTIOC; // TX I/O Control
  4146. union CANRIOC_REG CANRIOC; // RX I/O Control
  4147. union CANLNT_REG CANLNT; // Local Network Time
  4148. union CANTOC_REG CANTOC; // Time-out Control
  4149. union CANTOS_REG CANTOS; // Time-out Status
  4150.  
  4151. };
  4152.  
  4153. /* --------------------------------------------------- */
  4154. /* eCAN Mailbox Registers */
  4155. /* ----------------------------------------------------*/
  4156.  
  4157. /* eCAN Message ID (MID) bit definitions */
  4158. struct CANMID_BITS { // bits description
  4159. Uint16 MSGID_L:16; // 0:15
  4160. Uint16 MSGID_H:13; // 16:28
  4161. Uint16 AAM:1; // 29
  4162. Uint16 AME:1; // 30
  4163. Uint16 IDE:1; // 31
  4164. };
  4165.  
  4166. /* Allow access to the bit fields or entire register */
  4167. union CANMID_REG {
  4168. Uint32 all;
  4169. struct CANMID_BITS bit;
  4170. };
  4171.  
  4172. /* eCAN Master Control Field (MCF) bit definitions */
  4173. struct CANMCF_BITS { // bits description
  4174. Uint16 DLC:4; // 0:3
  4175. Uint16 RTR:1; // 4
  4176. Uint16 rsvd1:3; // 7:5 reserved
  4177. Uint16 TPL:5; // 12:8
  4178. Uint16 rsvd2:3; // 15:13 reserved
  4179. Uint16 rsvd3:16; // 31:16 reserved
  4180. };
  4181.  
  4182. /* Allow access to the bit fields or entire register */
  4183. union CANMCF_REG {
  4184. Uint32 all;
  4185. struct CANMCF_BITS bit;
  4186. };
  4187.  
  4188. /* eCAN Message Data Register low (MDR_L) bit definitions */
  4189. struct CANMDRL_BITS { // bits description
  4190. Uint16 LOW_WORD:16; // 0:15
  4191. Uint16 HI_WORD:16; // 31:16
  4192. };
  4193.  
  4194. /* Allow access to the bit fields or entire register */
  4195. union CANMDRL_REG {
  4196. Uint32 all;
  4197. struct CANMDRL_BITS bit;
  4198. };
  4199.  
  4200. /* eCAN Message Data Register high (MDR_H) bit definitions */
  4201. struct CANMDRH_BITS { // bits description
  4202. Uint16 LOW_WORD:16; // 0:15
  4203. Uint16 HI_WORD:16; // 31:16
  4204. };
  4205.  
  4206. /* Allow access to the bit fields or entire register */
  4207. union CANMDRH_REG {
  4208. Uint32 all;
  4209. struct CANMDRH_BITS bit;
  4210. };
  4211.  
  4212. struct MBOX {
  4213. union CANMID_REG MID;
  4214. union CANMCF_REG MCF;
  4215. union CANMDRL_REG MDRL;
  4216. union CANMDRH_REG MDRH;
  4217. };
  4218.  
  4219. /**************************************/
  4220. /* eCAN Mailboxes */
  4221. /**************************************/
  4222.  
  4223. struct ECAN_MBOXES {
  4224. struct MBOX MBOX0;
  4225. struct MBOX MBOX1;
  4226. struct MBOX MBOX2;
  4227. struct MBOX MBOX3;
  4228. struct MBOX MBOX4;
  4229. struct MBOX MBOX5;
  4230. struct MBOX MBOX6;
  4231. struct MBOX MBOX7;
  4232. struct MBOX MBOX8;
  4233. struct MBOX MBOX9;
  4234. struct MBOX MBOX10;
  4235. struct MBOX MBOX11;
  4236. struct MBOX MBOX12;
  4237. struct MBOX MBOX13;
  4238. struct MBOX MBOX14;
  4239. struct MBOX MBOX15;
  4240. struct MBOX MBOX16;
  4241. struct MBOX MBOX17;
  4242. struct MBOX MBOX18;
  4243. struct MBOX MBOX19;
  4244. struct MBOX MBOX20;
  4245. struct MBOX MBOX21;
  4246. struct MBOX MBOX22;
  4247. struct MBOX MBOX23;
  4248. struct MBOX MBOX24;
  4249. struct MBOX MBOX25;
  4250. struct MBOX MBOX26;
  4251. struct MBOX MBOX27;
  4252. struct MBOX MBOX28;
  4253. struct MBOX MBOX29;
  4254. struct MBOX MBOX30;
  4255. struct MBOX MBOX31;
  4256. };
  4257.  
  4258. /* eCAN Local Acceptance Mask (LAM) bit definitions */
  4259. struct CANLAM_BITS { // bits description
  4260. Uint16 LAM_L:16; // 0:15
  4261. Uint16 LAM_H:13; // 16:28
  4262. Uint16 rsvd1:2; // 29:30 reserved
  4263. Uint16 LAMI:1; // 31
  4264. };
  4265.  
  4266. /* Allow access to the bit fields or entire register */
  4267. union CANLAM_REG {
  4268. Uint32 all;
  4269. struct CANLAM_BITS bit;
  4270. };
  4271.  
  4272.  
  4273. /**************************************/
  4274. /* eCAN Local Acceptance Masks */
  4275. /**************************************/
  4276.  
  4277. /* eCAN LAM File */
  4278. struct LAM_REGS {
  4279. union CANLAM_REG LAM0;
  4280. union CANLAM_REG LAM1;
  4281. union CANLAM_REG LAM2;
  4282. union CANLAM_REG LAM3;
  4283. union CANLAM_REG LAM4;
  4284. union CANLAM_REG LAM5;
  4285. union CANLAM_REG LAM6;
  4286. union CANLAM_REG LAM7;
  4287. union CANLAM_REG LAM8;
  4288. union CANLAM_REG LAM9;
  4289. union CANLAM_REG LAM10;
  4290. union CANLAM_REG LAM11;
  4291. union CANLAM_REG LAM12;
  4292. union CANLAM_REG LAM13;
  4293. union CANLAM_REG LAM14;
  4294. union CANLAM_REG LAM15;
  4295. union CANLAM_REG LAM16;
  4296. union CANLAM_REG LAM17;
  4297. union CANLAM_REG LAM18;
  4298. union CANLAM_REG LAM19;
  4299. union CANLAM_REG LAM20;
  4300. union CANLAM_REG LAM21;
  4301. union CANLAM_REG LAM22;
  4302. union CANLAM_REG LAM23;
  4303. union CANLAM_REG LAM24;
  4304. union CANLAM_REG LAM25;
  4305. union CANLAM_REG LAM26;
  4306. union CANLAM_REG LAM27;
  4307. union CANLAM_REG LAM28;
  4308. union CANLAM_REG LAM29;
  4309. union CANLAM_REG LAM30;
  4310. union CANLAM_REG LAM31;
  4311. };
  4312.  
  4313. /* Mailbox MOTS File */
  4314.  
  4315. struct MOTS {
  4316. unsigned long MOTS0;
  4317. unsigned long MOTS1;
  4318. unsigned long MOTS2;
  4319. unsigned long MOTS3;
  4320. unsigned long MOTS4;
  4321. unsigned long MOTS5;
  4322. unsigned long MOTS6;
  4323. unsigned long MOTS7;
  4324. unsigned long MOTS8;
  4325. unsigned long MOTS9;
  4326. unsigned long MOTS10;
  4327. unsigned long MOTS11;
  4328. unsigned long MOTS12;
  4329. unsigned long MOTS13;
  4330. unsigned long MOTS14;
  4331. unsigned long MOTS15;
  4332. unsigned long MOTS16;
  4333. unsigned long MOTS17;
  4334. unsigned long MOTS18;
  4335. unsigned long MOTS19;
  4336. unsigned long MOTS20;
  4337. unsigned long MOTS21;
  4338. unsigned long MOTS22;
  4339. unsigned long MOTS23;
  4340. unsigned long MOTS24;
  4341. unsigned long MOTS25;
  4342. unsigned long MOTS26;
  4343. unsigned long MOTS27;
  4344. unsigned long MOTS28;
  4345. unsigned long MOTS29;
  4346. unsigned long MOTS30;
  4347. unsigned long MOTS31;
  4348. };
  4349.  
  4350. /* Mailbox MOTO File */
  4351.  
  4352. struct MOTO {
  4353. unsigned long MOTO0;
  4354. unsigned long MOTO1;
  4355. unsigned long MOTO2;
  4356. unsigned long MOTO3;
  4357. unsigned long MOTO4;
  4358. unsigned long MOTO5;
  4359. unsigned long MOTO6;
  4360. unsigned long MOTO7;
  4361. unsigned long MOTO8;
  4362. unsigned long MOTO9;
  4363. unsigned long MOTO10;
  4364. unsigned long MOTO11;
  4365. unsigned long MOTO12;
  4366. unsigned long MOTO13;
  4367. unsigned long MOTO14;
  4368. unsigned long MOTO15;
  4369. unsigned long MOTO16;
  4370. unsigned long MOTO17;
  4371. unsigned long MOTO18;
  4372. unsigned long MOTO19;
  4373. unsigned long MOTO20;
  4374. unsigned long MOTO21;
  4375. unsigned long MOTO22;
  4376. unsigned long MOTO23;
  4377. unsigned long MOTO24;
  4378. unsigned long MOTO25;
  4379. unsigned long MOTO26;
  4380. unsigned long MOTO27;
  4381. unsigned long MOTO28;
  4382. unsigned long MOTO29;
  4383. unsigned long MOTO30;
  4384. unsigned long MOTO31;
  4385. };
  4386.  
  4387.  
  4388. //---------------------------------------------------------------------------
  4389. // eCAN External References & Function Declarations:
  4390. //
  4391. extern volatile struct ECAN_REGS ECanaRegs;
  4392. extern volatile struct LAM_REGS ECanaLAMRegs;
  4393. extern volatile struct ECAN_MBOXES ECanaMboxes;
  4394.  
  4395. // eCAN control registers require read/write access using 32-bits. Thus we
  4396. // will create a set of shadow registers for this example. These shadow
  4397. // registers will be used to make sure the access is 32-bits and not 16.
  4398. //сама структура определена в файле
  4399. // co_Init.c в программе длЯ оперативного выделениЯ памЯти
  4400.  
  4401.  
  4402. //===========================================================================
  4403. // No more.
  4404. //===========================================================================
  4405. //
  4406. // TMDX ALPHA RELEASE
  4407. // Intended for product evaluation purposes
  4408. //
  4409. //###########################################################################
  4410. //
  4411. // FILE: DSP28_Gpio.h
  4412. //
  4413. // TITLE: DSP28 General Purpose I/O Definitions.
  4414. //
  4415. //###########################################################################
  4416. //
  4417. // Ver | dd mmm yyyy | Who | Description of changes
  4418. // =====|=============|======|===============================================
  4419. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  4420. // 0.56| 20 May 2002 | L.H. | No change
  4421. // 0.57| 24 May 2002 | L.H. | Fixed typo's on GPIOG registers
  4422. // 0.58| 29 Jun 2002 | L.H. | No change
  4423. //###########################################################################
  4424.  
  4425.  
  4426. //----------------------------------------------------
  4427. // General purpose I/O (GPIO) Register Bit Definitions
  4428.  
  4429. //----------------------------------------------------
  4430. // GPIO A mux control register bit definitions */
  4431. //
  4432. //
  4433. struct GPAMUX_BITS { // bits description
  4434. Uint16 PWM1_GPIOA0:1; // 0
  4435. Uint16 PWM2_GPIOA1:1; // 1
  4436. Uint16 PWM3_GPIOA2:1; // 2
  4437. Uint16 PWM4_GPIOA3:1; // 3
  4438. Uint16 PWM5_GPIOA4:1; // 4
  4439. Uint16 PWM6_GPIOA5:1; // 5
  4440. Uint16 T1PWM_GPIOA6:1; // 6
  4441. Uint16 T2PWM_GPIOA7:1; // 7
  4442. Uint16 CAP1Q1_GPIOA8:1; // 8
  4443. Uint16 CAP2Q2_GPIOA9:1; // 9
  4444. Uint16 CAP3QI1_GPIOA10:1; // 10
  4445. Uint16 TDIRA_GPIOA11:1; // 11
  4446. Uint16 TCLKINA_GPIOA12:1; // 12
  4447. Uint16 C1TRIP_GPIOA13:1; // 13
  4448. Uint16 C2TRIP_GPIOA14:1; // 14
  4449. Uint16 C3TRIP_GPIOA15:1; // 15
  4450.  
  4451. };
  4452.  
  4453. union GPAMUX_REG {
  4454. Uint16 all;
  4455. struct GPAMUX_BITS bit;
  4456. };
  4457.  
  4458.  
  4459.  
  4460. //---------------------------------------------------------------------------------------
  4461. // GPIO A Direction control register bit definitions
  4462. //
  4463. //
  4464. struct GPADIR_BITS { // bits description
  4465. Uint16 GPIOA0:1; // 0
  4466. Uint16 GPIOA1:1; // 1
  4467. Uint16 GPIOA2:1; // 2
  4468. Uint16 GPIOA3:1; // 3
  4469. Uint16 GPIOA4:1; // 4
  4470. Uint16 GPIOA5:1; // 5
  4471. Uint16 GPIOA6:1; // 6
  4472. Uint16 GPIOA7:1; // 7
  4473. Uint16 GPIOA8:1; // 8
  4474. Uint16 GPIOA9:1; // 9
  4475. Uint16 GPIOA10:1; // 10
  4476. Uint16 GPIOA11:1; // 11
  4477. Uint16 GPIOA12:1; // 12
  4478. Uint16 GPIOA13:1; // 13
  4479. Uint16 GPIOA14:1; // 14
  4480. Uint16 GPIOA15:1; // 15
  4481.  
  4482. };
  4483.  
  4484. union GPADIR_REG {
  4485. Uint16 all;
  4486. struct GPADIR_BITS bit;
  4487. };
  4488.  
  4489. //----------------------------------
  4490. // GPA Qualregister bit definitions
  4491. //
  4492. //
  4493.  
  4494. struct GPAQUAL_BITS { // bits description
  4495. Uint16 QUALPRD:8; // 0:7 Qualification Sampling Period
  4496. Uint16 rsvd1:8; // 15:8 reserved
  4497. };
  4498.  
  4499. union GPAQUAL_REG {
  4500. Uint16 all;
  4501. struct GPAQUAL_BITS BIT;
  4502. };
  4503.  
  4504.  
  4505. //---------------------------------------------------------------------------------------
  4506. // GPIO A Data register bit definitions
  4507. //
  4508. //
  4509. struct GPADAT_BITS { // bits description
  4510. Uint16 GPIOA0:1; // 0
  4511. Uint16 GPIOA1:1; // 1
  4512. Uint16 GPIOA2:1; // 2
  4513. Uint16 GPIOA3:1; // 3
  4514. Uint16 GPIOA4:1; // 4
  4515. Uint16 GPIOA5:1; // 5
  4516. Uint16 GPIOA6:1; // 6
  4517. Uint16 GPIOA7:1; // 7
  4518. Uint16 GPIOA8:1; // 8
  4519. Uint16 GPIOA9:1; // 9
  4520. Uint16 GPIOA10:1; // 10
  4521. Uint16 GPIOA11:1; // 11
  4522. Uint16 GPIOA12:1; // 12
  4523. Uint16 GPIOA13:1; // 13
  4524. Uint16 GPIOA14:1; // 14
  4525. Uint16 GPIOA15:1; // 15
  4526.  
  4527. };
  4528.  
  4529. union GPADAT_REG {
  4530. Uint16 all;
  4531. struct GPADAT_BITS bit;
  4532. };
  4533.  
  4534.  
  4535. //---------------------------------------------------------------------------------------
  4536. // GPIO A Data set bit definitions
  4537. //
  4538. //
  4539. struct GPASET_BITS { // bits description
  4540. Uint16 GPIOA0:1; // 0
  4541. Uint16 GPIOA1:1; // 1
  4542. Uint16 GPIOA2:1; // 2
  4543. Uint16 GPIOA3:1; // 3
  4544. Uint16 GPIOA4:1; // 4
  4545. Uint16 GPIOA5:1; // 5
  4546. Uint16 GPIOA6:1; // 6
  4547. Uint16 GPIOA7:1; // 7
  4548. Uint16 GPIOA8:1; // 8
  4549. Uint16 GPIOA9:1; // 9
  4550. Uint16 GPIOA10:1; // 10
  4551. Uint16 GPIOA11:1; // 11
  4552. Uint16 GPIOA12:1; // 12
  4553. Uint16 GPIOA13:1; // 13
  4554. Uint16 GPIOA14:1; // 14
  4555. Uint16 GPIOA15:1; // 15
  4556.  
  4557. };
  4558.  
  4559. union GPASET_REG {
  4560. Uint16 all;
  4561. struct GPASET_BITS bit;
  4562. };
  4563.  
  4564.  
  4565.  
  4566. //---------------------------------------------------------------------------------------
  4567. // GPIO A Data clear register bit definitions
  4568. //
  4569. //
  4570. struct GPACLEAR_BITS { // bits description
  4571. Uint16 GPIOA0:1; // 0
  4572. Uint16 GPIOA1:1; // 1
  4573. Uint16 GPIOA2:1; // 2
  4574. Uint16 GPIOA3:1; // 3
  4575. Uint16 GPIOA4:1; // 4
  4576. Uint16 GPIOA5:1; // 5
  4577. Uint16 GPIOA6:1; // 6
  4578. Uint16 GPIOA7:1; // 7
  4579. Uint16 GPIOA8:1; // 8
  4580. Uint16 GPIOA9:1; // 9
  4581. Uint16 GPIOA10:1; // 10
  4582. Uint16 GPIOA11:1; // 11
  4583. Uint16 GPIOA12:1; // 12
  4584. Uint16 GPIOA13:1; // 13
  4585. Uint16 GPIOA14:1; // 14
  4586. Uint16 GPIOA15:1; // 15
  4587.  
  4588. };
  4589.  
  4590. union GPACLEAR_REG {
  4591. Uint16 all;
  4592. struct GPACLEAR_BITS bit;
  4593. };
  4594.  
  4595. //---------------------------------------------------------------------------------------
  4596. // GPIO A Data toggle register bit definitions
  4597. //
  4598. //
  4599. struct GPATOGGLE_BITS { // bits description
  4600. Uint16 GPIOA0:1; // 0
  4601. Uint16 GPIOA1:1; // 1
  4602. Uint16 GPIOA2:1; // 2
  4603. Uint16 GPIOA3:1; // 3
  4604. Uint16 GPIOA4:1; // 4
  4605. Uint16 GPIOA5:1; // 5
  4606. Uint16 GPIOA6:1; // 6
  4607. Uint16 GPIOA7:1; // 7
  4608. Uint16 GPIOA8:1; // 8
  4609. Uint16 GPIOA9:1; // 9
  4610. Uint16 GPIOA10:1; // 10
  4611. Uint16 GPIOA11:1; // 11
  4612. Uint16 GPIOA12:1; // 12
  4613. Uint16 GPIOA13:1; // 13
  4614. Uint16 GPIOA14:1; // 14
  4615. Uint16 GPIOA15:1; // 15
  4616.  
  4617. };
  4618.  
  4619. union GPATOGGLE_REG {
  4620. Uint16 all;
  4621. struct GPATOGGLE_BITS bit;
  4622. };
  4623.  
  4624.  
  4625.  
  4626. //---------------------------------------------------------------------------------
  4627. // GPIO B mux control register bit definitions
  4628. //
  4629. //
  4630. struct GPBMUX_BITS { // bits description
  4631. Uint16 PWM7_GPIOB0:1; // 0
  4632. Uint16 PWM8_GPIOB1:1; // 1
  4633. Uint16 PWM9_GPIOB2:1; // 2
  4634. Uint16 PWM10_GPIOB3:1; // 3
  4635. Uint16 PWM11_GPIOB4:1; // 4
  4636. Uint16 PWM12_GPIOB5:1; // 5
  4637. Uint16 T3PWM_GPIOB6:1; // 6
  4638. Uint16 T4PWM_GPIOB7:1; // 7
  4639. Uint16 CAP4Q1_GPIOB8:1; // 8
  4640. Uint16 CAP5Q2_GPIOB9:1; // 9
  4641. Uint16 CAP6QI2_GPIOB10:1; // 10
  4642. Uint16 TDIRB_GPIOB11:1; // 11
  4643. Uint16 TCLKINB_GPIOB12:1; // 12
  4644. Uint16 C4TRIP_GPIOB13:1; // 13
  4645. Uint16 C5TRIP_GPIOB14:1; // 14
  4646. Uint16 C6TRIP_GPIOB15:1; // 15
  4647. };
  4648.  
  4649. union GPBMUX_REG {
  4650. Uint16 all;
  4651. struct GPBMUX_BITS bit;
  4652. };
  4653.  
  4654. //---------------------------------------------------------------------------------------
  4655. // GPIO B Direction control register bit definitions
  4656. //
  4657. //
  4658. struct GPBDIR_BITS { // bits description
  4659. Uint16 GPIOB0:1; // 0
  4660. Uint16 GPIOB1:1; // 1
  4661. Uint16 GPIOB2:1; // 2
  4662. Uint16 GPIOB3:1; // 3
  4663. Uint16 GPIOB4:1; // 4
  4664. Uint16 GPIOB5:1; // 5
  4665. Uint16 GPIOB6:1; // 6
  4666. Uint16 GPIOB7:1; // 7
  4667. Uint16 GPIOB8:1; // 8
  4668. Uint16 GPIOB9:1; // 9
  4669. Uint16 GPIOB10:1; // 10
  4670. Uint16 GPIOB11:1; // 11
  4671. Uint16 GPIOB12:1; // 12
  4672. Uint16 GPIOB13:1; // 13
  4673. Uint16 GPIOB14:1; // 14
  4674. Uint16 GPIOB15:1; // 15
  4675.  
  4676. };
  4677.  
  4678. union GPBDIR_REG {
  4679. Uint16 all;
  4680. struct GPBDIR_BITS bit;
  4681. };
  4682.  
  4683. //-----------------------------------
  4684. // GPB Qualregister bit definitions
  4685. //
  4686. //
  4687.  
  4688. struct GPBQUAL_BITS { // bits description
  4689. Uint16 QUALPRD:8; // 0:7 Qualification Sampling Period
  4690. Uint16 rsvd1:8; // 15:8 reserved
  4691. };
  4692.  
  4693. union GPBQUAL_REG {
  4694. Uint16 all;
  4695. struct GPBQUAL_BITS BIT;
  4696. };
  4697.  
  4698.  
  4699. //---------------------------------------------------------------------------------------
  4700. // GPIO B data register bit definitions
  4701. //
  4702. //
  4703. struct GPBDAT_BITS { // bits description
  4704. Uint16 GPIOB0:1; // 0
  4705. Uint16 GPIOB1:1; // 1
  4706. Uint16 GPIOB2:1; // 2
  4707. Uint16 GPIOB3:1; // 3
  4708. Uint16 GPIOB4:1; // 4
  4709. Uint16 GPIOB5:1; // 5
  4710. Uint16 GPIOB6:1; // 6
  4711. Uint16 GPIOB7:1; // 7
  4712. Uint16 GPIOB8:1; // 8
  4713. Uint16 GPIOB9:1; // 9
  4714. Uint16 GPIOB10:1; // 10
  4715. Uint16 GPIOB11:1; // 11
  4716. Uint16 GPIOB12:1; // 12
  4717. Uint16 GPIOB13:1; // 13
  4718. Uint16 GPIOB14:1; // 14
  4719. Uint16 GPIOB15:1; // 15
  4720.  
  4721. };
  4722.  
  4723. union GPBDAT_REG {
  4724. Uint16 all;
  4725. struct GPBDAT_BITS bit;
  4726. };
  4727.  
  4728.  
  4729.  
  4730. //---------------------------------------------------------------------------------------
  4731. // GPIO B data set register bit definitions
  4732. //
  4733. //
  4734. struct GPBSET_BITS { // bits description
  4735. Uint16 GPIOB0:1; // 0
  4736. Uint16 GPIOB1:1; // 1
  4737. Uint16 GPIOB2:1; // 2
  4738. Uint16 GPIOB3:1; // 3
  4739. Uint16 GPIOB4:1; // 4
  4740. Uint16 GPIOB5:1; // 5
  4741. Uint16 GPIOB6:1; // 6
  4742. Uint16 GPIOB7:1; // 7
  4743. Uint16 GPIOB8:1; // 8
  4744. Uint16 GPIOB9:1; // 9
  4745. Uint16 GPIOB10:1; // 10
  4746. Uint16 GPIOB11:1; // 11
  4747. Uint16 GPIOB12:1; // 12
  4748. Uint16 GPIOB13:1; // 13
  4749. Uint16 GPIOB14:1; // 14
  4750. Uint16 GPIOB15:1; // 15
  4751.  
  4752. };
  4753.  
  4754.  
  4755. union GPBSET_REG {
  4756. Uint16 all;
  4757. struct GPBSET_BITS bit;
  4758. };
  4759.  
  4760.  
  4761. //---------------------------------------------------------------------------------------
  4762. // GPIO B data clear register bit definitions
  4763. //
  4764. //
  4765. struct GPBCLEAR_BITS { // bits description
  4766. Uint16 GPIOB0:1; // 0
  4767. Uint16 GPIOB1:1; // 1
  4768. Uint16 GPIOB2:1; // 2
  4769. Uint16 GPIOB3:1; // 3
  4770. Uint16 GPIOB4:1; // 4
  4771. Uint16 GPIOB5:1; // 5
  4772. Uint16 GPIOB6:1; // 6
  4773. Uint16 GPIOB7:1; // 7
  4774. Uint16 GPIOB8:1; // 8
  4775. Uint16 GPIOB9:1; // 9
  4776. Uint16 GPIOB10:1; // 10
  4777. Uint16 GPIOB11:1; // 11
  4778. Uint16 GPIOB12:1; // 12
  4779. Uint16 GPIOB13:1; // 13
  4780. Uint16 GPIOB14:1; // 14
  4781. Uint16 GPIOB15:1; // 15
  4782.  
  4783. };
  4784.  
  4785. union GPBCLEAR_REG {
  4786. Uint16 all;
  4787. struct GPBCLEAR_BITS bit;
  4788. };
  4789.  
  4790.  
  4791.  
  4792. //---------------------------------------------------------------------------------------
  4793. // GPIO B data toggle register bit definitions
  4794. //
  4795. //
  4796. struct GPBTOGGLE_BITS { // bits description
  4797. Uint16 GPIOB0:1; // 0
  4798. Uint16 GPIOB1:1; // 1
  4799. Uint16 GPIOB2:1; // 2
  4800. Uint16 GPIOB3:1; // 3
  4801. Uint16 GPIOB4:1; // 4
  4802. Uint16 GPIOB5:1; // 5
  4803. Uint16 GPIOB6:1; // 6
  4804. Uint16 GPIOB7:1; // 7
  4805. Uint16 GPIOB8:1; // 8
  4806. Uint16 GPIOB9:1; // 9
  4807. Uint16 GPIOB10:1; // 10
  4808. Uint16 GPIOB11:1; // 11
  4809. Uint16 GPIOB12:1; // 12
  4810. Uint16 GPIOB13:1; // 13
  4811. Uint16 GPIOB14:1; // 14
  4812. Uint16 GPIOB15:1; // 15
  4813.  
  4814. };
  4815.  
  4816. union GPBTOGGLE_REG {
  4817. Uint16 all;
  4818. struct GPBTOGGLE_BITS bit;
  4819. };
  4820.  
  4821.  
  4822. //---------------------------------------------------------------------------------
  4823. // GPIO D mux control register bit definitions
  4824. //
  4825. //
  4826. struct GPDMUX_BITS { // bits description
  4827. Uint16 T1CTRIP_PDPA_GPIOD0:1; // 0
  4828. Uint16 T2CTRIP_SOCA_GPIOD1:1; // 1
  4829. Uint16 rsvd1:3; // 4:2
  4830. Uint16 T3CTRIP_PDPB_GPIOD5:1; // 5
  4831. Uint16 T4CTRIP_SOCB_GPIOD6:1; // 6
  4832. Uint16 rsvd2:9; // 15:7
  4833.  
  4834. };
  4835.  
  4836. union GPDMUX_REG {
  4837. Uint16 all;
  4838. struct GPDMUX_BITS bit;
  4839. };
  4840.  
  4841. //----------------------------------------------------
  4842. // GPIO D Direction control register bit definitions
  4843. //
  4844. //
  4845. struct GPDDIR_BITS { // bits description
  4846. Uint16 GPIOD0:1; // 0
  4847. Uint16 GPIOD1:1; // 1
  4848. Uint16 rsvd1:3; // 4:2
  4849. Uint16 GPIOD5:1; // 5
  4850. Uint16 GPIOD6:1; // 6
  4851. Uint16 rsvd2:9; // 15:7
  4852. };
  4853.  
  4854. union GPDDIR_REG {
  4855. Uint16 all;
  4856. struct GPDDIR_BITS bit;
  4857. };
  4858.  
  4859.  
  4860. //----------------------------------------------------
  4861. // GPIO D data register bit definitions
  4862. //
  4863. //
  4864. struct GPDDAT_BITS { // bits description
  4865. Uint16 GPIOD0:1; // 0
  4866. Uint16 GPIOD1:1; // 1
  4867. Uint16 rsvd1:3; // 4:2
  4868. Uint16 GPIOD5:1; // 5
  4869. Uint16 GPIOD6:1; // 6
  4870. Uint16 rsvd2:9; // 15:7
  4871. };
  4872.  
  4873. union GPDDAT_REG {
  4874. Uint16 all;
  4875. struct GPDDAT_BITS bit;
  4876. };
  4877.  
  4878.  
  4879. //----------------------------------------------------
  4880. // GPIO D data set register bit definitions
  4881. //
  4882. //
  4883. struct GPDSET_BITS { // bits description
  4884. Uint16 GPIOD0:1; // 0
  4885. Uint16 GPIOD1:1; // 1
  4886. Uint16 rsvd1:3; // 4:2
  4887. Uint16 GPIOD5:1; // 5
  4888. Uint16 GPIOD6:1; // 6
  4889. Uint16 rsvd2:9; // 15:7
  4890. };
  4891.  
  4892. union GPDSET_REG {
  4893. Uint16 all;
  4894. struct GPDSET_BITS bit;
  4895. };
  4896.  
  4897.  
  4898. //----------------------------------------------------
  4899. // GPIO D data clear register bit definitions
  4900. //
  4901. //
  4902. struct GPDCLEAR_BITS { // bits description
  4903. Uint16 GPIOD0:1; // 0
  4904. Uint16 GPIOD1:1; // 1
  4905. Uint16 rsvd1:3; // 4:2
  4906. Uint16 GPIOD5:1; // 5
  4907. Uint16 GPIOD6:1; // 6
  4908. Uint16 rsvd2:9; // 15:7
  4909. };
  4910.  
  4911. union GPDCLEAR_REG {
  4912. Uint16 all;
  4913. struct GPDCLEAR_BITS bit;
  4914. };
  4915.  
  4916.  
  4917.  
  4918. //----------------------------------------------------
  4919. // GPIO D data toggle register bit definitions
  4920. //
  4921. //
  4922. struct GPDTOGGLE_BITS { // bits description
  4923. Uint16 GPIOD0:1; // 0
  4924. Uint16 GPIOD1:1; // 1
  4925. Uint16 rsvd1:3; // 4:2
  4926. Uint16 GPIOD5:1; // 5
  4927. Uint16 GPIOD6:1; // 6
  4928. Uint16 rsvd2:9; // 15:7
  4929. };
  4930.  
  4931. union GPDTOGGLE_REG {
  4932. Uint16 all;
  4933. struct GPDTOGGLE_BITS bit;
  4934. };
  4935.  
  4936.  
  4937.  
  4938. //----------------------------------
  4939. // GPIOD Qualregister bit definitions
  4940. //
  4941. //
  4942. struct GPDQUAL_BITS { // bits description
  4943. Uint16 QUALPRD:8; // 0:7 Qualification Sampling Period
  4944. Uint16 rsvd1:8; // 15:8 reserved
  4945. };
  4946.  
  4947. union GPDQUAL_REG {
  4948. Uint16 all;
  4949. struct GPDQUAL_BITS BIT;
  4950. };
  4951.  
  4952.  
  4953. //---------------------------------------------
  4954. // GPIO E mux control register bit definitions
  4955. //
  4956. //
  4957. struct GPEMUX_BITS { // bits description
  4958. Uint16 XINT1_XBIO_GPIOE0:1; // 0
  4959. Uint16 XINT2_ADCSOC_GPIOE1:1; // 1
  4960. Uint16 XNMI_XINT13_GPIOE2:1; // 2
  4961. Uint16 rsvd1:12; // 15:3
  4962.  
  4963. };
  4964.  
  4965. union GPEMUX_REG {
  4966. Uint16 all;
  4967. struct GPEMUX_BITS bit;
  4968. };
  4969.  
  4970. //---------------------------------------------------
  4971. // GPIO E Direction control register bit definitions
  4972. //
  4973. //
  4974. struct GPEDIR_BITS { // bits description
  4975. Uint16 GPIOE0:1; // 0
  4976. Uint16 GPIOE1:1; // 1
  4977. Uint16 GPIOE2:1; // 2
  4978. Uint16 rsvd1:12; // 15:3
  4979. };
  4980.  
  4981. union GPEDIR_REG {
  4982. Uint16 all;
  4983. struct GPEDIR_BITS bit;
  4984. };
  4985.  
  4986. //---------------------------------------------------
  4987. // GPIO E data register bit definitions
  4988. //
  4989. //
  4990. struct GPEDAT_BITS { // bits description
  4991. Uint16 GPIOE0:1; // 0
  4992. Uint16 GPIOE1:1; // 1
  4993. Uint16 GPIOE2:1; // 2
  4994. Uint16 rsvd1:12; // 15:3
  4995. };
  4996.  
  4997. union GPEDAT_REG {
  4998. Uint16 all;
  4999. struct GPEDAT_BITS bit;
  5000. };
  5001.  
  5002.  
  5003.  
  5004. //---------------------------------------------------
  5005. // GPIO E data set register bit definitions
  5006. //
  5007. //
  5008. struct GPESET_BITS { // bits description
  5009. Uint16 GPIOE0:1; // 0
  5010. Uint16 GPIOE1:1; // 1
  5011. Uint16 GPIOE2:1; // 2
  5012. Uint16 rsvd1:12; // 15:3
  5013. };
  5014.  
  5015. union GPESET_REG {
  5016. Uint16 all;
  5017. struct GPESET_BITS bit;
  5018. };
  5019.  
  5020.  
  5021. //---------------------------------------------------
  5022. // GPIO E data clear register bit definitions
  5023. //
  5024. //
  5025. struct GPECLEAR_BITS { // bits description
  5026. Uint16 GPIOE0:1; // 0
  5027. Uint16 GPIOE1:1; // 1
  5028. Uint16 GPIOE2:1; // 2
  5029. Uint16 rsvd1:12; // 15:3
  5030. };
  5031.  
  5032. union GPECLEAR_REG {
  5033. Uint16 all;
  5034. struct GPECLEAR_BITS bit;
  5035. };
  5036.  
  5037.  
  5038. //---------------------------------------------------
  5039. // GPIO E data toggle register bit definitions
  5040. //
  5041. //
  5042. struct GPETOGGLE_BITS { // bits description
  5043. Uint16 GPIOE0:1; // 0
  5044. Uint16 GPIOE1:1; // 1
  5045. Uint16 GPIOE2:1; // 2
  5046. Uint16 rsvd1:12; // 15:3
  5047. };
  5048.  
  5049. union GPETOGGLE_REG {
  5050. Uint16 all;
  5051. struct GPETOGGLE_BITS bit;
  5052. };
  5053.  
  5054.  
  5055.  
  5056. //-----------------------------------
  5057. // GPIOE Qualregister bit definitions
  5058. //
  5059. //
  5060. struct GPEQUAL_BITS { // bits description
  5061. Uint16 QUALPRD:8; // 0:7 Qualification Sampling Period
  5062. Uint16 rsvd1:8; // 15:8 reserved
  5063. };
  5064.  
  5065. union GPEQUAL_REG {
  5066. Uint16 all;
  5067. struct GPEQUAL_BITS BIT;
  5068. };
  5069.  
  5070.  
  5071. //----------------------------------------------
  5072. // GPIO F mux control register bit definitions
  5073. //
  5074. //
  5075. struct GPFMUX_BITS { // bits description
  5076. Uint16 SPISIMOA_GPIOF0:1; // 0
  5077. Uint16 SPISOMIA_GPIOF1:1; // 1
  5078. Uint16 SPICLKA_GPIOF2:1; // 2
  5079. Uint16 SPISTEA_GPIOF3:1; // 3
  5080. Uint16 SCITXDA_GPIOF4:1; // 4
  5081. Uint16 SCIRXDA_GPIOF5:1; // 5
  5082. Uint16 CANTXA_GPIOF6:1; // 6
  5083. Uint16 CANRXA_GPIOF7:1; // 7
  5084. Uint16 MCLKXA_GPIOF8:1; // 8
  5085. Uint16 MCLKRA_GPIOF9:1; // 9
  5086. Uint16 MFSXA_GPIOF10:1; // 10
  5087. Uint16 MFSRA_GPIOF11:1; // 11
  5088. Uint16 MDXA_GPIOF12:1; // 12
  5089. Uint16 MDRA_GPIOF13:1; // 13
  5090. Uint16 XF_GPIOF14:1; // 14
  5091. Uint16 spare_GPIOF15:1; // 15
  5092.  
  5093. };
  5094.  
  5095. /* Allow access to the bit fields or entire register */
  5096. union GPFMUX_REG {
  5097. Uint16 all;
  5098. struct GPFMUX_BITS bit;
  5099. };
  5100.  
  5101. //---------------------------------------------------
  5102. // GPIO F Direction control register bit definitions
  5103. //
  5104. //
  5105.  
  5106. struct GPFDIR_BITS { // bits description
  5107. Uint16 GPIOF0:1; // 0
  5108. Uint16 GPIOF1:1; // 1
  5109. Uint16 GPIOF2:1; // 2
  5110. Uint16 GPIOF3:1; // 3
  5111. Uint16 GPIOF4:1; // 4
  5112. Uint16 GPIOF5:1; // 5
  5113. Uint16 GPIOF6:1; // 6
  5114. Uint16 GPIOF7:1; // 7
  5115. Uint16 GPIOF8:1; // 8
  5116. Uint16 GPIOF9:1; // 9
  5117. Uint16 GPIOF10:1; // 10
  5118. Uint16 GPIOF11:1; // 11
  5119. Uint16 GPIOF12:1; // 12
  5120. Uint16 GPIOF13:1; // 13
  5121. Uint16 GPIOF14:1; // 14
  5122. Uint16 GPIOF15:1; // 15
  5123.  
  5124. };
  5125.  
  5126. union GPFDIR_REG {
  5127. Uint16 all;
  5128. struct GPFDIR_BITS bit;
  5129. };
  5130.  
  5131. //---------------------------------------------------
  5132. // GPIO F data register bit definitions
  5133. //
  5134. //
  5135.  
  5136. struct GPFDAT_BITS { // bits description
  5137. Uint16 GPIOF0:1; // 0
  5138. Uint16 GPIOF1:1; // 1
  5139. Uint16 GPIOF2:1; // 2
  5140. Uint16 GPIOF3:1; // 3
  5141. Uint16 GPIOF4:1; // 4
  5142. Uint16 GPIOF5:1; // 5
  5143. Uint16 GPIOF6:1; // 6
  5144. Uint16 GPIOF7:1; // 7
  5145. Uint16 GPIOF8:1; // 8
  5146. Uint16 GPIOF9:1; // 9
  5147. Uint16 GPIOF10:1; // 10
  5148. Uint16 GPIOF11:1; // 11
  5149. Uint16 GPIOF12:1; // 12
  5150. Uint16 GPIOF13:1; // 13
  5151. Uint16 GPIOF14:1; // 14
  5152. Uint16 GPIOF15:1; // 15
  5153.  
  5154. };
  5155.  
  5156. union GPFDAT_REG {
  5157. Uint16 all;
  5158. struct GPFDAT_BITS bit;
  5159. };
  5160.  
  5161.  
  5162. //---------------------------------------------------
  5163. // GPIO F data set register bit definitions
  5164. //
  5165. //
  5166.  
  5167. struct GPFSET_BITS { // bits description
  5168. Uint16 GPIOF0:1; // 0
  5169. Uint16 GPIOF1:1; // 1
  5170. Uint16 GPIOF2:1; // 2
  5171. Uint16 GPIOF3:1; // 3
  5172. Uint16 GPIOF4:1; // 4
  5173. Uint16 GPIOF5:1; // 5
  5174. Uint16 GPIOF6:1; // 6
  5175. Uint16 GPIOF7:1; // 7
  5176. Uint16 GPIOF8:1; // 8
  5177. Uint16 GPIOF9:1; // 9
  5178. Uint16 GPIOF10:1; // 10
  5179. Uint16 GPIOF11:1; // 11
  5180. Uint16 GPIOF12:1; // 12
  5181. Uint16 GPIOF13:1; // 13
  5182. Uint16 GPIOF14:1; // 14
  5183. Uint16 GPIOF15:1; // 15
  5184.  
  5185. };
  5186.  
  5187. union GPFSET_REG {
  5188. Uint16 all;
  5189. struct GPFSET_BITS bit;
  5190. };
  5191.  
  5192.  
  5193. //---------------------------------------------------
  5194. // GPIO F data clear register bit definitions
  5195. //
  5196. //
  5197.  
  5198. struct GPFCLEAR_BITS { // bits description
  5199. Uint16 GPIOF0:1; // 0
  5200. Uint16 GPIOF1:1; // 1
  5201. Uint16 GPIOF2:1; // 2
  5202. Uint16 GPIOF3:1; // 3
  5203. Uint16 GPIOF4:1; // 4
  5204. Uint16 GPIOF5:1; // 5
  5205. Uint16 GPIOF6:1; // 6
  5206. Uint16 GPIOF7:1; // 7
  5207. Uint16 GPIOF8:1; // 8
  5208. Uint16 GPIOF9:1; // 9
  5209. Uint16 GPIOF10:1; // 10
  5210. Uint16 GPIOF11:1; // 11
  5211. Uint16 GPIOF12:1; // 12
  5212. Uint16 GPIOF13:1; // 13
  5213. Uint16 GPIOF14:1; // 14
  5214. Uint16 GPIOF15:1; // 15
  5215.  
  5216. };
  5217.  
  5218. union GPFCLEAR_REG {
  5219. Uint16 all;
  5220. struct GPFCLEAR_BITS bit;
  5221. };
  5222.  
  5223.  
  5224. //---------------------------------------------------
  5225. // GPIO F data toggle register bit definitions
  5226. //
  5227. //
  5228.  
  5229. struct GPFTOGGLE_BITS { // bits description
  5230. Uint16 GPIOF0:1; // 0
  5231. Uint16 GPIOF1:1; // 1
  5232. Uint16 GPIOF2:1; // 2
  5233. Uint16 GPIOF3:1; // 3
  5234. Uint16 GPIOF4:1; // 4
  5235. Uint16 GPIOF5:1; // 5
  5236. Uint16 GPIOF6:1; // 6
  5237. Uint16 GPIOF7:1; // 7
  5238. Uint16 GPIOF8:1; // 8
  5239. Uint16 GPIOF9:1; // 9
  5240. Uint16 GPIOF10:1; // 10
  5241. Uint16 GPIOF11:1; // 11
  5242. Uint16 GPIOF12:1; // 12
  5243. Uint16 GPIOF13:1; // 13
  5244. Uint16 GPIOF14:1; // 14
  5245. Uint16 GPIOF15:1; // 15
  5246.  
  5247. };
  5248.  
  5249. union GPFTOGGLE_REG {
  5250. Uint16 all;
  5251. struct GPFTOGGLE_BITS bit;
  5252. };
  5253.  
  5254. //----------------------------------------------
  5255. // GPIO G mux control register bit definitions
  5256. //
  5257. //
  5258. struct GPGMUX_BITS { // bits description
  5259. Uint16 rsvd1:4; // 3:0
  5260. Uint16 SCITXDB_GPIOG4:1; // 4
  5261. Uint16 SCIRXDB_GPIOG5:1; // 5
  5262. Uint16 rsvd2:10; // 15:6
  5263.  
  5264. };
  5265.  
  5266.  
  5267. /* Allow access to the bit fields or entire register */
  5268. union GPGMUX_REG {
  5269. Uint16 all;
  5270. struct GPGMUX_BITS bit;
  5271. };
  5272.  
  5273. //---------------------------------------------------
  5274. // GPIO G Direction control register bit definitions
  5275. //
  5276. //
  5277.  
  5278. struct GPGDIR_BITS { // bits description
  5279. Uint16 rsvd1:4; // 3:0
  5280. Uint16 GPIOG4:1; // 4
  5281. Uint16 GPIOG5:1; // 5
  5282. Uint16 rsvd2:10; // 15:6
  5283.  
  5284. };
  5285.  
  5286. union GPGDIR_REG {
  5287. Uint16 all;
  5288. struct GPGDIR_BITS bit;
  5289. };
  5290.  
  5291. //---------------------------------------------------
  5292. // GPIO G data register bit definitions
  5293. //
  5294. //
  5295.  
  5296. struct GPGDAT_BITS { // bits description
  5297. Uint16 rsvd1:4; // 3:0
  5298. Uint16 GPIOG4:1; // 4
  5299. Uint16 GPIOG5:1; // 5
  5300. Uint16 rsvd2:10; // 15:6
  5301.  
  5302. };
  5303.  
  5304. union GPGDAT_REG {
  5305. Uint16 all;
  5306. struct GPGDAT_BITS bit;
  5307. };
  5308.  
  5309.  
  5310. //---------------------------------------------------
  5311. // GPIO G data set register bit definitions
  5312. //
  5313. //
  5314.  
  5315. struct GPGSET_BITS { // bits description
  5316. Uint16 rsvd1:4; // 3:0
  5317. Uint16 GPIOG4:1; // 4
  5318. Uint16 GPIOG5:1; // 5
  5319. Uint16 rsvd2:10; // 15:6
  5320.  
  5321. };
  5322.  
  5323. union GPGSET_REG {
  5324. Uint16 all;
  5325. struct GPGSET_BITS bit;
  5326. };
  5327.  
  5328.  
  5329. //---------------------------------------------------
  5330. // GPIO G data clear register bit definitions
  5331. //
  5332. //
  5333.  
  5334. struct GPGCLEAR_BITS { // bits description
  5335. Uint16 rsvd1:4; // 3:0
  5336. Uint16 GPIOG4:1; // 4
  5337. Uint16 GPIOG5:1; // 5
  5338. Uint16 rsvd2:10; // 15:6
  5339.  
  5340. };
  5341.  
  5342. union GPGCLEAR_REG {
  5343. Uint16 all;
  5344. struct GPGCLEAR_BITS bit;
  5345. };
  5346.  
  5347.  
  5348. //---------------------------------------------------
  5349. // GPIO G data toggle register bit definitions
  5350. //
  5351. //
  5352.  
  5353. struct GPGTOGGLE_BITS { // bits description
  5354. Uint16 rsvd1:4; // 3:0
  5355. Uint16 GPIOG4:1; // 4
  5356. Uint16 GPIOG5:1; // 5
  5357. Uint16 rsvd2:10; // 15:6
  5358.  
  5359. };
  5360.  
  5361. union GPGTOGGLE_REG {
  5362. Uint16 all;
  5363. struct GPGTOGGLE_BITS bit;
  5364. };
  5365.  
  5366.  
  5367. struct GPIO_MUX_REGS {
  5368. union GPAMUX_REG GPAMUX;
  5369. union GPADIR_REG GPADIR;
  5370. union GPAQUAL_REG GPAQUAL;
  5371. Uint16 rsvd1;
  5372. union GPBMUX_REG GPBMUX;
  5373. union GPBDIR_REG GPBDIR;
  5374. union GPBQUAL_REG GPBQUAL;
  5375. Uint16 rsvd2[5];
  5376. union GPDMUX_REG GPDMUX;
  5377. union GPDDIR_REG GPDDIR;
  5378. union GPDQUAL_REG GPDQUAL;
  5379. Uint16 rsvd3;
  5380. union GPEMUX_REG GPEMUX;
  5381. union GPEDIR_REG GPEDIR;
  5382. union GPEQUAL_REG GPEQUAL;
  5383. Uint16 rsvd4;
  5384. union GPFMUX_REG GPFMUX;
  5385. union GPFDIR_REG GPFDIR;
  5386. Uint16 rsvd5[2];
  5387. union GPGMUX_REG GPGMUX;
  5388. union GPGDIR_REG GPGDIR;
  5389. Uint16 rsvd6[6];
  5390. };
  5391.  
  5392. struct GPIO_DATA_REGS {
  5393. union GPADAT_REG GPADAT;
  5394. union GPASET_REG GPASET;
  5395. union GPACLEAR_REG GPACLEAR;
  5396. union GPATOGGLE_REG GPATOGGLE;
  5397. union GPBDAT_REG GPBDAT;
  5398. union GPBSET_REG GPBSET;
  5399. union GPBCLEAR_REG GPBCLEAR;
  5400. union GPBTOGGLE_REG GPBTOGGLE;
  5401. Uint16 rsvd1[4];
  5402. union GPDDAT_REG GPDDAT;
  5403. union GPDSET_REG GPDSET;
  5404. union GPDCLEAR_REG GPDCLEAR;
  5405. union GPDTOGGLE_REG GPDTOGGLE;
  5406. union GPEDAT_REG GPEDAT;
  5407. union GPESET_REG GPESET;
  5408. union GPECLEAR_REG GPECLEAR;
  5409. union GPETOGGLE_REG GPETOGGLE;
  5410. union GPFDAT_REG GPFDAT;
  5411. union GPFSET_REG GPFSET;
  5412. union GPFCLEAR_REG GPFCLEAR;
  5413. union GPFTOGGLE_REG GPFTOGGLE;
  5414. union GPGDAT_REG GPGDAT;
  5415. union GPGSET_REG GPGSET;
  5416. union GPGCLEAR_REG GPGCLEAR;
  5417. union GPGTOGGLE_REG GPGTOGGLE;
  5418. Uint16 rsvd2[4];
  5419. };
  5420.  
  5421.  
  5422. //---------------------------------------------------------------------------
  5423. // GPI/O External References & Function Declarations:
  5424. //
  5425. extern volatile struct GPIO_MUX_REGS GpioMuxRegs;
  5426. extern volatile struct GPIO_DATA_REGS GpioDataRegs;
  5427.  
  5428.  
  5429.  
  5430. //===========================================================================
  5431. // No more.
  5432. //===========================================================================
  5433. //
  5434. // TMDX ALPHA RELEASE
  5435. // Intended for product evaluation purposes
  5436. //
  5437. //###########################################################################
  5438. //
  5439. // FILE: DSP28_Ev.h
  5440. //
  5441. // TITLE: DSP28 Device Event Manager Register Definitions.
  5442. //
  5443. //###########################################################################
  5444. //
  5445. // Ver | dd mmm yyyy | Who | Description of changes
  5446. // =====|=============|======|===============================================
  5447. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  5448. // 0.56| 17 May 2002 | L.H. | Removed extra reserved word in EVA EVB reg file
  5449. // 0.57| 27 May 2002 | L.H. | No change
  5450. // 0.58| 29 Jun 2002 | L.H. | Fixed missing bits in GPTCONA
  5451. //###########################################################################
  5452.  
  5453.  
  5454. /* --------------------------------------------------- */
  5455. /* F2810/12 Event Manager (EV) GP Timer Registers */
  5456. /* */
  5457. /* ----------------------------------------------------*/
  5458.  
  5459. /* Overall Timer Control Register */
  5460.  
  5461. struct GPTCONA_BITS {
  5462. Uint16 T1PIN:2; // 1:0 Polarity of GP timer 1 compare
  5463. Uint16 T2PIN:2; // 3:2 Polarity of GP timer 2 compare
  5464. Uint16 T1CMPOE:1; // 4 Timer1 compare output
  5465. Uint16 T2CMPOE:1; // 5 Timer2 compare output
  5466. Uint16 TCOMPOE:1; // 6 Compare output enable
  5467. Uint16 T1TOADC:2; // 8:7 Start ADC with timer 1 event
  5468. Uint16 T2TOADC:2; // 10:9 Start ADC with timer 2 event
  5469. Uint16 rsvd2:2; // 12:11 reserved
  5470. Uint16 T1STAT:1; // 13 GP Timer 1 status (read only)
  5471. Uint16 T2STAT:1; // 14 GP Timer 2 status (read only)
  5472. Uint16 rsvd:1; // 15 reserved
  5473. };
  5474.  
  5475. /* Allow access to the bit fields or entire register */
  5476. union GPTCONA_REG {
  5477. Uint16 all;
  5478. struct GPTCONA_BITS bit;
  5479. };
  5480.  
  5481. struct GPTCONB_BITS {
  5482. Uint16 T3PIN:2; // 1:0 Polarity of GP timer 3 compare
  5483. Uint16 T4PIN:2; // 3:2 Polarity of GP timer 4 compare
  5484. Uint16 T3CMPOE:1; // 4 Timer3 compare output
  5485. Uint16 T4CMPOE:1; // 5 Timer4 compare output
  5486. Uint16 TCOMPOE:1; // 6 Compare output enable
  5487. Uint16 T3TOADC:2; // 8:7 Start ADC with timer 3 event
  5488. Uint16 T4TOADC:2; // 10:9 Start ADC with timer 4 event
  5489. Uint16 T1CTRIP:1; // 11 Timer1 trip enable
  5490. Uint16 T2CTRIP:1; // 12 Timer2 trip enable
  5491. Uint16 T3STAT:1; // 13 GP Timer 3 status (read only)
  5492. Uint16 T4STAT:1; // 14 GP Timer 4 status (read only)
  5493. Uint16 rsvd2:1; // 15 reserved
  5494. };
  5495.  
  5496. /* Allow access to the bit fields or entire register */
  5497. union GPTCONB_REG {
  5498. Uint16 all;
  5499. struct GPTCONB_BITS bit;
  5500. };
  5501.  
  5502. /* Timer Control Register bit defintions */
  5503. struct TCONA_BITS {
  5504. Uint16 SET1PR:1; // 0 Period register select
  5505. Uint16 TECMPR:1; // 1 Timer compare enable
  5506. Uint16 TCLD10:2; // 3:2 Timer copare register reload
  5507. Uint16 TCLKS10:2; // 5:4 Clock source select
  5508. Uint16 TENABLE:1; // 6 Timer enable
  5509. Uint16 T2SWT1:1; // 7 Start GP timer 2 with GP timer 1's enable
  5510. Uint16 TPS:3; // 10:8 Input clock prescaler
  5511. Uint16 TMODE:2; // 12:11 Count mode selection
  5512. Uint16 rsvd:1; // 13 reserved
  5513. Uint16 FREE:1; // 14 Free emulation control
  5514. Uint16 SOFT:1; // 15 Soft emulation control
  5515. };
  5516.  
  5517. /* Allow access to the bit fields or entire register */
  5518. union TCONA_REG {
  5519. Uint16 all;
  5520. struct TCONA_BITS bit;
  5521. };
  5522.  
  5523. struct TCONB_BITS {
  5524. Uint16 SET3PR:1; // 0 Period register select
  5525. Uint16 TECMPR:1; // 1 Timer compare enable
  5526. Uint16 TCLD10:2; // 3:2 Timer copare register reload
  5527. Uint16 TCLKS10:2; // 5:4 Clock source select
  5528. Uint16 TENABLE:1; // 6 Timer enable
  5529. Uint16 T4SWT3:1; // 7 Start GP timer 2 with GP timer 1's enable
  5530. Uint16 TPS:3; // 10:8 Input clock prescaler
  5531. Uint16 TMODE:2; // 12:11 Count mode selection
  5532. Uint16 rsvd:1; // 13 reserved
  5533. Uint16 FREE:1; // 14 Free emulation control
  5534. Uint16 SOFT:1; // 15 Soft emulation control
  5535. };
  5536.  
  5537. /* Allow access to the bit fields or entire register */
  5538. union TCONB_REG {
  5539. Uint16 all;
  5540. struct TCONB_BITS bit;
  5541. };
  5542.  
  5543.  
  5544. struct EXTCONA_BITS {
  5545. Uint16 INDCOE:1; // 0 Independant compare output
  5546. Uint16 QEPIQEL:1; // 1 QEP/CAP3 Index Qual Mode
  5547. Uint16 QEPIE:1; // 2 QEP index enable
  5548. Uint16 EVSOCE:1; // 3 Ev start of conversion output enable
  5549. Uint16 rsvd:12; // 15:4 reserved
  5550. };
  5551.  
  5552. /* Allow access to the bit fields or entire register */
  5553. union EXTCONA_REG {
  5554. Uint16 all;
  5555. struct EXTCONA_BITS bit;
  5556. };
  5557.  
  5558.  
  5559. struct EXTCONB_BITS {
  5560. Uint16 INDCOE:1; // 0 Independant compare output
  5561. Uint16 QEPIQEL:1; // 1 QEP/CAP3 Index Qual Mode
  5562. Uint16 QEPIE:1; // 2 QEP index enable
  5563. Uint16 EVSOCE:1; // 3 Ev start of conversion output enable
  5564. Uint16 rsvd:12; // 15:4 reserved
  5565. };
  5566.  
  5567. /* Allow access to the bit fields or entire register */
  5568. union EXTCONB_REG {
  5569. Uint16 all;
  5570. struct EXTCONA_BITS bit;
  5571. };
  5572.  
  5573.  
  5574.  
  5575. /* Compare Control Register */
  5576. struct COMCONA_BITS {
  5577. Uint16 rsvd:8; // 7:0 reserved
  5578. Uint16 PDPINTASTATUS:1;// 8 Current status of the PDPINTA pin
  5579. Uint16 FCOMPOE:1; // 9 Compare output enable
  5580. Uint16 ACTRLD:2; // 11:10 Action control register reload
  5581. Uint16 SVENABLE:1; // 12 Space vector PWM Mode enable
  5582. Uint16 CLD:2; // 14:13 Compare register reload condition
  5583. Uint16 CENABLE:1; // 15 Compare enable
  5584. };
  5585.  
  5586. /* Allow access to the bit fields or entire register */
  5587. union COMCONA_REG {
  5588. Uint16 all;
  5589. struct COMCONA_BITS bit;
  5590. };
  5591.  
  5592. struct COMCONB_BITS {
  5593. Uint16 rsvd:8; // 7:0 reserved
  5594. Uint16 PDPINTBSTATUS:1;// 8 Current status of the PDPINTB pin
  5595. Uint16 FCOMPOE:1; // 9 Compare output enable
  5596. Uint16 ACTRLD:2; // 11:10 Action control register reload
  5597. Uint16 SVENABLE:1; // 12 Space vector PWM Mode enable
  5598. Uint16 CLD:2; // 14:13 Compare register reload condition
  5599. Uint16 CENABLE:1; // 15 Compare enable
  5600. };
  5601.  
  5602. /* Allow access to the bit fields or entire register */
  5603. union COMCONB_REG {
  5604. Uint16 all;
  5605. struct COMCONB_BITS bit;
  5606. };
  5607.  
  5608. /* Compare Action Control Register bit definitions */
  5609.  
  5610. struct ACTRA_BITS {
  5611. Uint16 CMP1ACT:2; // 1:0 Action on compare output pin 1 CMP1
  5612. Uint16 CMP2ACT:2; // 3:2 Action on compare output pin 2 CMP2
  5613. Uint16 CMP3ACT:2; // 5:4 Action on compare output pin 3 CMP3
  5614. Uint16 CMP4ACT:2; // 7:6 Action on compare output pin 4 CMP4
  5615. Uint16 CMP5ACT:2; // 9:8 Action on compare output pin 5 CMP5
  5616. Uint16 CMP6ACT:2; // 11:10 Action on compare output pin 6 CMP6
  5617. Uint16 D:3; // 14:12 Basic vector bits
  5618. Uint16 SVRDIR:1; // 15 Space vecor PWM rotation dir
  5619. };
  5620.  
  5621. /* Allow access to the bit fields or entire register */
  5622. union ACTRA_REG {
  5623. Uint16 all;
  5624. struct ACTRA_BITS bit;
  5625. };
  5626.  
  5627. struct ACTRB_BITS {
  5628. Uint16 CMP7ACT:2; // 1:0 Action on compare output pin 7 CMP7
  5629. Uint16 CMP8ACT:2; // 3:2 Action on compare output pin 8 CMP8
  5630. Uint16 CMP9ACT:2; // 5:4 Action on compare output pin 9 CMP9
  5631. Uint16 CMP10ACT:2; // 7:6 Action on compare output pin 10 CMP10
  5632. Uint16 CMP11ACT:2; // 9:8 Action on compare output pin 11 CMP11
  5633. Uint16 CMP12ACT:2; // 11:10 Action on compare output pin 12 CMP12
  5634. Uint16 D:3; // 14:12 Basic vector bits
  5635. Uint16 SVRDIR:1; // 15 Space vecor PWM rotation dir
  5636. };
  5637.  
  5638. /* Allow access to the bit fields or entire register */
  5639. union ACTRB_REG {
  5640. Uint16 all;
  5641. struct ACTRB_BITS bit;
  5642. };
  5643.  
  5644. /* Dead-Band Timer Control register bit definitions */
  5645. struct DBTCON_BITS {
  5646. Uint16 rsvd1:2; // 1:0 reserved
  5647. Uint16 DBTPS:3; // 4:2 Dead-Band timer prescaler
  5648. Uint16 EDBT1:1; // 5 Dead-Band timer 1 enable
  5649. Uint16 EDBT2:1; // 6 Dead-Band timer 2 enable
  5650. Uint16 EDBT3:1; // 7 Dead-Band timer 3 enable
  5651. Uint16 DBT:4; // 11:8 Dead-Band timer period
  5652. Uint16 rsvd2:4; // 15:12 reserved
  5653. };
  5654.  
  5655. /* Allow access to the bit fields or entire register */
  5656. union DBTCON_REG {
  5657. Uint16 all;
  5658. struct DBTCON_BITS bit;
  5659. };
  5660.  
  5661.  
  5662. /* Capture Control register bit definitions */
  5663. struct CAPCONA_BITS {
  5664. Uint16 rsvd1:2; // 1:0 reserved
  5665. Uint16 CAP3EDGE:2; // 3:2 Edge Detection for Unit 3
  5666. Uint16 CAP2EDGE:2; // 5:4 Edge Detection for Unit 2
  5667. Uint16 CAP1EDGE:2; // 7:6 Edge Detection for Unit 1
  5668. Uint16 CAP3TOADC:1; // 8 Unit 3 starts the ADC
  5669. Uint16 CAP12TSEL:1; // 9 GP Timer selection for Units 1 and 2
  5670. Uint16 CAP3TSEL:1; // 10 GP Timer selection for Unit 3
  5671. Uint16 rsvd2:1; // 11 reserved
  5672. Uint16 CAP3EN:1; // 12 Capture Unit 3 control
  5673. Uint16 CAPQEPN:2; // 14:13 Capture Unit 1 and 2 control
  5674. Uint16 CAPRES:1; // 15 Capture reset (always reads 0)
  5675. };
  5676.  
  5677. /* Allow access to the bit fields or entire register */
  5678. union CAPCONA_REG {
  5679. Uint16 all;
  5680. struct CAPCONA_BITS bit;
  5681. };
  5682.  
  5683.  
  5684. /* Control register bit definitions */
  5685. struct CAPCONB_BITS {
  5686. Uint16 rsvd1:2; // 1:0 reserved
  5687. Uint16 CAP6EDGE:2; // 3:2 Edge Detection for Unit 6
  5688. Uint16 CAP5EDGE:2; // 5:4 Edge Detection for Unit 5
  5689. Uint16 CAP4EDGE:2; // 7:6 Edge Detection for Unit 4
  5690. Uint16 CAP6TOADC:1; // 8 Unit 6 starts the ADC
  5691. Uint16 CAP45TSEL:1; // 9 GP Timer selection for Units 4 and 5
  5692. Uint16 CAP6TSEL:1; // 10 GP Timer selection for Unit 6
  5693. Uint16 rsvd2:1; // 11 reserved
  5694. Uint16 CAP6EN:1; // 12 Capture Unit 6 control
  5695. Uint16 CAPQEPN:2; // 14:13 Capture Unit 4 and 5 control
  5696. Uint16 CAPRES:1; // 15 Capture reset (always reads 0)
  5697. };
  5698.  
  5699. /* Allow access to the bit fields or entire register */
  5700. union CAPCONB_REG {
  5701. Uint16 all;
  5702. struct CAPCONB_BITS bit;
  5703. };
  5704.  
  5705. /* Capture FIFO Status Register bit definitions */
  5706. struct CAPFIFOA_BITS {
  5707. Uint16 rsvd1:8; // 7:0 reserved
  5708. Uint16 CAP1FIFO:2; // 9:8 CAP1 FIFO status
  5709. Uint16 CAP2FIFO:2; // 11:10 CAP2 FIFO status
  5710. Uint16 CAP3FIFO:2; // 13:12 CAP2 FIFO status
  5711. Uint16 rsvd2:2; // 15:14 reserved
  5712. };
  5713.  
  5714. /* Allow access to the bit fields or entire register */
  5715. union CAPFIFOA_REG {
  5716. Uint16 all;
  5717. struct CAPFIFOA_BITS bit;
  5718. };
  5719.  
  5720. /* Capture FIFO Status Register bit definitions */
  5721. struct CAPFIFOB_BITS {
  5722. Uint16 rsvd1:8; // 7:0 reserved
  5723. Uint16 CAP4FIFO:2; // 9:8 CAP4 FIFO status
  5724. Uint16 CAP5FIFO:2; // 11:10 CAP5 FIFO status
  5725. Uint16 CAP6FIFO:2; // 13:12 CAP6 FIFO status
  5726. Uint16 rsvd2:2; // 15:14 reserved
  5727. };
  5728.  
  5729. /* Allow access to the bit fields or entire register */
  5730. union CAPFIFOB_REG {
  5731. Uint16 all;
  5732. struct CAPFIFOB_BITS bit;
  5733. };
  5734.  
  5735. /* Interrupt Mask Register bit definitions */
  5736. struct EVAIMRA_BITS {
  5737. Uint16 PDPINTA:1; // 0 Enable PDPINTA
  5738. Uint16 CMP1INT:1; // 1 Enable
  5739. Uint16 CMP2INT:1; // 2 Enable
  5740. Uint16 CMP3INT:1; // 3 Enable
  5741. Uint16 rsvd1:3; // 6:4 reserved
  5742. Uint16 T1PINT:1; // 7 Enable
  5743. Uint16 T1CINT:1; // 8 Enable
  5744. Uint16 T1UFINT:1; // 9 Enable
  5745. Uint16 T1OFINT:1; // 10 Enable
  5746. Uint16 rsvd2:5; // 15:11 reserved
  5747. };
  5748.  
  5749. /* Allow access to the bit fields or entire register */
  5750. union EVAIMRA_REG {
  5751. Uint16 all;
  5752. struct EVAIMRA_BITS bit;
  5753. };
  5754.  
  5755. /* Interrupt Mask Register bit definitions */
  5756. struct EVBIMRA_BITS {
  5757. Uint16 PDPINTB:1; // 0 Enable PDPINTB
  5758. Uint16 CMP4INT:1; // 1 Enable
  5759. Uint16 CMP5INT:1; // 2 Enable
  5760. Uint16 CMP6INT:1; // 3 Enable
  5761. Uint16 rsvd1:3; // 6:4 reserved
  5762. Uint16 T3PINT:1; // 7 Enable
  5763. Uint16 T3CINT:1; // 8 Enable
  5764. Uint16 T3UFINT:1; // 9 Enable
  5765. Uint16 T3OFINT:1; // 10 Enable
  5766. Uint16 rsvd2:5; // 15:11 reserved
  5767. };
  5768.  
  5769. /* Allow access to the bit fields or entire register */
  5770. union EVBIMRA_REG {
  5771. Uint16 all;
  5772. struct EVBIMRA_BITS bit;
  5773. };
  5774.  
  5775. struct EVAIMRB_BITS {
  5776. Uint16 T2PINT:1; // 0 Enable
  5777. Uint16 T2CINT:1; // 1 Enable
  5778. Uint16 T2UFINT:1; // 2 Enable
  5779. Uint16 T2OFINT:1; // 3 Enable
  5780. Uint16 rsvd1:12; // 15:4 reserved
  5781. };
  5782.  
  5783. /* Allow access to the bit fields or entire register */
  5784. union EVAIMRB_REG {
  5785. Uint16 all;
  5786. struct EVAIMRB_BITS bit;
  5787. };
  5788.  
  5789. struct EVBIMRB_BITS {
  5790. Uint16 T4PINT:1; // 0 Enable
  5791. Uint16 T4CINT:1; // 1 Enable
  5792. Uint16 T4UFINT:1; // 2 Enable
  5793. Uint16 T4OFINT:1; // 3 Enable
  5794. Uint16 rsvd1:12; // 15:4 reserved
  5795. };
  5796.  
  5797. /* Allow access to the bit fields or entire register */
  5798. union EVBIMRB_REG {
  5799. Uint16 all;
  5800. struct EVBIMRB_BITS bit;
  5801. };
  5802.  
  5803. struct EVAIMRC_BITS {
  5804. Uint16 CAP1INT:1; // 0 Enable
  5805. Uint16 CAP2INT:1; // 1 Enable
  5806. Uint16 CAP3INT:1; // 2 Enable
  5807. Uint16 rsvd1:13; // 15:3 reserved
  5808. };
  5809.  
  5810. /* Allow access to the bit fields or entire register */
  5811. union EVAIMRC_REG {
  5812. Uint16 all;
  5813. struct EVAIMRC_BITS bit;
  5814. };
  5815.  
  5816. struct EVBIMRC_BITS {
  5817. Uint16 CAP4INT:1; // 0 Enable
  5818. Uint16 CAP5INT:1; // 1 Enable
  5819. Uint16 CAP6INT:1; // 2 Enable
  5820. Uint16 rsvd1:13; // 15:3 reserved
  5821. };
  5822.  
  5823. /* Allow access to the bit fields or entire register */
  5824. union EVBIMRC_REG {
  5825. Uint16 all;
  5826. struct EVBIMRC_BITS bit;
  5827. };
  5828.  
  5829. /* Interrupt Flag Register bit definitions */
  5830. struct EVAIFRA_BITS {
  5831. Uint16 PDPINTA:1; // 0 Flag PDPINTA
  5832. Uint16 CMP1INT:1; // 1 Flag
  5833. Uint16 CMP2INT:1; // 2 Flag
  5834. Uint16 CMP3INT:1; // 3 Flag
  5835. Uint16 rsvd1:3; // 6:4 reserved
  5836. Uint16 T1PINT:1; // 7 Flag
  5837. Uint16 T1CINT:1; // 8 Flag
  5838. Uint16 T1UFINT:1; // 9 Flag
  5839. Uint16 T1OFINT:1; // 10 Flag
  5840. Uint16 rsvd2:5; // 15:11 reserved
  5841. };
  5842.  
  5843. /* Allow access to the bit fields or entire register */
  5844. union EVAIFRA_REG {
  5845. Uint16 all;
  5846. struct EVAIMRA_BITS bit;
  5847. };
  5848.  
  5849. /* Interrupt Mask Register bit definitions */
  5850. struct EVBIFRA_BITS {
  5851. Uint16 PDPINTB:1; // 0 Flag PDPINTB
  5852. Uint16 CMP4INT:1; // 1 Flag
  5853. Uint16 CMP5INT:1; // 2 Flag
  5854. Uint16 CMP6INT:1; // 3 Flag
  5855. Uint16 rsvd1:3; // 6:4 reserved
  5856. Uint16 T3PINT:1; // 7 Flag
  5857. Uint16 T3CINT:1; // 8 Flag
  5858. Uint16 T3UFINT:1; // 9 Flag
  5859. Uint16 T3OFINT:1; // 10 Flag
  5860. Uint16 rsvd2:5; // 15:11 reserved
  5861. };
  5862.  
  5863. /* Allow access to the bit fields or entire register */
  5864. union EVBIFRA_REG {
  5865. Uint16 all;
  5866. struct EVBIFRA_BITS bit;
  5867. };
  5868.  
  5869. struct EVAIFRB_BITS {
  5870. Uint16 T2PINT:1; // 0 Flag
  5871. Uint16 T2CINT:1; // 1 Flag
  5872. Uint16 T2UFINT:1; // 2 Flag
  5873. Uint16 T2OFINT:1; // 3 Flag
  5874. Uint16 rsvd1:12; // 15:4 reserved
  5875. };
  5876.  
  5877. /* Allow access to the bit fields or entire register */
  5878. union EVAIFRB_REG {
  5879. Uint16 all;
  5880. struct EVAIFRB_BITS bit;
  5881. };
  5882.  
  5883. struct EVBIFRB_BITS {
  5884. Uint16 T4PINT:1; // 0 Flag
  5885. Uint16 T4CINT:1; // 1 Flag
  5886. Uint16 T4UFINT:1; // 2 Flag
  5887. Uint16 T4OFINT:1; // 3 Flag
  5888. Uint16 rsvd1:12; // 15:4 reserved
  5889. };
  5890.  
  5891. /* Allow access to the bit fields or entire register */
  5892. union EVBIFRB_REG {
  5893. Uint16 all;
  5894. struct EVBIFRB_BITS bit;
  5895. };
  5896.  
  5897. struct EVAIFRC_BITS {
  5898. Uint16 CAP1INT:1; // 0 Flag
  5899. Uint16 CAP2INT:1; // 1 Flag
  5900. Uint16 CAP3INT:1; // 2 Flag
  5901. Uint16 rsvd1:13; // 15:3 reserved
  5902. };
  5903.  
  5904. /* Allow access to the bit fields or entire register */
  5905. union EVAIFRC_REG {
  5906. Uint16 all;
  5907. struct EVAIFRC_BITS bit;
  5908. };
  5909.  
  5910. struct EVBIFRC_BITS {
  5911. Uint16 CAP4INT:1; // 0 Flag
  5912. Uint16 CAP5INT:1; // 1 Flag
  5913. Uint16 CAP6INT:1; // 2 Flag
  5914. Uint16 rsvd1:13; // 15:3 reserved
  5915. };
  5916.  
  5917. /* Allow access to the bit fields or entire register */
  5918. union EVBIFRC_REG {
  5919. Uint16 all;
  5920. struct EVBIFRC_BITS bit;
  5921. };
  5922.  
  5923. /* EVA Register File */
  5924.  
  5925. struct EVA_REGS {
  5926. union GPTCONA_REG GPTCONA; //0x7400
  5927. Uint16 T1CNT; //0x7401
  5928. Uint16 T1CMPR; //0x7402
  5929. Uint16 T1PR; //0x7403
  5930. union TCONA_REG T1CON; //0x7404
  5931. Uint16 T2CNT; //0x7405
  5932. Uint16 T2CMPR; //0x7406
  5933. Uint16 T2PR; //0x7407
  5934. union TCONA_REG T2CON; //0x7408
  5935. union EXTCONA_REG EXTCON; //0x7409
  5936. Uint16 rsvd1[7]; //0x740A-10
  5937. union COMCONA_REG COMCONA; //0x7411
  5938. Uint16 rsvd2; //0x7412
  5939. union ACTRA_REG ACTRA; //0x7413
  5940. Uint16 rsvd3; //0x7414
  5941. union DBTCON_REG DBTCONA; //0x7415
  5942. Uint16 rsvd4; //0x7416
  5943. Uint16 CMPR1; //0x7417
  5944. Uint16 CMPR2; //0x7418
  5945. Uint16 CMPR3; //0x7419
  5946. Uint16 rsvd5[6]; //0x741A-F
  5947. union CAPCONA_REG CAPCON; //0x7420
  5948. Uint16 rsvd6; //0x7421
  5949. union CAPFIFOA_REG CAPFIFO; //0x7422
  5950. Uint16 CAP1FIFO; //0x7423
  5951. Uint16 CAP2FIFO; //0x7424
  5952. Uint16 CAP3FIFO; //0x7425
  5953. Uint16 rsvd7; //0x7426
  5954. Uint16 CAP1FBOT; //0x7427
  5955. Uint16 CAP2FBOT; //0x7428
  5956. Uint16 CAP3FBOT; //0x7429
  5957. Uint16 rsvd8[2]; //0x742A-B
  5958. union EVAIMRA_REG EVAIMRA; //0x742C
  5959. union EVAIMRB_REG EVAIMRB; //0x742D
  5960. union EVAIMRC_REG EVAIMRC; //0x742E
  5961. union EVAIFRA_REG EVAIFRA; //0x742F
  5962. union EVAIFRB_REG EVAIFRB; //0x7430
  5963. union EVAIFRC_REG EVAIFRC; //0x7431
  5964. };
  5965.  
  5966.  
  5967. /* EVB Register File */
  5968.  
  5969. struct EVB_REGS {
  5970. union GPTCONB_REG GPTCONB; //0x7500
  5971. Uint16 T3CNT; //0x7501
  5972. Uint16 T3CMPR; //0x7502
  5973. Uint16 T3PR; //0x7503
  5974. union TCONB_REG T3CON; //0x7504
  5975. Uint16 T4CNT; //0x7505
  5976. Uint16 T4CMPR; //0x7506
  5977. Uint16 T4PR; //0x7507
  5978. union TCONB_REG T4CON; //0x7508
  5979. union EXTCONB_REG EXTCONB; //0x7509
  5980. Uint16 rsvd1[7]; //0x750A-10
  5981. union COMCONB_REG COMCONB; //0x7511
  5982. Uint16 rsvd2; //0x7512
  5983. union ACTRB_REG ACTRB; //0x7513
  5984. Uint16 rsvd3; //0x7514
  5985. union DBTCON_REG DBTCONB; //0x7515
  5986. Uint16 rsvd4; //0x7516
  5987. Uint16 CMPR4; //0x7517
  5988. Uint16 CMPR5; //0x7518
  5989. Uint16 CMPR6; //0x7519
  5990. Uint16 rsvd5[6]; //0x751A-F
  5991. union CAPCONB_REG CAPCONB; //0x7520
  5992. Uint16 rsvd6; //0x7521
  5993. union CAPFIFOB_REG CAPFIFOB; //0x7522
  5994. Uint16 CAP4FIFO; //0x7523
  5995. Uint16 CAP5FIFO; //0x7524
  5996. Uint16 CAP6FIFO; //0x7525
  5997. Uint16 rsvd7; //0x7526
  5998. Uint16 CAP4FBOT; //0x7527
  5999. Uint16 CAP5FBOT; //0x7528
  6000. Uint16 CAP6FBOT; //0x7529
  6001. Uint16 rsvd8[2]; //0x752A-B
  6002. union EVBIMRA_REG EVBIMRA; //0x752C
  6003. union EVBIMRB_REG EVBIMRB; //0x752D
  6004. union EVBIMRC_REG EVBIMRC; //0x752E
  6005. union EVBIFRA_REG EVBIFRA; //0x752F
  6006. union EVBIFRB_REG EVBIFRB; //0x7530
  6007. union EVBIFRC_REG EVBIFRC; //0x7531
  6008. };
  6009.  
  6010.  
  6011.  
  6012. //---------------------------------------------------------------------------
  6013. // Function prototypes and external definitions:
  6014. //
  6015.  
  6016. extern volatile struct EVA_REGS EvaRegs;
  6017. extern volatile struct EVB_REGS EvbRegs;
  6018.  
  6019.  
  6020.  
  6021. //===========================================================================
  6022. // No more.
  6023. //===========================================================================
  6024. //
  6025. // TMDX ALPHA RELEASE
  6026. // Intended for product evaluation purposes
  6027. //
  6028. //###########################################################################
  6029. //
  6030. // FILE: DSP28_Adc.h
  6031. //
  6032. // TITLE: DSP28 Device ADC Register Definitions.
  6033. //
  6034. //###########################################################################
  6035. //
  6036. // Ver | dd mmm yyyy | Who | Description of changes
  6037. // =====|=============|======|===============================================
  6038. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  6039. // 0.56| 20 May 2002 | L.H. | No change
  6040. // 0.57| 27 May 2002 | L.H. | No change
  6041. // 0.58| 29 Jun 2002 | L.H. | Updated register names to match the datasheet
  6042. //###########################################################################
  6043.  
  6044.  
  6045. //---------------------------------------------------------------------------
  6046. // ADC Individual Register Bit Definitions:
  6047.  
  6048. struct ADCTRL1_BITS { // bits description
  6049. Uint16 rsvd1:4; // 3:0 reserved
  6050. Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
  6051. Uint16 rsvd2:1; // 5 reserved
  6052. Uint16 CONT_RUN:1; // 6 Continuous run
  6053. Uint16 CPS:1; // 7 ADC core clock prescaler
  6054. Uint16 ACQ_PS:4; // 11:8 Acquisition window size
  6055. Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
  6056. Uint16 RESET:1; // 14 ADC reset
  6057. Uint16 rsvd3:1; // 15 reserved
  6058. };
  6059.  
  6060.  
  6061. union ADCTRL1_REG {
  6062. Uint16 all;
  6063. struct ADCTRL1_BITS bit;
  6064. };
  6065.  
  6066.  
  6067. struct ADCTRL2_BITS { // bits description
  6068. Uint16 EVB_SOC_SEQ2:1; // 0 Event manager B SOC mask for SEQ2
  6069. Uint16 rsvd1:1; // 1 reserved
  6070. Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode
  6071. Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable
  6072. Uint16 rsvd2:1; // 4 reserved
  6073. Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2
  6074. Uint16 RST_SEQ2:1; // 6 Reset SEQ2
  6075. Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1
  6076. Uint16 EVA_SOC_SEQ1:1; // 8 Event manager A SOC mask for SEQ1
  6077. Uint16 rsvd3:1; // 9 reserved
  6078. Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode
  6079. Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable
  6080. Uint16 rsvd4:1; // 12 reserved
  6081. Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1
  6082. Uint16 RST_SEQ1:1; // 14 Restart sequencer 1
  6083. Uint16 EVB_SOC_SEQ:1; // 15 EVB SOC enable
  6084. };
  6085.  
  6086.  
  6087. union ADCTRL2_REG {
  6088. Uint16 all;
  6089. struct ADCTRL2_BITS bit;
  6090. };
  6091.  
  6092.  
  6093. struct ADCCASEQSR_BITS { // bits description
  6094. Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state
  6095. Uint16 SEQ2_STATE:3; // 6:2 SEQ2 state
  6096. Uint16 rsvd1:1; // 7 resverved
  6097. Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status
  6098. Uint16 rsvd2:4; // 15:12 reserved
  6099. };
  6100.  
  6101. union ADCCASEQSR_REG {
  6102. Uint16 all;
  6103. struct ADCCASEQSR_BITS bit;
  6104. };
  6105.  
  6106.  
  6107. struct ADCMAXCONV_BITS {
  6108. Uint16 MAX_CONV:7; // 6:0 Max number of conversions
  6109. Uint16 rsvd1:9; // 15:7 reserved
  6110. };
  6111.  
  6112. union ADCMAXCONV_REG {
  6113. Uint16 all;
  6114. struct ADCMAXCONV_BITS bit;
  6115. };
  6116.  
  6117.  
  6118. struct ADCCHSELSEQ1_BITS {
  6119. Uint16 CONV00:4;
  6120. Uint16 CONV01:4;
  6121. Uint16 CONV02:4;
  6122. Uint16 CONV03:4;
  6123. };
  6124.  
  6125. union ADCCHSELSEQ1_REG{
  6126. Uint16 all;
  6127. struct ADCCHSELSEQ1_BITS bit;
  6128. };
  6129.  
  6130. struct ADCCHSELSEQ2_BITS {
  6131. Uint16 CONV04:4;
  6132. Uint16 CONV05:4;
  6133. Uint16 CONV06:4;
  6134. Uint16 CONV07:4;
  6135. };
  6136.  
  6137. union ADCCHSELSEQ2_REG{
  6138. Uint16 all;
  6139. struct ADCCHSELSEQ2_BITS bit;
  6140. };
  6141.  
  6142. struct ADCCHSELSEQ3_BITS {
  6143. Uint16 CONV08:4;
  6144. Uint16 CONV09:4;
  6145. Uint16 CONV10:4;
  6146. Uint16 CONV11:4;
  6147. };
  6148.  
  6149. union ADCCHSELSEQ3_REG{
  6150. Uint16 all;
  6151. struct ADCCHSELSEQ3_BITS bit;
  6152. };
  6153.  
  6154. struct ADCCHSELSEQ4_BITS {
  6155. Uint16 CONV12:4;
  6156. Uint16 CONV13:4;
  6157. Uint16 CONV14:4;
  6158. Uint16 CONV15:4;
  6159. };
  6160.  
  6161. union ADCCHSELSEQ4_REG {
  6162. Uint16 all;
  6163. struct ADCCHSELSEQ4_BITS bit;
  6164. };
  6165.  
  6166. struct ADCTRL3_BITS {
  6167. Uint16 SMODE_SEL:1; // 0 Sampling mode select
  6168. Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider
  6169. Uint16 ADCPWDN:1; // 5 ADC powerdown
  6170. Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down
  6171. Uint16 rsvd1:8; // 15:8 reserved
  6172. };
  6173.  
  6174. union ADCTRL3_REG {
  6175. Uint16 all;
  6176. struct ADCTRL3_BITS bit;
  6177. };
  6178.  
  6179.  
  6180. struct ADCST_BITS {
  6181. Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag
  6182. Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag
  6183. Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status
  6184. Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status
  6185. Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear
  6186. Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear
  6187. Uint16 EOS_BUF1:1; // 6 End of sequence buffer1
  6188. Uint16 EOS_BUF2:1; // 7 End of sequence buffer2
  6189. Uint16 rsvd1:8; // 15:8
  6190. };
  6191.  
  6192.  
  6193. union ADCST_REG {
  6194. Uint16 all;
  6195. struct ADCST_BITS bit;
  6196. };
  6197.  
  6198.  
  6199. struct ADC_REGS {
  6200. union ADCTRL1_REG ADCTRL1; // ADC Control 1
  6201. union ADCTRL2_REG ADCTRL2; // ADC Control 2
  6202. union ADCMAXCONV_REG ADCMAXCONV; // Max conversions
  6203. union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control
  6204. union ADCCHSELSEQ2_REG ADCCHSELSEQ2;
  6205. union ADCCHSELSEQ3_REG ADCCHSELSEQ3;
  6206. union ADCCHSELSEQ4_REG ADCCHSELSEQ4;
  6207. union ADCCASEQSR_REG ADCASEQSR; // Autosequence status register
  6208. Uint16 ADCRESULT0; // Conversion Result Buffer 0 - 15
  6209. Uint16 ADCRESULT1;
  6210. Uint16 ADCRESULT2;
  6211. Uint16 ADCRESULT3;
  6212. Uint16 ADCRESULT4;
  6213. Uint16 ADCRESULT5;
  6214. Uint16 ADCRESULT6;
  6215. Uint16 ADCRESULT7;
  6216. Uint16 ADCRESULT8;
  6217. Uint16 ADCRESULT9;
  6218. Uint16 ADCRESULT10;
  6219. Uint16 ADCRESULT11;
  6220. Uint16 ADCRESULT12;
  6221. Uint16 ADCRESULT13;
  6222. Uint16 ADCRESULT14;
  6223. Uint16 ADCRESULT15;
  6224. union ADCTRL3_REG ADCTRL3; // ADC Contrl 3
  6225. union ADCST_REG ADCST; // ADC Status Register
  6226. };
  6227.  
  6228.  
  6229. //---------------------------------------------------------------------------
  6230. // ADC External References & Function Declarations:
  6231. //
  6232. extern volatile struct ADC_REGS AdcRegs;
  6233.  
  6234.  
  6235. //===========================================================================
  6236. // No more.
  6237. //===========================================================================
  6238. //
  6239. // TMDX ALPHA RELEASE
  6240. // Intended for product evaluation purposes
  6241. //
  6242. //###########################################################################
  6243. //
  6244. // FILE: DSP28_XIntrupt.h
  6245. //
  6246. // TITLE: DSP28 Device External Interrupt Register Definitions.
  6247. //
  6248. //###########################################################################
  6249. //
  6250. // Ver | dd mmm yyyy | Who | Description of changes
  6251. // =====|=============|======|===============================================
  6252. // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
  6253. // 0.56| 20 May 2002 | L.H. | No change
  6254. // 0.57| 27 May 2002 | L.H. | No change
  6255. // 0.58| 29 Jun 2002 | L.H. | No change
  6256. //###########################################################################
  6257.  
  6258.  
  6259. //---------------------------------------------------------------------------
  6260.  
  6261. struct XINTCR_BITS {
  6262. Uint16 ENABLE:1; // 0 enable/disable
  6263. Uint16 rsvd1:1; // 1 reserved
  6264. Uint16 POLARITY:1; // 2 pos/neg triggered
  6265. Uint16 rsvd2:12; // 15:3 reserved
  6266. };
  6267.  
  6268. union XINTCR_REG {
  6269. Uint16 all;
  6270. struct XINTCR_BITS bit;
  6271. };
  6272.  
  6273. struct XNMICR_BITS {
  6274. Uint16 ENABLE:1; // 0 enable/disable
  6275. Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to INT13
  6276. Uint16 POLARITY:1; // 2 pos/neg triggered
  6277. Uint16 rsvd2:12; // 15:3 reserved
  6278. };
  6279.  
  6280. union XNMICR_REG {
  6281. Uint16 all;
  6282. struct XNMICR_BITS bit;
  6283. };
  6284.  
  6285.  
  6286.  
  6287.  
  6288. //---------------------------------------------------------------------------
  6289. // External Interrupt Register File:
  6290. //
  6291. struct XINTRUPT_REGS {
  6292. union XINTCR_REG XINT1CR;
  6293. union XINTCR_REG XINT2CR;
  6294. Uint16 rsvd1[5];
  6295. union XNMICR_REG XNMICR;
  6296. Uint16 XINT1CTR;
  6297. Uint16 XINT2CTR;
  6298. Uint16 rsvd[5];
  6299. Uint16 XNMICTR;
  6300. };
  6301.  
  6302. //---------------------------------------------------------------------------
  6303. // External Interrupt References & Function Declarations:
  6304. //
  6305. extern volatile struct XINTRUPT_REGS XIntruptRegs;
  6306.  
  6307.  
  6308. //===========================================================================
  6309. // No more.
  6310. //===========================================================================
  6311.  
  6312. //---------------------------------------------------------------------------
  6313. // Define Device Init Function Prototype:
  6314. //
  6315. }
  6316.  
  6317.  
  6318.  
  6319. //===========================================================================
  6320. // No more.
  6321. //===========================================================================
  6322.  
  6323.  
  6324.  
  6325. /*!
  6326. \file co_ODvars.h
  6327. \brief ОбъЯвлЯет некоторые служебные структуры длЯ драйвера CANOpen
  6328.  
  6329. \author Aliamkin Dmitriy I
  6330. \version v 1.19 04/05/2012
  6331. @{
  6332. */
  6333.  
  6334. extern "C"
  6335. {
  6336.  
  6337. //#include "DSP.h"
  6338. //#include "CANOpen_drv.h"
  6339. //#include "V_eFIFO.h"
  6340. //****************************************************************************************************************************************
  6341. //! Начальный адрес длЯ сохранениЯ в SPI памЯти словарЯ 1-го CAN
  6342. //! Начальный адрес длЯ сохранениЯ в SPI памЯти словарЯ 2-го CAN
  6343.  
  6344. //!здесь указываетсЯ количество "замеппированных" объектов длЯ каждого PDO
  6345.  
  6346. // !!!данные параметры должны быть выставлены в соответствии с количеством объектов
  6347. //"замэппированных" в словаре объектов
  6348.  
  6349. //!Конфигурирование полей SDO
  6350. struct SDOcommSpecifier
  6351. {
  6352. Uint16 s :1; //!< 0 - если s=1, то размер передаваемых данных известен и указан
  6353. Uint16 e :1; //!< 1 - expedited или нет
  6354. Uint16 n :2; //!< 3:2 - количество байт данных не содержащих данных
  6355. Uint16 X :1; //!< 4 - reserved
  6356. Uint16 cs :3; //!< 7:5 - SDO команда
  6357. Uint16 reserved :8; //
  6358. };
  6359.  
  6360. //! Нулевой байт мейл-бокса
  6361. union MBOXByte0
  6362. {
  6363. struct SDOcommSpecifier SDO_Spicifier;
  6364. Uint16 byte0;
  6365. };
  6366. //! Байты мейл-бокса, используемого длЯ альтернативной CAN свЯзи (ZigBee, USB)
  6367. typedef struct
  6368. {
  6369. union MBOXByte0 MByte0;
  6370. Uint16 byte1;
  6371. Uint16 byte2;
  6372. Uint16 byte3;
  6373. Uint16 byte4;
  6374. Uint16 byte5;
  6375. Uint16 byte6;
  6376. Uint16 byte7;
  6377. Uint16 senderNodeID;
  6378. } Z_MBytes;
  6379.  
  6380. ///сообщение в виде полей SDO
  6381. struct SDOmsg
  6382. {
  6383. Uint32 s :1; //!< 0 - если s=1, то размер передаваемых данных известен и указан
  6384. Uint32 e :1; //!< 1 - expedited или нет
  6385. Uint32 n :2; //!< 3:2 - количество байт данных не содержащих данных
  6386. Uint32 X :1; //!< 4 - reserved
  6387. Uint32 cs :3; //!< 7:5 - SDO команда
  6388. Uint32 index :16;
  6389. Uint32 subindex :8;
  6390. Uint32 data :32;
  6391. };
  6392. //сообщение в виде байтов
  6393. struct MBOX_bytes
  6394. {
  6395. Uint16 byte0 :8;
  6396. Uint16 byte1 :8;
  6397. Uint16 byte2 :8;
  6398. Uint16 byte3 :8;
  6399. Uint16 byte4 :8;
  6400. Uint16 byte5 :8;
  6401. Uint16 byte6 :8;
  6402. Uint16 byte7 :8;
  6403. };
  6404. //сообщение в виде слов
  6405. struct MBOX_words
  6406. {
  6407. Uint16 word0;
  6408. Uint16 word1;
  6409. Uint16 word2;
  6410. Uint16 word3;
  6411. };
  6412. //сообщение в виде MDRL, MDRH
  6413. struct MBOX_Uint32
  6414. {
  6415. Uint32 MDRL;
  6416. Uint32 MDRH;
  6417. };
  6418. //все представлениЯ накладываем друг на друга
  6419. union MBOX_data
  6420. {
  6421. struct MBOX_Uint32 u32;
  6422. struct MBOX_words u16;
  6423. struct MBOX_bytes u8;
  6424. struct SDOmsg SDO;
  6425. };
  6426. typedef volatile union MBOX_data TMBOX_data;
  6427.  
  6428. struct MID_bits
  6429. {
  6430. Uint32 rsvd1 :18; //пока не используем
  6431. Uint32 senderNodeID :7; //номер узла
  6432. Uint32 rsvd2 :7; //пока не используем
  6433. };
  6434. union MID_data
  6435. {
  6436. Uint32 all;
  6437. struct MID_bits bit;
  6438. };
  6439. // мейл-бокс
  6440. struct MData
  6441. {
  6442. union MBOX_data data;
  6443. union MID_data MID;
  6444. };
  6445.  
  6446. //! Сборник данных всех мейл-боксов
  6447. struct CO_MBOXDATA
  6448. {
  6449. struct MData MBOX_0;
  6450. struct MData MBOX_1;
  6451. struct MData MBOX_2;
  6452. struct MData MBOX_3;
  6453. struct MData MBOX_4;
  6454. struct MData MBOX_5;
  6455. struct MData MBOX_6;
  6456. struct MData MBOX_7;
  6457. struct MData MBOX_8;
  6458. struct MData MBOX_9;
  6459. struct MData MBOX_10;
  6460. struct MData MBOX_11;
  6461. struct MData MBOX_12;
  6462. struct MData MBOX_13;
  6463. struct MData MBOX_14;
  6464. struct MData MBOX_15;
  6465. struct MData MBOX_16;
  6466. struct MData MBOX_17;
  6467. struct MData MBOX_18;
  6468. struct MData MBOX_19;
  6469. struct MData MBOX_20;
  6470. struct MData MBOX_21;
  6471. struct MData MBOX_22;
  6472. struct MData MBOX_23;
  6473. struct MData MBOX_24;
  6474. struct MData MBOX_25;
  6475. struct MData MBOX_26;
  6476. struct MData MBOX_27;
  6477. struct MData MBOX_28;
  6478. struct MData MBOX_29;
  6479. struct MData MBOX_30;
  6480. struct MData MBOX_31;
  6481. };
  6482.  
  6483. typedef volatile struct CO_MBOXDATA TCo_MboxData;
  6484.  
  6485. //****************************************************************************************************************************************
  6486. //структуры модулЯ блочной передачи
  6487. //внутримодульные дефайны
  6488.  
  6489. struct S_BT_FIFO
  6490. {
  6491. Uint16 busy_flag; //флаг занЯтости ФИФО, показывает количество инстанций, использующих ФИФО в данный момент
  6492. Uint16 size;
  6493. Uint16 number_of_msgs;
  6494. Uint16 read_ptr;
  6495. Uint16 write_ptr;
  6496. TMBOX_data msg_array[8];
  6497. Uint16 (*read)(volatile struct S_BT_FIFO*, TMBOX_data*);
  6498. Uint16 (*write)(volatile struct S_BT_FIFO*, TMBOX_data*);
  6499. Uint16 (*clear)(volatile struct S_BT_FIFO*);
  6500. };
  6501.  
  6502. typedef volatile struct S_BT_FIFO T_BT_FIFO;
  6503.  
  6504.  
  6505. Uint16 BT_FIFO_Read(T_BT_FIFO*, TMBOX_data*);
  6506. Uint16 BT_FIFO_Write(T_BT_FIFO*, TMBOX_data*);
  6507. Uint16 BT_FIFO_Clear(T_BT_FIFO* p);
  6508.  
  6509.  
  6510.  
  6511. struct SBlockTransfer
  6512. {
  6513. Uint16 state; //СостоЯние.
  6514. Uint16 state_shadow; //Теневое состоЯние.
  6515. Uint16 state_prev; //Предыдущее состоЯние (на один такт)
  6516. Uint16 E; //Флаг первого вхождениЯ.
  6517. Uint32 state_time; //времЯ нахождениЯ в текущем состоЯнии, в мс.
  6518. Uint16 RX_block_size; //размер принимаемого блока (определЯетсЯ пользователем перед приемом)
  6519. Uint16 TX_block_size; //размер отправлЯемого блока (определЯетсЯ пользователем перед отправкой)
  6520. Uint16 firstTXmsg; //флаг, показывающий, что 1-е сообщение блока еще не отправлЯлось.
  6521. Uint16* RX_dest_ptr;
  6522. Uint16* TX_source_ptr;
  6523. int RX_index;
  6524. int TX_index;
  6525. T_BT_FIFO RXmsgFIFO;
  6526. T_BT_FIFO TXmsgFIFO;
  6527. Uint16 blockCRC;
  6528. Uint16 rx_status; //обратнаЯ свЯзь длЯ внешней программы использующей блочную передачу
  6529. Uint16 tx_status; //
  6530. Uint32 timeout;
  6531. };
  6532.  
  6533. typedef volatile struct SBlockTransfer TBlockTransfer;
  6534.  
  6535.  
  6536. //! Стандартные переменные словарЯ CANOpen
  6537.  
  6538. //! Все перечисленные переменные должны быть добавлены в словаре CANOpen.
  6539. //!Так как CAN'а у контроллера два, то длЯ каждого словарЯ должны быть свои объекты,
  6540. //!чтобы иметь возможность настроить CANOpen по-разному. Поэтому делаетсЯ два экземплЯра этой структуры,
  6541. //!если это требуетсЯ.
  6542.  
  6543. struct SCo_OdVars
  6544. {
  6545. Uint32 co_deviceType; //1000.0
  6546. Uint16 co_errorRegister; //1001.0 Регистр ошибки
  6547. Uint32 co_deviceState; //1002.0
  6548. Uint32 co_emcyCOBID; //1014.0
  6549. Uint32 co_CHBT; //1016.1 Consumer heartbeat time
  6550. Uint32 co_PHBT; //1017.0 Producer heartbeat time
  6551. Uint32 co_vendorID; //1018.1
  6552. Uint32 co_productCode; //1018.2
  6553. Uint32 co_revisionNumber; //1018.3
  6554. Uint32 co_serialNumber; //1018.4
  6555. Uint32 co_csrxCOBID; //1200.1
  6556. Uint32 co_sctxCOBID; //1200.2
  6557. Uint32 co_cstxCOBID; //1280.1
  6558. Uint32 co_scrxCOBID; //1280.2
  6559. Uint16 co_ssNODEID; //1280.3
  6560. Uint32 co_RPDO1COBID; //1400.1
  6561. Uint16 co_transType; //1400.2 , 1401.2 , 1402.2 , 1403.2
  6562. Uint32 co_RPDO2COBID; //1401.1
  6563. Uint32 co_RPDO3COBID; //1402.1
  6564. Uint32 co_RPDO4COBID; //1403.1
  6565. //2007_03_14
  6566. Uint32 co_RPDO5COBID; //1404.1 rwp
  6567. Uint32 co_RPDO6COBID; //1405.1 rwp
  6568. Uint32 co_RPDO7COBID; //1406.1 rwp
  6569. Uint32 co_RPDO8COBID; //1407.1 rwp
  6570. //
  6571. Uint32 co_RPDO1_1Mapping; //1600.1
  6572. Uint32 co_RPDO1_2Mapping; //1600.2
  6573. Uint32 co_RPDO1_3Mapping; //1600.3
  6574. Uint32 co_RPDO1_4Mapping; //1600.4
  6575. Uint32 co_RPDO2_1Mapping; //1601.1
  6576. Uint32 co_RPDO2_2Mapping; //1601.2
  6577. Uint32 co_RPDO2_3Mapping; //1601.3
  6578. Uint32 co_RPDO2_4Mapping; //1601.4
  6579. Uint32 co_RPDO3_1Mapping; //1602.1
  6580. Uint32 co_RPDO3_2Mapping; //1602.2
  6581. Uint32 co_RPDO3_3Mapping; //1602.3
  6582. Uint32 co_RPDO3_4Mapping; //1602.4
  6583. Uint32 co_RPDO4_1Mapping; //1603.1
  6584. Uint32 co_RPDO4_2Mapping; //1603.2
  6585. Uint32 co_RPDO4_3Mapping; //1603.3
  6586. Uint32 co_RPDO4_4Mapping; //1603.4
  6587. //2007_03_14
  6588. Uint32 co_RPDO5_1Mapping; //1604.1 rwp
  6589. Uint32 co_RPDO5_2Mapping; //1604.2 rwp
  6590. Uint32 co_RPDO5_3Mapping; //1604.3 rwp
  6591. Uint32 co_RPDO5_4Mapping; //1604.4 rwp
  6592. Uint32 co_RPDO6_1Mapping; //1605.1 rwp
  6593. Uint32 co_RPDO6_2Mapping; //1605.2 rwp
  6594. Uint32 co_RPDO6_3Mapping; //1605.3 rwp
  6595. Uint32 co_RPDO6_4Mapping; //1605.4 rwp
  6596. Uint32 co_RPDO7_1Mapping; //1606.1 rwp
  6597. Uint32 co_RPDO7_2Mapping; //1606.2 rwp
  6598. Uint32 co_RPDO7_3Mapping; //1606.3 rwp
  6599. Uint32 co_RPDO7_4Mapping; //1606.4 rwp
  6600. Uint32 co_RPDO8_1Mapping; //1607.1 rwp
  6601. Uint32 co_RPDO8_2Mapping; //1607.2 rwp
  6602. Uint32 co_RPDO8_3Mapping; //1607.3 rwp
  6603. Uint32 co_RPDO8_4Mapping; //1607.4 rwp
  6604. //
  6605. Uint32 co_TPDO1COBID; //1800.1
  6606. Uint16 co_TPDO1ITime; //1800.3 rw
  6607. Uint16 co_compatEntry; //1800.4 rw
  6608. Uint16 co_TPDO1EventTimer; //1800.5 rw
  6609. Uint32 co_TPDO2COBID; //1801.1
  6610. Uint16 co_TPDO2ITime; //1801.3 rw
  6611. Uint16 co_TPDO2EventTimer; //1800.5 rw
  6612. Uint32 co_TPDO3COBID; //1802.1
  6613. Uint16 co_TPDO3ITime; //1802.3 rw
  6614. Uint16 co_TPDO3EventTimer; //1800.5 rw
  6615. Uint32 co_TPDO4COBID; //1803.1
  6616. Uint16 co_TPDO4ITime; //1803.3 rw
  6617. Uint16 co_TPDO4EventTimer; //1800.5 rw
  6618. //2007_03_14
  6619. Uint32 co_TPDO5COBID; //1804.1 r
  6620. Uint16 co_TPDO5ITime; //1804.3 rw
  6621. Uint16 co_TPDO5EventTimer; //1804.5 rw
  6622. Uint32 co_TPDO6COBID; //1805.1 r
  6623. Uint16 co_TPDO6ITime; //1805.3 rw
  6624. Uint16 co_TPDO6EventTimer; //1805.5 rw
  6625. Uint32 co_TPDO7COBID; //1806.1 r
  6626. Uint16 co_TPDO7ITime; //1806.3 rw
  6627. Uint16 co_TPDO7EventTimer; //1806.5 rw
  6628. Uint32 co_TPDO8COBID; //1807.1 r
  6629. Uint16 co_TPDO8ITime; //1807.3 rw
  6630. Uint16 co_TPDO8EventTimer; //1807.5 rw
  6631. //
  6632. Uint32 co_TPDO1_1Mapping; //1A00.1
  6633. Uint32 co_TPDO1_2Mapping; //1A00.2
  6634. Uint32 co_TPDO1_3Mapping; //1A00.3
  6635. Uint32 co_TPDO1_4Mapping; //1A00.4
  6636. Uint32 co_TPDO2_1Mapping; //1A01.1
  6637. Uint32 co_TPDO2_2Mapping; //1A01.2
  6638. Uint32 co_TPDO2_3Mapping; //1A01.3
  6639. Uint32 co_TPDO2_4Mapping; //1A01.4
  6640. Uint32 co_TPDO3_1Mapping; //1A02.1
  6641. Uint32 co_TPDO3_2Mapping; //1A02.2
  6642. Uint32 co_TPDO3_3Mapping; //1A02.3
  6643. Uint32 co_TPDO3_4Mapping; //1A02.4
  6644. Uint32 co_TPDO4_1Mapping; //1A03.1
  6645. Uint32 co_TPDO4_2Mapping; //1A03.2
  6646. Uint32 co_TPDO4_3Mapping; //1A03.3
  6647. Uint32 co_TPDO4_4Mapping; //1A03.4
  6648. //2007_03_14
  6649. Uint32 co_TPDO5_1Mapping; //1A04.1 rwp
  6650. Uint32 co_TPDO5_2Mapping; //1A04.2 rwp
  6651. Uint32 co_TPDO5_3Mapping; //1A04.3 rwp
  6652. Uint32 co_TPDO5_4Mapping; //1A04.4 rwp
  6653. Uint32 co_TPDO6_1Mapping; //1A05.1 rwp
  6654. Uint32 co_TPDO6_2Mapping; //1A05.2 rwp
  6655. Uint32 co_TPDO6_3Mapping; //1A05.3 rwp
  6656. Uint32 co_TPDO6_4Mapping; //1A05.4 rwp
  6657. Uint32 co_TPDO7_1Mapping; //1A06.1 rwp
  6658. Uint32 co_TPDO7_2Mapping; //1A06.2 rwp
  6659. Uint32 co_TPDO7_3Mapping; //1A06.3 rwp
  6660. Uint32 co_TPDO7_4Mapping; //1A06.4 rwp
  6661. Uint32 co_TPDO8_1Mapping; //1A07.1 rwp
  6662. Uint32 co_TPDO8_2Mapping; //1A07.2 rwp
  6663. Uint32 co_TPDO8_3Mapping; //1A07.3 rwp
  6664. Uint32 co_TPDO8_4Mapping; //1A07.4 rwp
  6665. //
  6666. Uint16 co_nodeID; //2000.0 номер данного узла
  6667. Uint16 co_bitRate; //2001.0
  6668. Uint16 co_specialData1; //2003.1
  6669. Uint16 co_specialData2; //2003.2
  6670. Uint16 co_specialData3; //2003.3
  6671. Uint16 co_specialData4; //2003.4
  6672. Uint32 co_secretCode; //2004.0
  6673. Uint16 co_protectBit; //2005.0 - ?
  6674. Uint32 co_devicePresentFlag0;
  6675. Uint32 co_devicePresentFlag1;
  6676. Uint32 co_devicePresentFlag2;
  6677. Uint32 co_devicePresentFlag3;
  6678. Uint32 co_deviceGlobalPresent0;
  6679. Uint32 co_deviceGlobalPresent1;
  6680. Uint32 co_deviceGlobalPresent2;
  6681. Uint32 co_deviceGlobalPresent3;
  6682. Uint32 co_heartbeatFlag0; //2010.1 Флаги heartbeat с 0 по 31-е устройство
  6683. Uint32 co_heartbeatFlag1; //2010.2 Флаги heartbeat с 32 по 63-е устройство
  6684. Uint32 co_heartbeatFlag2; //2010.3 Флаги heartbeat с 64 по 95-е устройство
  6685. Uint32 co_heartbeatFlag3; //2010.4 Флаги heartbeat с 96 по 127-е устройство
  6686. Uint32 co_heartbeatMask0; //2011.1 Маски heartbeat с 0 по 31-е устройство (0110b)
  6687. Uint32 co_heartbeatMask1; //2011.2 Маски heartbeat с 32 по 63-е устройство
  6688. Uint32 co_heartbeatMask2; //2011.3 Маски heartbeat с 64 по 95-е устройство
  6689. Uint32 co_heartbeatMask3; //2011.4 Маски heartbeat с 96 по 127-е устройство
  6690. Uint16 co_heartbeatAutoStart; //2012.0 Параметр, определЯющий возможен ли автозапуск сети
  6691. Uint16 co_heartbeatAutoRecovery; //2014.0 Параметр, определЯющий возможен ли перезапуск системы из состоЯниЯ STOPPED
  6692. Uint16 co_nodeState; //2015.0 состоЯние данного узла - вначале BOOTUP
  6693. Uint16 co_emergencyErrorCode; //2016.0 Код аварии
  6694. Uint32 co_deviceErrorState; //2017.0 Статусный регистр ошибок производителЯ
  6695. Uint16 co_ODCommand; //2080.1
  6696. Uint16 co_currentODIndex; //2080.2
  6697. Uint16 co_currentODSubIndex; //2080.3
  6698. Uint16 co_currentODEText; //2080.4
  6699. Uint16 co_currentODEFormat; //2080.5
  6700. Uint16 co_currentODEMin; //2080.6
  6701. Uint16 co_currentODEMax; //2080.7
  6702. Uint16 co_currentODEDefault; //2080.8
  6703. Uint16 co_currentODEMinLow; //2080.9
  6704. Uint16 co_currentODEMaxLow; //2080.10
  6705. Uint16 co_currentODEDefaultLow; //2080.11
  6706. Uint16 co_currentODEAddrHigh; //2080.12
  6707. Uint16 co_currentODEAddrLow;
  6708. Uint16 co_currentODEType;
  6709. Uint16 co_odIndexSize;
  6710. Uint32 co_defaultIndex1; //2082.1 rw
  6711. Uint32 co_defaultIndex2; //2082.2 rw
  6712. Uint16 co_maskElement01; //2083.1,2 rw
  6713. Uint16 co_maskElement23; //2083.3,4 rw
  6714. Uint16 co_maskElement45; //2083.5,6 rw
  6715. Uint16 co_maskElement67; //2083.7,8 rw
  6716. Uint16 co_maskElement89; //2083.9,A rw
  6717. Uint16 co_maskElementAB; //2083.B,C rw
  6718. Uint16 co_maskElementCD; //2083.D,E rw
  6719. Uint16 co_maskElementEF; //2083.F,10 rw
  6720. Uint16 co_profileAccessMask; //2081.0 rw
  6721. Uint16 co_scaleNum0; //2100.1
  6722. Uint16 co_scaleNum0Format; //2100.2
  6723. Uint16 co_scaleNum1; //2101.1
  6724. Uint16 co_scaleNum1Format; //2101.2
  6725. Uint16 co_scaleNum2; //2102.1
  6726. Uint16 co_scaleNum2Format; //2102.2
  6727. Uint16 co_scaleNum3; //2103.1
  6728. Uint16 co_scaleNum3Format; //2103.2
  6729. Uint16 co_scaleNum4; //2104.1
  6730. Uint16 co_scaleNum4Format; //2104.2
  6731. Uint16 co_scaleNum5; //2105.1
  6732. Uint16 co_scaleNum5Format; //2105.2
  6733. Uint16 co_scaleNum6; //2106.1
  6734. Uint16 co_scaleNum6Format; //2106.2
  6735. Uint16 co_scaleNum7; //2107.1
  6736. Uint16 co_scaleNum7Format; //2107.2
  6737. Uint16 co_scaleNum8; //2108.1
  6738. Uint16 co_scaleNum8Format; //2108.2
  6739. Uint16 co_scaleNum9; //2109.1
  6740. Uint16 co_scaleNum9Format; //2109.2
  6741. Uint16 co_scaleNumA; //210A.1
  6742. Uint16 co_scaleNumAFormat; //210A.2
  6743. Uint16 co_scaleNumB; //210B.1
  6744. Uint16 co_scaleNumBFormat; //210B.2
  6745. Uint16 co_scaleNumC; //210C.1
  6746. Uint16 co_scaleNumCFormat; //210C.2
  6747. Uint16 co_scaleNumD; //210D.1
  6748. Uint16 co_scaleNumDFormat; //210D.2
  6749. Uint16 co_scaleNumE; //210E.1
  6750. Uint16 co_scaleNumEFormat; //210E.2
  6751. Uint16 co_scaleNumF; //210F.1
  6752. Uint16 co_scaleNumFFormat; //210F.2
  6753. Uint16 co_scaleNum10; //2110.1
  6754. Uint16 co_scaleNum10Format; //2110.2
  6755. Uint16 co_scaleNum11; //2111.1
  6756. Uint16 co_scaleNum11Format; //2111.2
  6757. Uint16 co_scaleNum12; //2112.1
  6758. Uint16 co_scaleNum12Format; //2112.2
  6759. Uint16 co_scaleNum13; //2113.1
  6760. Uint16 co_scaleNum13Format; //2113.2
  6761. Uint16 co_scaleNum14; //2114.1
  6762. Uint16 co_scaleNum14Format; //2114.2
  6763. Uint16 co_scaleNum15; //2115.1
  6764. Uint16 co_scaleNum15Format; //2115.2
  6765. Uint16 co_scaleNum16; //2116.1
  6766. Uint16 co_scaleNum16Format; //2116.2
  6767. Uint16 co_scaleNum17; //2117.1
  6768. Uint16 co_scaleNum17Format; //2117.2
  6769. Uint16 co_scaleNum18; //2118.1
  6770. Uint16 co_scaleNum18Format; //2118.2
  6771. Uint16 co_scaleNum19; //2119.1
  6772. Uint16 co_scaleNum19Format; //2119.2
  6773. Uint16 co_scaleNum1A; //211A.1
  6774. Uint16 co_scaleNum1AFormat; //211A.2
  6775. Uint16 co_scaleNum1B; //211B.1
  6776. Uint16 co_scaleNum1BFormat; //211B.2
  6777. Uint16 co_scaleNum1C; //211C.1
  6778. Uint16 co_scaleNum1CFormat; //211C.2
  6779. Uint16 co_scaleNum1D; //211D.1
  6780. Uint16 co_scaleNum1DFormat; //211D.2
  6781. Uint16 co_scaleNum1E; //211E.1
  6782. Uint16 co_scaleNum1EFormat; //211E.2
  6783. Uint16 co_scaleNum1F; //211F.1
  6784. Uint16 co_scaleNum1FFormat; //211F.2
  6785.  
  6786. Uint16 co_blockTransferCommand; //2700
  6787.  
  6788. //Указатели
  6789. Uint16 *co_currentWordODTbl1; //данные указатели ипользуютсЯ длЯ работы интерпретатора
  6790. Uint16 *co_currentWordODTbl2; //команд в прерывании ШИМ (длЯ обработки быстрых команд)
  6791. Uint16 co_currentAccessMask; //маска доступа индекса на который указывает co_currentWordODTbl1
  6792.  
  6793. Uint16 *co_shadow_currentWordODTbl1; //данные указатели ипользуютсЯ длЯ работы интерпретатора
  6794. Uint16 *co_shadow_currentWordODTbl2; //команд в фоновой программе (длЯ обработки медленных команд)
  6795.  
  6796. Uint16 *co_SDOcurrentWordODTbl1;
  6797. Uint16 *co_SDOcurrentWordODTbl2;
  6798.  
  6799. //ZBee
  6800. Uint16 *Z_co_SDOcurrentWordODTbl1;
  6801. Uint16 *Z_co_SDOcurrentWordODTbl2;
  6802.  
  6803. Uint16 *co_PDOcurrentWordODTbl1;
  6804. Uint16 *co_PDOcurrentWordODTbl2;
  6805. Uint16 *co_PDOMAPcurrentWordODTbl1;
  6806. Uint16 *co_PDOMAPcurrentWordODTbl2;
  6807.  
  6808. Uint16 *co_endODTbl1; //указывает на последний элемент индекс в таблице ODTbl1
  6809. TCo_MboxData co_MboxesData;
  6810. Uint32 co_MailboxMDRL;
  6811. Uint32 co_MailboxMDRH;
  6812. Uint32 co_MailboxMID;
  6813.  
  6814. Uint32 co_flagBackUp0; //
  6815. Uint32 co_flagBackUp1; // предыдущие состоЯниЯ флагов
  6816. Uint32 co_flagBackUp2; //
  6817. Uint32 co_flagBackUp3; //
  6818.  
  6819. Uint32 co_backupEEC; // Предыдущее состоЯние кода аварии
  6820. Uint32 co_backupER; // Предыдущее состоЯние регистра ошибки
  6821. Uint32 co_backupDES; // Предыдущее состоЯние статусного регистра ошибок производителЯ
  6822.  
  6823. Uint32 co_consHBTimeCounter; // изначально должен быть равен co_CHBT
  6824. Uint32 co_prodHBTimeCounter; // изначально должен быть равен co_PHBT
  6825. Uint32 co_emcyNewState; // СостоЯние в которое перешел узел после ошибки
  6826. Uint32 co_msDevisor; // делитель частоты длЯ получениЯ 1мс - используетсЯ длЯ отправки Heartbeat
  6827.  
  6828. Uint16 co_shadow_currentODIndex;
  6829. Uint16 co_shadow_currentODSubIndex;
  6830. Uint16 co_shadow_currentODEText;
  6831. Uint16 co_shadow_currentODEFormat;
  6832. Uint16 co_shadow_currentODEMin;
  6833. Uint16 co_shadow_currentODEMax;
  6834. Uint16 co_shadow_currentODEDefault;
  6835. Uint16 co_shadow_currentODEMinLow;
  6836. Uint16 co_shadow_currentODEMaxLow;
  6837. Uint16 co_shadow_currentODEDefaultLow;
  6838. Uint16 co_shadow_currentODEAddrLow;
  6839. Uint16 co_shadow_currentODEAddrHigh;
  6840. Uint16 co_shadow_currentODEType;
  6841. //переменные необходимые длЯ работы SDO служб
  6842. Uint16 co_SDOrequestIndex;
  6843. Uint16 co_SDOrequestSubIndex;
  6844. Uint16 co_SDOrequestData;
  6845. Uint16 co_SDOrequestDataH;
  6846. Uint16 co_SDOrequestStatus;
  6847. Uint16 co_SDOrequestFlag;
  6848. Uint16 requestR;
  6849. Uint16 requestW;
  6850. Uint16 co_SDOSuspendedSend;
  6851.  
  6852. //временнаЯ переменнаЯ защиты секретных параметров от несанкционированного доступа
  6853. Uint16 co_secretProtectBit;
  6854.  
  6855. //переменные необходимые длЯ работы PDO служб
  6856. Uint16 co_PDOMappingFlags; //RRRR RRRR TTTT TTTT - "T" - TPDO;- "R" - RPDO
  6857.  
  6858. Uint16 co_PDO1Devisor; // делитель длЯ получениЯ заданной скорости передачи PDO1
  6859. Uint16 co_PDO2Devisor;
  6860. Uint16 co_PDO3Devisor;
  6861. Uint16 co_PDO4Devisor;
  6862. Uint16 co_PDO5Devisor;
  6863. Uint16 co_PDO6Devisor;
  6864. Uint16 co_PDO7Devisor;
  6865. Uint16 co_PDO8Devisor;
  6866. //
  6867. Uint16 co_NumOfNextPDO;
  6868. Uint16 co_PDOTransmitFlags; //0000 0000 TTTT TTTT
  6869. Uint16 co_PDOTransmitEna; //0000 0000 TTTT TTTT
  6870. Uint16 co_PDOReceiveEna; //0000 0000 RRRR RRRR
  6871.  
  6872. Uint16 co_my_PDO1TransmitFlags;
  6873. Uint16 co_my_PDO2TransmitFlags;
  6874. Uint16 co_my_PDO3TransmitFlags;
  6875. Uint16 co_my_PDO4TransmitFlags;
  6876. Uint16 co_my_PDO5TransmitFlags;
  6877. Uint16 co_my_PDO6TransmitFlags;
  6878. Uint16 co_my_PDO7TransmitFlags;
  6879. Uint16 co_my_PDO8TransmitFlags;
  6880.  
  6881. Uint32 co_RPDO1_addr[4];
  6882. Uint32 co_RPDO2_addr[4];
  6883. Uint32 co_RPDO3_addr[4];
  6884. Uint32 co_RPDO4_addr[4];
  6885. //2007_03_14
  6886. Uint32 co_RPDO5_addr[4];
  6887. Uint32 co_RPDO6_addr[4];
  6888. Uint32 co_RPDO7_addr[4];
  6889. Uint32 co_RPDO8_addr[4];
  6890. //
  6891.  
  6892. Uint16 co_RPDO1_startBit[4];
  6893. Uint16 co_RPDO2_startBit[4];
  6894. Uint16 co_RPDO3_startBit[4];
  6895. Uint16 co_RPDO4_startBit[4];
  6896. //2007_03_14
  6897. Uint16 co_RPDO5_startBit[4];
  6898. Uint16 co_RPDO6_startBit[4];
  6899. Uint16 co_RPDO7_startBit[4];
  6900. Uint16 co_RPDO8_startBit[4];
  6901. //
  6902.  
  6903. Uint16 co_RPDO1_numOfBits[4];
  6904. Uint16 co_RPDO2_numOfBits[4];
  6905. Uint16 co_RPDO3_numOfBits[4];
  6906. Uint16 co_RPDO4_numOfBits[4];
  6907. //2007_03_14
  6908. Uint16 co_RPDO5_numOfBits[4];
  6909. Uint16 co_RPDO6_numOfBits[4];
  6910. Uint16 co_RPDO7_numOfBits[4];
  6911. Uint16 co_RPDO8_numOfBits[4];
  6912. //
  6913.  
  6914. Uint32 co_TPDO1_addr[4];
  6915. Uint32 co_TPDO2_addr[4];
  6916. Uint32 co_TPDO3_addr[4];
  6917. Uint32 co_TPDO4_addr[4];
  6918. //2007_03_14
  6919. Uint32 co_TPDO5_addr[4];
  6920. Uint32 co_TPDO6_addr[4];
  6921. Uint32 co_TPDO7_addr[4];
  6922. Uint32 co_TPDO8_addr[4];
  6923. //
  6924.  
  6925. Uint16 co_TPDO1_startBit[4];
  6926. Uint16 co_TPDO2_startBit[4];
  6927. Uint16 co_TPDO3_startBit[4];
  6928. Uint16 co_TPDO4_startBit[4];
  6929. //2007_03_14
  6930. Uint16 co_TPDO5_startBit[4];
  6931. Uint16 co_TPDO6_startBit[4];
  6932. Uint16 co_TPDO7_startBit[4];
  6933. Uint16 co_TPDO8_startBit[4];
  6934. //
  6935.  
  6936. Uint16 co_TPDO1_numOfBits[4];
  6937. Uint16 co_TPDO2_numOfBits[4];
  6938. Uint16 co_TPDO3_numOfBits[4];
  6939. Uint16 co_TPDO4_numOfBits[4];
  6940. //2007_03_14
  6941. Uint16 co_TPDO5_numOfBits[4];
  6942. Uint16 co_TPDO6_numOfBits[4];
  6943. Uint16 co_TPDO7_numOfBits[4];
  6944. Uint16 co_TPDO8_numOfBits[4];
  6945. //
  6946. Uint16 load_params_from_SPI;
  6947. Uint16 ParamRestorationError;
  6948. Uint16 co_requestCANInit;
  6949.  
  6950. Uint32 ISRDroppingCounter;
  6951. //данные из coodedit-а
  6952. //Uint16 co_numOfInd;
  6953. int16* OD_TBL1;
  6954. Uint16* OD_TBL2;
  6955. int32* OD_TBL3;
  6956. Uint16* TYPE_DEF_TABLE;
  6957. int32* OD_CALLBACK_TBL;
  6958.  
  6959. Uint16 co_SPIrange1rw;
  6960. Uint16 co_SPIrange1rwCRC;
  6961. Uint16 co_SPIrange1rwp;
  6962. Uint16 co_SPIrange1rwpCRC;
  6963. Uint16 co_SPIrange1rwps;
  6964. Uint16 co_SPIrange1rwpsCRC;
  6965. Uint16 co_SPIrange2rw;
  6966. Uint16 co_SPIrange2rwCRC;
  6967. Uint16 co_SPIrange2rwp;
  6968. Uint16 co_SPIrange2rwpCRC;
  6969. Uint16 co_SPIrange2rwps;
  6970. Uint16 co_SPIrange2rwpsCRC;
  6971. Uint16 co_SPIrange3rw;
  6972. Uint16 co_SPIrange3rwCRC;
  6973. Uint16 co_SPIrange3rwp;
  6974. Uint16 co_SPIrange3rwpCRC;
  6975. Uint16 co_SPIrange3rwps;
  6976. Uint16 co_SPIrange3rwpsCRC;
  6977. Uint16 co_SPIrange4rw;
  6978. Uint16 co_SPIrange4rwCRC;
  6979. Uint16 co_SPIrange4rwp;
  6980. Uint16 co_SPIrange4rwpCRC;
  6981. Uint16 co_SPIrange4rwps;
  6982. Uint16 co_SPIrange4rwpsCRC;
  6983. Uint16 co_SPIrange5rw;
  6984. Uint16 co_SPIrange5rwCRC;
  6985. Uint16 co_SPIrange5rwp;
  6986. Uint16 co_SPIrange5rwpCRC;
  6987. Uint16 co_SPIrange5rwps;
  6988. Uint16 co_SPIrange5rwpsCRC;
  6989. Uint16 co_first1000;
  6990. Uint16 co_first2000;
  6991. Uint16 co_first3000;
  6992. Uint16 co_first4000;
  6993. Uint16 co_first5000;
  6994. //указатели длЯ работы с регистрами и функциЯми, привЯзанными к аппаратной части
  6995. volatile struct ECAN_REGS* ECanRegs;
  6996. volatile struct ECAN_MBOXES* ECanMboxes;
  6997. volatile struct LAM_REGS* ECanLAMRegs;
  6998. void (*GpioInit)();
  6999. void (*CANINTDisable)();
  7000. void (*CANINTEnable)();
  7001. // #ifdef CAN_BLOCK_TRANSFER_ENABLE
  7002. TBlockTransfer* BT; //указатель делаем чтоб легко инициализировать структуру TBlockTransfer
  7003. // #endif
  7004.  
  7005. };
  7006.  
  7007. typedef volatile struct SCo_OdVars TCo_OdVars;
  7008.  
  7009. extern TCo_OdVars co1_vars;
  7010. extern TCo_OdVars co2_vars;
  7011. extern TBlockTransfer CANaBlockTransfer;
  7012. extern TBlockTransfer CANbBlockTransfer;
  7013.  
  7014. //***************************************************************************************************************************************************
  7015. }
  7016.  
  7017. /*@}*/
  7018.  
  7019. /*!
  7020. \file v_data_log.h
  7021. \brief 4-х канальный логгер длЯ осциллографированиЯ в реальном времени (см. TDataLog)
  7022.  
  7023. \author Коллектив ООО НПФ Вектор
  7024. \version v 1.0 21/02/2010
  7025. \defgroup v_data_log Цифровой осциллограф (см. TDataLog)
  7026.  
  7027. @{
  7028. */
  7029.  
  7030.  
  7031.  
  7032. extern "C"
  7033. {
  7034.  
  7035. //! change "int" to "long" or "float" according to variable type
  7036. typedef int16 type_data;
  7037.  
  7038. //! Размер массивов длЯ осциллографированиЯ.
  7039.  
  7040. //!Если нужно менЯть, то это делать надо не только тут - слишком много завЯзано на это число
  7041. //!Переделать сложно, так как на это число завЯзка косвеннаЯ: например, длЯ ускорениЯ работы
  7042. //!применЯютсЯ такие конструкции: p->Wcounter&=0xFF; Где FF - маска (символизирует 256 точек)
  7043.  
  7044. /*! \class TDataLog
  7045. \brief 4-х канальный логгер длЯ осциллографированиЯ в реальном времени
  7046.  
  7047. Класс \a TDataLog, основанный на структуре SDataLog, позволЯет записывать выбранные 4 переменных в массивы
  7048. из 255 точек с заданной дискретизацией по времени. Кроме того, имеет
  7049. свЯзь с драйвером CANOpen длЯ автоматизации указаниЯ этих переменных: можно
  7050. "зарЯдить" в даталоггер любой существующий элемент словарЯ.*/
  7051.  
  7052. //! см. TDataLog
  7053. struct SDataLog
  7054. {
  7055. type_data buff[(256*4)]; //4 массива для отснятых осциллограмм, слепленные в один большой
  7056. type_data *dlog_iptr1; //!< указатели на переменные для записи (например. ток фазы A, скорость и т.д.)
  7057. type_data *dlog_iptr2; //!< Input: Second input pointer (Q15)
  7058. type_data *dlog_iptr3;
  7059. type_data *dlog_iptr4;
  7060. int dlog_cntr_max; //!< Parameter: Maximum number of samples
  7061. Uint16 Wcounter; //!< Счетчик по массиву длЯ записи
  7062. Uint16 Rcounter; //!< Счетчик по массиву длЯ чтениЯ
  7063. type_data* dl_buffer1_adr; //!< Указатели на массивы, где лежат отснятые осциллограммы
  7064. type_data* dl_buffer2_adr; //!< Parameter: Buffer starting address 2
  7065. type_data* dl_buffer3_adr;
  7066. type_data* dl_buffer4_adr;
  7067.  
  7068. type_data upload_buff[256]; //массив для отправки осциллограммы в юникон. Сюда копируется осциллограмма из одного из четырех массивов buff со смещением, чтобы начало осциллограммы было в начале массива.
  7069. type_data* dl_upload_buffer_adr; //указатель на массив для отправки.
  7070. Uint32 trig_shift; //сдвиг первой точки после срабатывания триггера. Используется, чтобы задать, сколько точек предыстории сохранять.
  7071. Uint16 trig_shift_int; //то же, переведенное в точки
  7072. Uint16 first_point_written; //первая точка, относящаяся к записываемой осциллограмме с учетом длины предыстории и точки срабатывания триггера
  7073. Uint16 prehistory_length; //длина записанной предыстории (если даталоггер переинициализировался кнопкой "обновить", она обнуляется)
  7074. Uint16 valid_points_num; //счетчик валидных точек предыстории, записанных после переинициализации кнопкой "обновить" в юниконе
  7075.  
  7076. /*! Режимов работы четыре:\n
  7077. 0 - стоп\n
  7078. 1 - однократнаЯ запись\n
  7079. 2 - запись по кругу без остановки\n
  7080. 3 - однократнаЯ запись одной переменной во все 4 массива последовательно, длЯ получениЯ длинной осциллограммы.\n
  7081. Устанавливать переменную надо только вызовом функции set_mode! */
  7082. Uint16 mode_reset; //!< задаетсЯ режим работы
  7083. Uint16 mode_reset_prev; //!< предыдущий режим работы
  7084. int E; // флаг энтри
  7085.  
  7086. /*! "control" имеет 32 разрЯда. Первые 8 бит первого слова отведем под флаги, второе слово под установку разреживаниЯ.\n
  7087. 7 6 5 4 3 2 1 0\n
  7088. | x | x | x | x | x | x | x | x |\n
  7089. | | | | первые 4 бита - какие из 4х переменых интересуют (какие сдреса обновлЯть, какие данные записывать)\n
  7090. | | 2 бита - желаемый режим даталоггера. Ноль, один, два.\n
  7091. | бит "данные готовы" - устанавливаетсЯ контроллером\n
  7092. резерв */
  7093. long control; //!< управление даталоггером через внешние программы
  7094.  
  7095. unsigned int WriteDelimiter; //!<делитель данных при записи
  7096. unsigned int WriteDelimiterCounter; //!<Счетчик длЯ делителЯ
  7097. long ind_subind1; //!<записываетсЯ индекс и подындекс длЯ словарЯ
  7098. long ind_subind2;
  7099. long ind_subind3;
  7100. long ind_subind4;
  7101. unsigned long next_value_var; //!<через эту переменную выдвигаютсЯ записанные значениЯ при считывании
  7102. Uint16 StartBits;
  7103. int buff_num; //!<номер массива, из которого идет выдвижение значений в next_value_var
  7104. Uint16 OneShotOperation; //!<флаг синхронизации осциллографа только по первому событию (переход в 1 возможен только из 2)
  7105. void (*update)(volatile struct SDataLog *); //!<Pointer to update function
  7106. void (*set_mode)(Uint16 mode_reset,volatile struct SDataLog *); //!<Pointer to set_mode function
  7107. void (*background_analizer)(volatile struct SDataLog *); //!<Pointer to background_analizer function
  7108. } ;
  7109.  
  7110. typedef volatile struct SDataLog TDataLog;
  7111.  
  7112.  
  7113.  
  7114.  
  7115.  
  7116. //! Инициализатор по-умолчанию длЯ данного класса
  7117.  
  7118.  
  7119. //! \memberof TDataLog
  7120. void data_log_update(TDataLog *);
  7121. //! \memberof TDataLog
  7122. void dlog_set_mode(Uint16 mode_reset,TDataLog *);
  7123. //! \memberof TDataLog
  7124. void dlog_background_analizer(TDataLog *);
  7125.  
  7126. }
  7127.  
  7128.  
  7129. /*@}*/
  7130.  
  7131.  
  7132.  
  7133. extern Uint16 * co_getAddr(TCo_OdVars* ppc, Uint32 ind_subind);
  7134.  
  7135. //! Фоновый обработчик.
  7136.  
  7137. /*! работает в фоне. Нужно длЯ установки адресов переменных через CAN.
  7138. если нет CAN, можно записать нужные адреса вручную в TDataLog.dlog_iptr */
  7139. //! \memberof TDataLog
  7140. void dlog_background_analizer(TDataLog *p) {
  7141. //перевод длины предыстории из % в точки
  7142. p->trig_shift_int = (p->trig_shift&0xFFFFFF)>>16; //делаем количество точек
  7143. if (p->trig_shift_int > 255) //ограничим
  7144. p->trig_shift_int = 255;
  7145.  
  7146. TCo_OdVars *pco_vars = &co1_vars; //с каким словарем работать. От какого CAN
  7147. unsigned char mode;
  7148.  
  7149. //если не стоит хоть один из первых шести бит control,
  7150. //то ничего анализировать и делать не надо
  7151. if (!(p->control & 0x3F))
  7152. return;
  7153. //В любом случае перед всеми изменениЯми
  7154. //тормозим даталоггер. Иначе он может начать записывать данные по прерыванию,
  7155. //пока тут, в фоне, идет, скажем, запись адресов.
  7156. //И тогда в лучшем случае будет каша из данных, в худшем - останов контроллера
  7157. //при обращении по неправильному адресу.
  7158. p->mode_reset = 0;
  7159. p->valid_points_num = 0; //т.к. даталоггер останавливался (mode = 0), то предыстория неактуальна, т.к.
  7160. //1) за время стопа даталоггера между записанной предысторией и новыми данными будет разрыв по времени и
  7161. //2) выбранные записываемые переменные вообще могли смениться и предыстория останется от старых, а новые данные - от новых
  7162. //спрашиваем адреса у драйвера CAN_OPEN
  7163. if (p->control & 1)
  7164. if (!(p->dlog_iptr1 = (type_data*) co_getAddr(pco_vars, p->ind_subind1))) //если адрес=0
  7165. p->dlog_iptr1 = (type_data*) &p->ind_subind1; //пусть указывает на ind_subind
  7166. if (p->control & 2)
  7167. if (!(p->dlog_iptr2 = (type_data*) co_getAddr(pco_vars, p->ind_subind2)))
  7168. p->dlog_iptr2 = (type_data*) &p->ind_subind2;
  7169. if (p->control & 4)
  7170. if (!(p->dlog_iptr3 = (type_data*) co_getAddr(pco_vars, p->ind_subind3)))
  7171. p->dlog_iptr3 = (type_data*) &p->ind_subind3;
  7172. if (p->control & 8)
  7173. if (!(p->dlog_iptr4 = (type_data*) co_getAddr(pco_vars, p->ind_subind4)))
  7174. p->dlog_iptr4 = (type_data*) &p->ind_subind4;
  7175. p->WriteDelimiter = (p->control >> 16) & 0xFF; //прореживание. ОграничиваетсЯ 8ю битами
  7176. mode = (p->control >> 4) & 3; //режим - 2 бита
  7177. p->control = 0; //все обработали, обнулЯем, чтобы при след. вызове не начать обрабатывать снова
  7178. dlog_set_mode(mode, p); //длЯ установки режима вызываетсЯ спец. функциЯ. НапрЯмую нельзЯ
  7179. }
  7180.  
  7181. //! функциЯ длЯ установки mode_reset.
  7182.  
  7183. //! предполагаетсЯ длЯ управлениЯ логгером из других модулей
  7184. //! проверЯет mode_reset на валидность и обнулЯет счетчики
  7185. //! \memberof TDataLog
  7186. #pragma CODE_SECTION("secureRamFuncs")
  7187.  
  7188. void dlog_set_mode(Uint16 mode_reset, TDataLog *p) {
  7189. if (mode_reset > 3)
  7190. return;
  7191. //в 1 переводим только если текущий режим 2, чтоб синхронизироватьсЯ
  7192. //по первому событию (очень полезно когда событий много)
  7193. if (p->OneShotOperation == 1) {
  7194. if ((mode_reset == 1)) {
  7195. if (p->mode_reset == 2)
  7196. p->mode_reset = mode_reset;
  7197. else
  7198. return;
  7199. }
  7200. } else
  7201. p->mode_reset = mode_reset;
  7202.  
  7203. //при смене режима в любом случае сбрасываем флаг "данные готовы"
  7204. p->control = ~((~p->control) | 64);
  7205. p->WriteDelimiterCounter = 0;
  7206. }
  7207.  
  7208. //! Записывает очередные точки в массивы осциллограммы.
  7209.  
  7210. //!Должна вызыватьсЯ с заданной дискретизацией и занимаетсЯ записью массивов,
  7211. //! т.е. непосредственно осциллографированием. Умеет записывать данные
  7212. //! в массивы по-разному в зависимости от выбранного режима работы осциллографа
  7213. //! \memberof TDataLog
  7214. #pragma CODE_SECTION("secureRamFuncs")
  7215. void data_log_update(TDataLog *p) {
  7216. //везде испоьзуетсЯ p-> , а не p* - так быстрее
  7217.  
  7218. //прореживание данных. Если не достигли уставки WriteDelimiter, выходим
  7219. //WriteDelimiter=1 - не делим
  7220. //WriteDelimiter=2 - берем каждую вторую
  7221. if ((p->WriteDelimiterCounter++ + 1) < p->WriteDelimiter)
  7222. return;
  7223. else
  7224. p->WriteDelimiterCounter = 0;
  7225.  
  7226. if (p->mode_reset != p->mode_reset_prev) p->E=1;
  7227. else p->E=0;
  7228. p->mode_reset_prev = p->mode_reset;
  7229.  
  7230. switch (p->mode_reset) {
  7231. case 0: {
  7232. p->Wcounter = 0;
  7233. return;
  7234. }
  7235.  
  7236. case 1: //однократнаЯ запись - дошли до конца и стоп (режим 0)
  7237. {
  7238. //При входе в режим получаем точку срабатывания триггера (это текущий Wcounter, с которым мы сюда зашли) и рассчитываем первую точку, относящуюся к данной осце (исходя из текущей точки и заданной длины предыстории)
  7239. if (p->E==1)
  7240. {
  7241. p->prehistory_length = p->valid_points_num; //длина предыстории равна количеству валидных точек
  7242. if (p->prehistory_length > p->trig_shift_int) //если предыстория длиннее заданного, ограничим
  7243. p->prehistory_length = p->trig_shift_int;
  7244. p->first_point_written = (p->Wcounter - p->prehistory_length + 1) & 0xFE; //& 0xFE, чтобы получить четное число не более 254. Начальная точка осциллограммы должна быть четной т.к. копируем в массив для буферной
  7245. //передачи попарно. +1 - чтобы предыстория получилась на 1 точку короче, а не длиннеее (мало ли что там в этой лишней точке лежит...).
  7246. }
  7247. p->Wcounter &= 0xFF; //защита - если вдруг в counter не валидное значение
  7248. p->dl_buffer1_adr[p->Wcounter] = *p->dlog_iptr1;
  7249. p->dl_buffer2_adr[p->Wcounter] = *p->dlog_iptr2;
  7250. p->dl_buffer3_adr[p->Wcounter] = *p->dlog_iptr3;
  7251. p->dl_buffer4_adr[p->Wcounter] = *p->dlog_iptr4;
  7252. p->Wcounter++;
  7253. p->Wcounter &= 0xFF; //если прошли 256 точек, обнулитсЯ
  7254. //if (p->Wcounter == 0) //если ноль,
  7255. if (p->Wcounter == p->first_point_written) //если дошли до последней записываемой точки
  7256. {
  7257. p->mode_reset = 0; //режим СТОП
  7258. p->control|=64; //флаг "данные готовы"
  7259. }
  7260. return;
  7261. }
  7262.  
  7263. case 2: //записываем лог по кругу
  7264. {
  7265. p->valid_points_num++; //считаем количество записанных валидных точек предыстории
  7266. if (p->valid_points_num > 256) //ограничиваем
  7267. p->valid_points_num = 256;
  7268. p->Wcounter &= 0xFF; //защита - если вдруг в counter не валидное значение
  7269. p->dl_buffer1_adr[p->Wcounter] = *p->dlog_iptr1;
  7270. p->dl_buffer2_adr[p->Wcounter] = *p->dlog_iptr2;
  7271. p->dl_buffer3_adr[p->Wcounter] = *p->dlog_iptr3;
  7272. p->dl_buffer4_adr[p->Wcounter] = *p->dlog_iptr4;
  7273. p->Wcounter++;
  7274. p->Wcounter &= 0xFF; //если прошли 256 точек, обнулитсЯ
  7275. return;
  7276. }
  7277.  
  7278. case 3: //режим однократной записи 1024 точек
  7279. {
  7280. //с учетом того, что буферы в памЯти расположены последовательно,
  7281. //записываем в первый, "заезжаЯ" на остальные три
  7282. p->dl_buffer1_adr[p->Wcounter] = *p->dlog_iptr1;
  7283. p->Wcounter++;
  7284. if (p->Wcounter >= 1024) //если дошли до конца
  7285. {
  7286. p->mode_reset = 0; //режим СТОП
  7287. p->control|=64; //флаг "данные готовы"
  7288. }
  7289. return;
  7290. }
  7291. }
  7292.  
  7293. }
  7294.  
  7295. /*@}*/
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