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  1. From 420497e2891a2ed31619e016a9d597d165ea4eb9 Mon Sep 17 00:00:00 2001
  2. From: Michel Thierry <michel.thierry@intel.com>
  3. Date: Tue, 23 Jun 2015 10:46:49 +0100
  4. Subject: [PATCH v2] intel: Add EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag.
  5.  
  6. Gen8+ supports 48-bit virtual addresses, but some objects must always be
  7. allocated inside the 32-bit address range.
  8.  
  9. In specific, any resource used with flat/heapless (0x00000000-0xfffff000)
  10. General State Heap (GSH) or Intruction State Heap (ISH) must be in a
  11. 32-bit range, because the General State Offset and Instruction State Offset
  12. are limited to 32-bits.
  13.  
  14. Provide a flag to set when the 4GB limit is not necessary in a given bo.
  15. 48-bit range will only be used when explicitly requested.
  16.  
  17. Calls to the new drm_intel_bo_emit_reloc_48bit function will have this flag
  18. set automatically, while calls to drm_intel_bo_emit_reloc will clear it.
  19.  
  20. v2: Make set/clear functions nops on pre-gen8 platforms, and use them
  21. internally in emit_reloc functions (Ben)
  22. s/48BADDRESS/48B_ADDRESS/ (Dave)
  23.  
  24. Cc: Ben Widawsky <ben@bwidawsk.net>
  25. Cc: Dave Gordon <david.s.gordon@intel.com>
  26. Signed-off-by: Michel Thierry <michel.thierry@intel.com>
  27. ---
  28. include/drm/i915_drm.h | 3 ++-
  29. intel/intel_bufmgr.c | 24 +++++++++++++++++++++
  30. intel/intel_bufmgr.h | 8 ++++++-
  31. intel/intel_bufmgr_gem.c | 54 +++++++++++++++++++++++++++++++++++++++++++----
  32. intel/intel_bufmgr_priv.h | 11 ++++++++++
  33. 5 files changed, 94 insertions(+), 6 deletions(-)
  34.  
  35. diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
  36. index ded43b1..426b25c 100644
  37. --- a/include/drm/i915_drm.h
  38. +++ b/include/drm/i915_drm.h
  39. @@ -680,7 +680,8 @@ struct drm_i915_gem_exec_object2 {
  40. #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
  41. #define EXEC_OBJECT_NEEDS_GTT (1<<1)
  42. #define EXEC_OBJECT_WRITE (1<<2)
  43. -#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
  44. +#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
  45. +#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_SUPPORTS_48B_ADDRESS<<1)
  46. __u64 flags;
  47.  
  48. __u64 rsvd1;
  49. diff --git a/intel/intel_bufmgr.c b/intel/intel_bufmgr.c
  50. index 14ea9f9..590a855 100644
  51. --- a/intel/intel_bufmgr.c
  52. +++ b/intel/intel_bufmgr.c
  53. @@ -188,6 +188,18 @@ drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
  54. return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
  55. }
  56.  
  57. +void drm_intel_bo_set_supports_48b_address(drm_intel_bo *bo)
  58. +{
  59. + if (bo->bufmgr->bo_set_supports_48b_address)
  60. + bo->bufmgr->bo_set_supports_48b_address(bo);
  61. +}
  62. +
  63. +void drm_intel_bo_clear_supports_48b_address(drm_intel_bo *bo)
  64. +{
  65. + if (bo->bufmgr->bo_clear_supports_48b_address)
  66. + bo->bufmgr->bo_clear_supports_48b_address(bo);
  67. +}
  68. +
  69. int
  70. drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
  71. {
  72. @@ -202,6 +214,18 @@ drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
  73. drm_intel_bo *target_bo, uint32_t target_offset,
  74. uint32_t read_domains, uint32_t write_domain)
  75. {
  76. + drm_intel_bo_clear_supports_48b_address(target_bo);
  77. + return bo->bufmgr->bo_emit_reloc(bo, offset,
  78. + target_bo, target_offset,
  79. + read_domains, write_domain);
  80. +}
  81. +
  82. +int
  83. +drm_intel_bo_emit_reloc_48bit(drm_intel_bo *bo, uint32_t offset,
  84. + drm_intel_bo *target_bo, uint32_t target_offset,
  85. + uint32_t read_domains, uint32_t write_domain)
  86. +{
  87. + drm_intel_bo_set_supports_48b_address(target_bo);
  88. return bo->bufmgr->bo_emit_reloc(bo, offset,
  89. target_bo, target_offset,
  90. read_domains, write_domain);
  91. diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
  92. index 285919e..62480cb 100644
  93. --- a/intel/intel_bufmgr.h
  94. +++ b/intel/intel_bufmgr.h
  95. @@ -87,7 +87,8 @@ struct _drm_intel_bo {
  96. /**
  97. * Last seen card virtual address (offset from the beginning of the
  98. * aperture) for the object. This should be used to fill relocation
  99. - * entries when calling drm_intel_bo_emit_reloc()
  100. + * entries when calling drm_intel_bo_emit_reloc() or
  101. + * drm_intel_bo_emit_reloc_48bit()
  102. */
  103. uint64_t offset64;
  104. };
  105. @@ -137,6 +138,8 @@ void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
  106.  
  107. void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
  108. void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
  109. +void drm_intel_bo_set_supports_48b_address(drm_intel_bo *bo);
  110. +void drm_intel_bo_clear_supports_48b_address(drm_intel_bo *bo);
  111. int drm_intel_bo_exec(drm_intel_bo *bo, int used,
  112. struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
  113. int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
  114. @@ -147,6 +150,9 @@ int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
  115. int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
  116. drm_intel_bo *target_bo, uint32_t target_offset,
  117. uint32_t read_domains, uint32_t write_domain);
  118. +int drm_intel_bo_emit_reloc_48bit(drm_intel_bo *bo, uint32_t offset,
  119. + drm_intel_bo *target_bo, uint32_t target_offset,
  120. + uint32_t read_domains, uint32_t write_domain);
  121. int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
  122. drm_intel_bo *target_bo,
  123. uint32_t target_offset,
  124. diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
  125. index 60c06fc..e3e2b0e 100644
  126. --- a/intel/intel_bufmgr_gem.c
  127. +++ b/intel/intel_bufmgr_gem.c
  128. @@ -143,6 +143,7 @@ typedef struct _drm_intel_bufmgr_gem {
  129. } drm_intel_bufmgr_gem;
  130.  
  131. #define DRM_INTEL_RELOC_FENCE (1<<0)
  132. +#define DRM_INTEL_RELOC_SUPPORTS_48B_ADDRESS (2<<0)
  133.  
  134. typedef struct _drm_intel_reloc_target_info {
  135. drm_intel_bo *bo;
  136. @@ -240,6 +241,14 @@ struct _drm_intel_bo_gem {
  137. bool is_userptr;
  138.  
  139. /**
  140. + * Boolean of whether this buffer can be in the whole 48-bit address.
  141. + *
  142. + * By default, buffers will be keep in a 32-bit range, unless this
  143. + * flag is explicitly set.
  144. + */
  145. + bool supports_48b_address;
  146. +
  147. + /**
  148. * Size in bytes of this buffer and its relocation descendents.
  149. *
  150. * Used to avoid costly tree walking in
  151. @@ -471,13 +480,18 @@ drm_intel_add_validate_buffer(drm_intel_bo *bo)
  152. }
  153.  
  154. static void
  155. -drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
  156. +drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence,
  157. + int supports_48b_address)
  158. {
  159. drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
  160. drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
  161. int index;
  162.  
  163. if (bo_gem->validate_index != -1) {
  164. + if (supports_48b_address) {
  165. + bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
  166. + EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
  167. + }
  168. if (need_fence)
  169. bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
  170. EXEC_OBJECT_NEEDS_FENCE;
  171. @@ -516,6 +530,10 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
  172. bufmgr_gem->exec2_objects[index].flags |=
  173. EXEC_OBJECT_NEEDS_FENCE;
  174. }
  175. + if (supports_48b_address) {
  176. + bufmgr_gem->exec2_objects[index].flags |=
  177. + EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
  178. + }
  179. bufmgr_gem->exec_count++;
  180. }
  181.  
  182. @@ -1931,11 +1949,33 @@ do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
  183. else
  184. bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
  185.  
  186. + if (target_bo_gem->supports_48b_address)
  187. + bo_gem->reloc_target_info[bo_gem->reloc_count].flags |=
  188. + DRM_INTEL_RELOC_SUPPORTS_48B_ADDRESS;
  189. +
  190. bo_gem->reloc_count++;
  191.  
  192. return 0;
  193. }
  194.  
  195. +static void drm_intel_gem_bo_set_supports_48b_address(drm_intel_bo *bo)
  196. +{
  197. + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
  198. + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
  199. +
  200. + if (bufmgr_gem->gen >= 8)
  201. + bo_gem->supports_48b_address = 1;
  202. +}
  203. +
  204. +static void drm_intel_gem_bo_clear_supports_48b_address(drm_intel_bo *bo)
  205. +{
  206. + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
  207. + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
  208. +
  209. + if (bufmgr_gem->gen >= 8)
  210. + bo_gem->supports_48b_address = 0;
  211. +}
  212. +
  213. static int
  214. drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
  215. drm_intel_bo *target_bo, uint32_t target_offset,
  216. @@ -2049,7 +2089,7 @@ drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
  217.  
  218. for (i = 0; i < bo_gem->reloc_count; i++) {
  219. drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
  220. - int need_fence;
  221. + int need_fence, supports_48b_addr;
  222.  
  223. if (target_bo == bo)
  224. continue;
  225. @@ -2062,8 +2102,12 @@ drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
  226. need_fence = (bo_gem->reloc_target_info[i].flags &
  227. DRM_INTEL_RELOC_FENCE);
  228.  
  229. + supports_48b_addr = (bo_gem->reloc_target_info[i].flags &
  230. + DRM_INTEL_RELOC_SUPPORTS_48B_ADDRESS);
  231. +
  232. /* Add the target to the validate list */
  233. - drm_intel_add_validate_buffer2(target_bo, need_fence);
  234. + drm_intel_add_validate_buffer2(target_bo, need_fence,
  235. + supports_48b_addr);
  236. }
  237. }
  238.  
  239. @@ -2508,7 +2552,7 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
  240. /* Add the batch buffer to the validation list. There are no relocations
  241. * pointing to it.
  242. */
  243. - drm_intel_add_validate_buffer2(bo, 0);
  244. + drm_intel_add_validate_buffer2(bo, 0, 0);
  245.  
  246. memclear(execbuf);
  247. execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
  248. @@ -3657,6 +3701,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
  249. bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
  250. bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
  251. bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
  252. + bufmgr_gem->bufmgr.bo_set_supports_48b_address = drm_intel_gem_bo_set_supports_48b_address;
  253. + bufmgr_gem->bufmgr.bo_clear_supports_48b_address = drm_intel_gem_bo_clear_supports_48b_address;
  254. bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
  255. bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
  256. bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
  257. diff --git a/intel/intel_bufmgr_priv.h b/intel/intel_bufmgr_priv.h
  258. index 59ebd18..774fa02 100644
  259. --- a/intel/intel_bufmgr_priv.h
  260. +++ b/intel/intel_bufmgr_priv.h
  261. @@ -152,6 +152,17 @@ struct _drm_intel_bufmgr {
  262. void (*destroy) (drm_intel_bufmgr *bufmgr);
  263.  
  264. /**
  265. + * Set/Clear 48-bit address support flag in a given bo.
  266. + *
  267. + * Any resource used with flat/heapless (0x00000000-0xfffff000)
  268. + * General State Heap (GSH) or Intructions State Heap (ISH) must
  269. + * be in a 32-bit range. 48-bit range will only be used when explicitly
  270. + * requested.
  271. + */
  272. + void (*bo_set_supports_48b_address) (drm_intel_bo *bo);
  273. + void (*bo_clear_supports_48b_address) (drm_intel_bo *bo);
  274. +
  275. + /**
  276. * Add relocation entry in reloc_buf, which will be updated with the
  277. * target buffer's real offset on on command submission.
  278. *
  279. --
  280. 2.4.5
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