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  1. /{
  2. power-domains {
  3. pd_r5_0: pd_r5_0 {
  4. Send Feedback
  5. Libmetal and OpenAMP 16
  6. UG1186 (v2018.1) April 18, 2018 www.xilinx.com
  7. Chapter 2: Libmetal
  8. #power-domain-cells = <0x0>;
  9. pd-id = <0x7>;
  10. };
  11. pd_tcm_0_a: pd_tcm_0_a {
  12. #power-domain-cells = <0x0>;
  13. pd-id = <0xf>;
  14. };
  15. pd_tcm_0_b: pd_tcm_0_b {
  16. #power-domain-cells = <0x0>;
  17. pd-id = <0x10>;
  18. };
  19. };
  20. amba {
  21. /* firmware memory nodes */
  22. r5_0_tcm_a: tcm@ffe00000 {
  23. compatible = "mmio-sram";
  24. reg = <0x0 0xFFE00000 0x0 0x10000>;
  25. pd-handle = <&pd_tcm_0_a>;
  26. };
  27. r5_0_tcm_b: tcm@ffe20000 {
  28. compatible = "mmio-sram";
  29. reg = <0x0 0xFFE20000 0x0 0x10000>;
  30. pd-handle = <&pd_tcm_0_b>;
  31. };
  32. elf_ddr_0: ddr@3ed00000 {
  33. compatible = "mmio-sram";
  34. reg = <0x0 0x3ed00000 0x0 0x100000>;
  35. };
  36. test_r5_0: zynqmp_r5_rproc@0 {
  37. compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
  38. reg = <0x0 0xff9a0100 0x0 0x100>,
  39. <0x0 0xff9a0000 0x0 0x100>;
  40. reg-names = "rpu_base", "rpu_glbl_base";
  41. dma-ranges;
  42. core_conf = "split0";
  43. srams = <&r5_0_tcm_a &r5_0_tcm_b &elf_ddr_0>;
  44. pd-handle = <&pd_r5_0>;
  45. };
  46. };
  47. };
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