module mean_signal(up,lo,clk,mean);
input signed [15:0] up,lo;
input clk;
output reg signed [15:0] mean;

    reg [15:0] ans    ;
    reg [15:0] abs_ans;

always @(posedge clk)
    begin
//        assign ans=(up-lo);
ans=(up-lo);
         if (ans[15] == 1'b1) begin
            abs_ans = -ans;
          end
          else begin
            abs_ans = ans;
          end
//         assign mean=abs_ans/2;
mean=abs_ans/2;

//         if(mean==15'dx)
//            mean=0;
//         else
//            mean=mean;
    end


endmodule