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  1. /*
  2. * Copyright 2016 Lothar Waßmann <[email protected]>
  3. * Copyright 2016-2017 Oliver Wendt <[email protected]>
  4. * Copyright 2016 Michael Vyskocil <[email protected]>
  5. *
  6. * This file is dual-licensed: you can use it either under the terms
  7. * of the GPL or the X11 license, at your option. Note that this dual
  8. * licensing only applies to this file, and not this project as a
  9. * whole.
  10. *
  11. * a) This file is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This file is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * Or, alternatively,
  21. *
  22. * b) Permission is hereby granted, free of charge, to any person
  23. * obtaining a copy of this software and associated documentation
  24. * files (the "Software"), to deal in the Software without
  25. * restriction, including without limitation the rights to use,
  26. * copy, modify, merge, publish, distribute, sublicense, and/or
  27. * sell copies of the Software, and to permit persons to whom the
  28. * Software is furnished to do so, subject to the following
  29. * conditions:
  30. *
  31. * The above copyright notice and this permission notice shall be
  32. * included in all copies or substantial portions of the Software.
  33. *
  34. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41. * OTHER DEALINGS IN THE SOFTWARE.
  42. */
  43.  
  44. /*
  45. * Please be reminded that in general DTSI file(s) are include files that are
  46. * for more than one purpose (usually bound to a SoC) and as such shouldn't be
  47. * edited. For end-user products it should be the DTS file(s) that choose which
  48. * devices and pins are active and setup.
  49. *
  50. * The setup of DT files for Ka-Ro TX COM Modules under Yocto follow a
  51. * different, non-standard, implementation, which can make it necessary.
  52. */
  53.  
  54. #include <dt-bindings/gpio/gpio.h>
  55. #include <dt-bindings/gpio/imx6qdl-tx6-gpio.h>
  56. #include <dt-bindings/input/input.h>
  57. #include <dt-bindings/pwm/pwm.h>
  58. #include <dt-bindings/sound/fsl-imx-audmux.h>
  59.  
  60. /*
  61. * Definitions for simpler referencing of TX's standard nodes
  62. */
  63.  
  64. /* On-board NVMe */
  65. #define TX_EMMC &usdhc4
  66. #define TX_NAND &gpmi
  67. /* bus connectors */
  68. #define TX_I2C &i2c3
  69. #define TX_CAN1 &can2
  70. #define TX_CAN2 &can1
  71. /* video & display */
  72. #define TX_LCD &lcd
  73. #define TX_LCD_FB &mxcfb0
  74. #define TX_LDB &ldb
  75. #define TX_LDB_FB1 &mxcfb1
  76. #define TX_LDB_FB2 &mxcfb2
  77. #define TX_PWM &pwm2
  78. #define TX_PWM1 &pwm2 /* First (1st) PWM used (TX's default) */
  79. #define TX_PWM2 &pwm1 /* Second (2nd) PWM used */
  80. /* NVM */
  81. #define TX_SD1 &usdhc1
  82. #define TX_SD2 &usdhc2
  83. #define TX_SPI &ecspi1
  84. #define TX_SSI1 &audmux
  85. #define TX_SSI_PIN &pinctrl_ssi1
  86. /* UART */
  87. #define TX_UART1 &uart1
  88. #define TX_UART2 &uart2
  89. #define TX_UART3 &uart3
  90. /* USB */
  91. #define TX_USBH &usbh1
  92. #define TX_USBOTG &usbotg
  93.  
  94. / {
  95. aliases {
  96. can0 = &can2;
  97. can1 = &can1;
  98. emmc = &usdhc4;
  99. ethernet0 = &fec;
  100. sdhc0 = &usdhc1;
  101. sdhc1 = &usdhc2;
  102. usbh = &usbh1;
  103. usbotg = &usbotg;
  104. };
  105.  
  106. memory {
  107. reg = <0 0>; /* will be filled by U-Boot */
  108. };
  109.  
  110. /* override imx6dl.dtsi gpu clock definition bug */
  111.  
  112. clocks {
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115.  
  116. mclk: clock {
  117. compatible = "fixed-clock";
  118. #clock-cells = <0>;
  119. clock-frequency = <26000000>;
  120. };
  121. };
  122.  
  123. chosen {
  124. stdout-path = TX_UART1;
  125. };
  126.  
  127. regulators {
  128. compatible = "simple-bus";
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131.  
  132. reg_3v3_etn: regulator-3v3etn {
  133. compatible = "regulator-fixed";
  134. regulator-name = "3V3_ETN";
  135. regulator-min-microvolt = <3300000>;
  136. regulator-max-microvolt = <3300000>;
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&pinctrl_etnphy_power>;
  139. gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  140. enable-active-high;
  141. };
  142.  
  143. reg_usbh1_vbus: regulator-usbh1vbus {
  144. compatible = "regulator-fixed";
  145. regulator-name = "usbh1_vbus";
  146. regulator-min-microvolt = <5000000>;
  147. regulator-max-microvolt = <5000000>;
  148. pinctrl-names = "default";
  149. pinctrl-0 = <&pinctrl_usbh1_vbus>;
  150. gpio = <TX_GPIO_PIN27 GPIO_ACTIVE_HIGH>;
  151. enable-active-high;
  152. };
  153.  
  154. reg_usbotg_vbus: regulator-usbotgvbus {
  155. compatible = "regulator-fixed";
  156. regulator-name = "usbotg_vbus";
  157. regulator-min-microvolt = <5000000>;
  158. regulator-max-microvolt = <5000000>;
  159. pinctrl-names = "default";
  160. pinctrl-0 = <&pinctrl_usbotg_vbus>;
  161. gpio = <TX_GPIO_PIN34 GPIO_ACTIVE_HIGH>;
  162. enable-active-high;
  163. };
  164. };
  165.  
  166. lcd: lcd@0 {
  167. status = "disabled";
  168. };
  169.  
  170. mxcfb0: fb@0 {
  171. compatible = "fsl,mxc_sdc_fb";
  172. disp_dev = "lcd";
  173. interface_pix_fmt = "RGB24";
  174. default_bpp = <16>;
  175. int_clk = <0>;
  176. late_init = <0>;
  177. status = "disabled";
  178. };
  179.  
  180. mxcfb1: fb@1 {
  181. compatible = "fsl,mxc_sdc_fb";
  182. disp_dev = "ldb";
  183. interface_pix_fmt = "RGB666";
  184. default_bpp = <16>;
  185. int_clk = <0>;
  186. late_init = <0>;
  187. status = "disabled";
  188. };
  189.  
  190. mxcfb2: fb@2 {
  191. compatible = "fsl,mxc_sdc_fb";
  192. disp_dev = "ldb";
  193. interface_pix_fmt = "RGB666";
  194. default_bpp = <16>;
  195. int_clk = <0>;
  196. late_init = <0>;
  197. status = "disabled";
  198. };
  199.  
  200. v4l2_cap_0 {
  201. compatible = "fsl,imx6q-v4l2-capture";
  202. ipu_id = <0>;
  203. csi_id = <0>;
  204. mclk_source = <0>;
  205. status = "disabled";
  206. };
  207.  
  208. v4l2_cap_1 {
  209. compatible = "fsl,imx6q-v4l2-capture";
  210. ipu_id = <0>;
  211. csi_id = <1>;
  212. mclk_source = <0>;
  213. status = "disabled";
  214. };
  215.  
  216. v4l2_out {
  217. compatible = "fsl,mxc_v4l2_output";
  218. status = "disabled";
  219. };
  220. };
  221.  
  222. &can1 {
  223. pinctrl-names = "default";
  224. pinctrl-0 = <&pinctrl_flexcan1>;
  225. status = "disabled";
  226. };
  227.  
  228. &can2 {
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&pinctrl_flexcan2>;
  231. status = "disabled";
  232. };
  233.  
  234. &clks {
  235. fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
  236. fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
  237. };
  238.  
  239. &dcic2 {
  240. dcic_id = <1>;
  241. dcic_mux = "dcic-lvds1";
  242. status = "okay";
  243. };
  244.  
  245. &ecspi1 {
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&pinctrl_ecspi1>;
  248. fsl,spi-num-chipselects = <2>;
  249. cs-gpios = <
  250. TX_GPIO_PIN44 GPIO_ACTIVE_HIGH
  251. TX_GPIO_PIN45 GPIO_ACTIVE_HIGH
  252. >;
  253. status = "okay";
  254.  
  255. spidev0: spi@0 {
  256. compatible = "spidev";
  257. reg = <0>;
  258. spi-max-frequency = <54000000>;
  259. };
  260.  
  261. spidev1: spi@1 {
  262. compatible = "spidev";
  263. reg = <1>;
  264. spi-max-frequency = <54000000>;
  265. };
  266. };
  267.  
  268. &fec {
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&pinctrl_enet>;
  271. clocks = <&clks IMX6QDL_CLK_ENET>,
  272. <&clks IMX6QDL_CLK_ENET>,
  273. <&clks IMX6QDL_CLK_ENET_REF>,
  274. <&clks IMX6QDL_CLK_ENET_REF>;
  275. clock-names = "ipg", "ahb", "ptp", "enet_out";
  276. ref-clock = <50000000>;
  277. phy-mode = "rmii";
  278. phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
  279. phy-handle = <&etnphy>;
  280. phy-supply = <&reg_3v3_etn>;
  281. status = "okay";
  282.  
  283. mdio {
  284. #address-cells = <1>;
  285. #size-cells = <0>;
  286.  
  287. etnphy: ethernet-phy@0 {
  288. compatible = "ethernet-phy-ieee802.3-c22";
  289. reg = <0>;
  290. interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>;
  291. status = "okay";
  292. };
  293. };
  294. };
  295.  
  296. &gpmi {
  297. pinctrl-names = "default";
  298. pinctrl-0 = <&pinctrl_gpmi_nand>;
  299. nand-on-flash-bbt;
  300. fsl,no-blockmark-swap;
  301. fsl,legacy-bch-geometry;
  302. status = "disabled";
  303. };
  304.  
  305. &i2c3 {
  306. pinctrl-names = "default";
  307. pinctrl-0 = <&pinctrl_i2c3>;
  308. clock-frequency = <400000>;
  309. status = "disabled";
  310. };
  311.  
  312. &pwm1 {
  313. pinctrl-names = "default";
  314. pinctrl-0 = <&pinctrl_pwm1>;
  315. status = "disabled";
  316. };
  317.  
  318. &pwm2 {
  319. pinctrl-names = "default";
  320. pinctrl-0 = <&pinctrl_pwm2>;
  321. status = "disabled";
  322. };
  323.  
  324. &reg_arm {
  325. /delete-property/ regulator-allow-bypass;
  326. };
  327.  
  328. &reg_pu {
  329. /delete-property/ regulator-allow-bypass;
  330. };
  331.  
  332. &reg_soc {
  333. /delete-property/ regulator-allow-bypass;
  334. };
  335.  
  336. &snvs_poweroff {
  337. status = "okay";
  338. };
  339.  
  340. &audmux {
  341. status = "okay";
  342.  
  343. ssi1 {
  344. fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>;
  345. fsl,port-config = <
  346. 0x00000000
  347. IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT5_SSI_PINS_5)
  348. >;
  349. };
  350.  
  351.  
  352. aud5 {
  353. fsl,audmux-port = <MX31_AUDMUX_PORT5_SSI_PINS_5>;
  354. fsl,port-config = <
  355. (IMX_AUDMUX_V2_PTCR_TFSDIR |
  356. IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT1_SSI0) |
  357. IMX_AUDMUX_V2_PTCR_TCLKDIR |
  358. IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT1_SSI0))
  359. IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0)
  360. >;
  361. };
  362. };
  363.  
  364. &ssi1 {
  365. fsl,mode = "i2s-master";
  366. assigned-clocks = <&clks IMX6QDL_CLK_SSI1_SEL>, <&clks IMX6QDL_CLK_SSI1>;
  367. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
  368. assigned-clock-rates = <0>, <49152000>; // 48kHz on SSI1 clock
  369. status = "okay";
  370. };
  371.  
  372. &ssi2 {
  373. status = "okay";
  374. };
  375.  
  376. &uart1 {
  377. pinctrl-names = "default";
  378. pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
  379. status = "disabled";
  380. };
  381.  
  382. &uart2 {
  383. pinctrl-names = "default";
  384. pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
  385. status = "disabled";
  386. };
  387.  
  388. &uart3 {
  389. pinctrl-names = "default";
  390. pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
  391. status = "disabled";
  392. };
  393.  
  394. &usbotg {
  395. vbus-supply = <&reg_usbotg_vbus>;
  396. pinctrl-names = "default";
  397. pinctrl-0 = <&pinctrl_usbotg>;
  398. dr_mode = "peripheral";
  399. disable-over-current;
  400. status = "disabled";
  401. };
  402.  
  403. &usbh1 {
  404. vbus-supply = <&reg_usbh1_vbus>;
  405. dr_mode = "host";
  406. disable-over-current;
  407. status = "disabled";
  408. };
  409.  
  410. &usdhc1 {
  411. pinctrl-names = "default";
  412. pinctrl-0 = <&pinctrl_usdhc1>;
  413. bus-width = <4>;
  414. no-1-8-v;
  415. cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
  416. fsl,wp-controller;
  417. status = "disabled";
  418. };
  419.  
  420. &usdhc2 {
  421. pinctrl-names = "default";
  422. pinctrl-0 = <&pinctrl_usdhc2>;
  423. bus-width = <4>;
  424. no-1-8-v;
  425. cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
  426. fsl,wp-controller;
  427. status = "disabled";
  428. };
  429.  
  430. &usdhc4 {
  431. pinctrl-names = "default";
  432. pinctrl-0 = <&pinctrl_usdhc4>;
  433. bus-width = <4>;
  434. non-removable;
  435. no-1-8-v;
  436. fsl,wp-controller;
  437. status = "disabled";
  438. };
  439.  
  440. &iomuxc {
  441. pinctrl-names = "default";
  442. pinctrl-0 = <&pinctrl_hog>;
  443.  
  444. tx6 {
  445. pinctrl_hog: hoggrp {
  446. fsl,pins = <
  447. MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
  448. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
  449. >;
  450. };
  451.  
  452. pinctrl_ssi1: audmuxgrp {
  453. fsl,pins = <
  454. MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
  455. MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
  456. MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
  457. MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
  458. >;
  459. };
  460.  
  461. pinctrl_ecspi1: ecspi1grp {
  462. fsl,pins = <
  463. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
  464. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
  465. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
  466. MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
  467. MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
  468. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
  469. >;
  470. };
  471.  
  472. pinctrl_enet: enetgrp {
  473. fsl,pins = <
  474. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  475. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  476. MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
  477. MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
  478. MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
  479. MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
  480. MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
  481. MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
  482. MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
  483. >;
  484. };
  485.  
  486. pinctrl_etnphy_power: etnphy-pwrgrp {
  487. fsl,pins = <
  488. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
  489. >;
  490. };
  491.  
  492. pinctrl_flexcan1: flexcan1grp {
  493. fsl,pins = <
  494. MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
  495. MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
  496. >;
  497. };
  498.  
  499. pinctrl_flexcan2: flexcan2grp {
  500. fsl,pins = <
  501. MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
  502. MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
  503. >;
  504. };
  505.  
  506. pinctrl_gpmi_nand: gpminandgrp {
  507. fsl,pins = <
  508. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
  509. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
  510. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
  511. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
  512. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
  513. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
  514. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
  515. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
  516. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
  517. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
  518. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
  519. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
  520. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
  521. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
  522. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
  523. >;
  524. };
  525.  
  526. pinctrl_i2c3: i2c3grp {
  527. fsl,pins = <
  528. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  529. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  530. >;
  531. };
  532.  
  533. pinctrl_ipu1: ipu1grp {
  534. fsl,pins = <
  535. MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  536. MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  537. MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  538. MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  539. MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
  540. MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  541. MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  542. MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  543. MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  544. MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  545. MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  546. MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  547. MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  548. MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  549. MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  550. MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  551. MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  552. MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  553. MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  554. MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  555. MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  556. MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  557. MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  558. MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  559. MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  560. MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  561. MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  562. MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  563. MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  564. >;
  565. };
  566.  
  567. pinctrl_pwm1: pwm1grp {
  568. fsl,pins = <
  569. MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  570. >;
  571. };
  572.  
  573. pinctrl_pwm2: pwm2grp {
  574. fsl,pins = <
  575. MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
  576. >;
  577. };
  578.  
  579. pinctrl_uart1: uart1grp {
  580. fsl,pins = <
  581. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  582. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  583. >;
  584. };
  585.  
  586. pinctrl_uart1_rtscts: uart1_rtsctsgrp {
  587. fsl,pins = <
  588. MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
  589. MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
  590. >;
  591. };
  592.  
  593. pinctrl_uart2: uart2grp {
  594. fsl,pins = <
  595. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  596. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  597. >;
  598. };
  599.  
  600. pinctrl_uart2_rtscts: uart2_rtsctsgrp {
  601. fsl,pins = <
  602. MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
  603. MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
  604. >;
  605. };
  606.  
  607. pinctrl_uart3: uart3grp {
  608. fsl,pins = <
  609. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  610. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  611. >;
  612. };
  613.  
  614. pinctrl_uart3_rtscts: uart3_rtsctsgrp {
  615. fsl,pins = <
  616. MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
  617. MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
  618. >;
  619. };
  620.  
  621. pinctrl_usbh1_vbus: usbh1-vbusgrp {
  622. fsl,pins = <
  623. MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
  624. >;
  625. };
  626.  
  627. pinctrl_usbotg: usbotggrp {
  628. fsl,pins = <
  629. MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
  630. >;
  631. };
  632.  
  633. pinctrl_usbotg_vbus: usbotg-vbusgrp {
  634. fsl,pins = <
  635. MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
  636. >;
  637. };
  638.  
  639. pinctrl_usdhc1: usdhc1grp {
  640. fsl,pins = <
  641. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
  642. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
  643. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
  644. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
  645. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
  646. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
  647. MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
  648. >;
  649. };
  650.  
  651. pinctrl_usdhc2: usdhc2grp {
  652. fsl,pins = <
  653. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
  654. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
  655. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
  656. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
  657. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
  658. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
  659. MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
  660. >;
  661. };
  662.  
  663. pinctrl_usdhc4: usdhc4grp {
  664. fsl,pins = <
  665. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
  666. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
  667. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
  668. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
  669. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
  670. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
  671. MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
  672. >;
  673. };
  674. };
  675. };
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