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  1. /*
  2. Copyright (c) 1998 - 2002 Frodo Looijaard <[email protected]> and
  3. Philip Edelbrock <[email protected]>
  4.  
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9.  
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. GNU General Public License for more details.
  14. */
  15.  
  16. /*
  17. Supports:
  18. Intel PIIX4, 440MX
  19. Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
  20. ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
  21. AMD Hudson-2, ML, CZ
  22. SMSC Victory66
  23.  
  24. Note: we assume there can only be one device, with one or more
  25. SMBus interfaces.
  26. The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
  27. For devices supporting multiple ports the i2c_adapter should provide
  28. an i2c_algorithm to access them.
  29. */
  30.  
  31. #include <linux/module.h>
  32. #include <linux/moduleparam.h>
  33. #include <linux/pci.h>
  34. #include <linux/kernel.h>
  35. #include <linux/delay.h>
  36. #include <linux/stddef.h>
  37. #include <linux/ioport.h>
  38. #include <linux/i2c.h>
  39. #include <linux/slab.h>
  40. #include <linux/dmi.h>
  41. #include <linux/acpi.h>
  42. #include <linux/io.h>
  43.  
  44.  
  45. /* PIIX4 SMBus address offsets */
  46. #define SMBHSTSTS (0 + piix4_smba)
  47. #define SMBHSLVSTS (1 + piix4_smba)
  48. #define SMBHSTCNT (2 + piix4_smba)
  49. #define SMBHSTCMD (3 + piix4_smba)
  50. #define SMBHSTADD (4 + piix4_smba)
  51. #define SMBHSTDAT0 (5 + piix4_smba)
  52. #define SMBHSTDAT1 (6 + piix4_smba)
  53. #define SMBBLKDAT (7 + piix4_smba)
  54. #define SMBSLVCNT (8 + piix4_smba)
  55. #define SMBSHDWCMD (9 + piix4_smba)
  56. #define SMBSLVEVT (0xA + piix4_smba)
  57. #define SMBSLVDAT (0xC + piix4_smba)
  58.  
  59. /* count for request_region */
  60. #define SMBIOSIZE 9
  61.  
  62. /* PCI Address Constants */
  63. #define SMBBA 0x090
  64. #define SMBHSTCFG 0x0D2
  65. #define SMBSLVC 0x0D3
  66. #define SMBSHDW1 0x0D4
  67. #define SMBSHDW2 0x0D5
  68. #define SMBREV 0x0D6
  69.  
  70. /* Other settings */
  71. #define MAX_TIMEOUT 500
  72. #define ENABLE_INT9 0
  73.  
  74. /* PIIX4 constants */
  75. #define PIIX4_QUICK 0x00
  76. #define PIIX4_BYTE 0x04
  77. #define PIIX4_BYTE_DATA 0x08
  78. #define PIIX4_WORD_DATA 0x0C
  79. #define PIIX4_BLOCK_DATA 0x14
  80.  
  81. /* Multi-port constants */
  82. #define PIIX4_MAX_ADAPTERS 4
  83.  
  84. /* SB800 constants */
  85. #define SB800_PIIX4_SMB_IDX 0xcd6
  86.  
  87. #define KERNCZ_IMC_IDX 0x3e
  88. #define KERNCZ_IMC_DATA 0x3f
  89.  
  90. /*
  91. * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
  92. * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
  93. * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
  94. */
  95. #define SB800_PIIX4_PORT_IDX 0x2c
  96. #define SB800_PIIX4_PORT_IDX_ALT 0x2e
  97. #define SB800_PIIX4_PORT_IDX_SEL 0x2f
  98. #define SB800_PIIX4_PORT_IDX_MASK 0x06
  99. #define SB800_PIIX4_PORT_IDX_SHIFT 1
  100.  
  101. /* On kerncz, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
  102. #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
  103. #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
  104. #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
  105.  
  106. /* insmod parameters */
  107.  
  108. /* If force is set to anything different from 0, we forcibly enable the
  109. PIIX4. DANGEROUS! */
  110. static int force;
  111. module_param (force, int, 0);
  112. MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
  113.  
  114. /* If force_addr is set to anything different from 0, we forcibly enable
  115. the PIIX4 at the given address. VERY DANGEROUS! */
  116. static int force_addr;
  117. module_param_hw(force_addr, int, ioport, 0);
  118. MODULE_PARM_DESC(force_addr,
  119. "Forcibly enable the PIIX4 at the given address. "
  120. "EXTREMELY DANGEROUS!");
  121.  
  122. static int srvrworks_csb5_delay;
  123. static struct pci_driver piix4_driver;
  124.  
  125. static const struct dmi_system_id piix4_dmi_blacklist[] = {
  126. {
  127. .ident = "Sapphire AM2RD790",
  128. .matches = {
  129. DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
  130. DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
  131. },
  132. },
  133. {
  134. .ident = "DFI Lanparty UT 790FX",
  135. .matches = {
  136. DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
  137. DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
  138. },
  139. },
  140. { }
  141. };
  142.  
  143. /* The IBM entry is in a separate table because we only check it
  144. on Intel-based systems */
  145. static const struct dmi_system_id piix4_dmi_ibm[] = {
  146. {
  147. .ident = "IBM",
  148. .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
  149. },
  150. { },
  151. };
  152.  
  153. /*
  154. * SB800 globals
  155. */
  156. static u8 piix4_port_sel_sb800;
  157. static u8 piix4_port_mask_sb800;
  158. static u8 piix4_port_shift_sb800;
  159. static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
  160. " port 0", " port 2", " port 3", " port 4"
  161. };
  162. static const char *piix4_aux_port_name_sb800 = " port 1";
  163.  
  164. struct i2c_piix4_adapdata {
  165. unsigned short smba;
  166.  
  167. /* SB800 */
  168. bool sb800_main;
  169. bool notify_imc;
  170. u8 port; /* Port number, shifted */
  171. };
  172.  
  173. static int piix4_setup(struct pci_dev *PIIX4_dev,
  174. const struct pci_device_id *id)
  175. {
  176. unsigned char temp;
  177. unsigned short piix4_smba;
  178.  
  179. if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
  180. (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
  181. srvrworks_csb5_delay = 1;
  182.  
  183. /* On some motherboards, it was reported that accessing the SMBus
  184. caused severe hardware problems */
  185. if (dmi_check_system(piix4_dmi_blacklist)) {
  186. dev_err(&PIIX4_dev->dev,
  187. "Accessing the SMBus on this system is unsafe!\n");
  188. return -EPERM;
  189. }
  190.  
  191. /* Don't access SMBus on IBM systems which get corrupted eeproms */
  192. if (dmi_check_system(piix4_dmi_ibm) &&
  193. PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
  194. dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
  195. "may corrupt your serial eeprom! Refusing to load "
  196. "module!\n");
  197. return -EPERM;
  198. }
  199.  
  200. /* Determine the address of the SMBus areas */
  201. if (force_addr) {
  202. piix4_smba = force_addr & 0xfff0;
  203. force = 0;
  204. } else {
  205. pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
  206. piix4_smba &= 0xfff0;
  207. if(piix4_smba == 0) {
  208. dev_err(&PIIX4_dev->dev, "SMBus base address "
  209. "uninitialized - upgrade BIOS or use "
  210. "force_addr=0xaddr\n");
  211. return -ENODEV;
  212. }
  213. }
  214.  
  215. if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
  216. return -ENODEV;
  217.  
  218. if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
  219. dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
  220. piix4_smba);
  221. return -EBUSY;
  222. }
  223.  
  224. pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
  225.  
  226. /* If force_addr is set, we program the new address here. Just to make
  227. sure, we disable the PIIX4 first. */
  228. if (force_addr) {
  229. pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
  230. pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
  231. pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
  232. dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
  233. "new address %04x!\n", piix4_smba);
  234. } else if ((temp & 1) == 0) {
  235. if (force) {
  236. /* This should never need to be done, but has been
  237. * noted that many Dell machines have the SMBus
  238. * interface on the PIIX4 disabled!? NOTE: This assumes
  239. * I/O space and other allocations WERE done by the
  240. * Bios! Don't complain if your hardware does weird
  241. * things after enabling this. :') Check for Bios
  242. * updates before resorting to this.
  243. */
  244. pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
  245. temp | 1);
  246. dev_notice(&PIIX4_dev->dev,
  247. "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
  248. } else {
  249. dev_err(&PIIX4_dev->dev,
  250. "SMBus Host Controller not enabled!\n");
  251. release_region(piix4_smba, SMBIOSIZE);
  252. return -ENODEV;
  253. }
  254. }
  255.  
  256. if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
  257. dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
  258. else if ((temp & 0x0E) == 0)
  259. dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
  260. else
  261. dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
  262. "(or code out of date)!\n");
  263.  
  264. pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
  265. dev_info(&PIIX4_dev->dev,
  266. "SMBus Host Controller at 0x%x, revision %d\n",
  267. piix4_smba, temp);
  268.  
  269. return piix4_smba;
  270. }
  271.  
  272. static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
  273. const struct pci_device_id *id, u8 aux)
  274. {
  275. unsigned short piix4_smba;
  276. u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel;
  277. u8 i2ccfg, i2ccfg_offset = 0x10;
  278.  
  279. /* SB800 and later SMBus does not support forcing address */
  280. if (force || force_addr) {
  281. dev_err(&PIIX4_dev->dev, "SMBus does not support "
  282. "forcing address!\n");
  283. return -EINVAL;
  284. }
  285.  
  286. /* Determine the address of the SMBus areas */
  287. if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
  288. PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
  289. PIIX4_dev->revision >= 0x41) ||
  290. (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
  291. PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
  292. PIIX4_dev->revision >= 0x49))
  293. smb_en = 0x00;
  294. else
  295. smb_en = (aux) ? 0x28 : 0x2c;
  296.  
  297. if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) {
  298. dev_err(&PIIX4_dev->dev,
  299. "SMB base address index region 0x%x already in use.\n",
  300. SB800_PIIX4_SMB_IDX);
  301. return -EBUSY;
  302. }
  303.  
  304. outb_p(smb_en, SB800_PIIX4_SMB_IDX);
  305. smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
  306. outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
  307. smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
  308.  
  309. release_region(SB800_PIIX4_SMB_IDX, 2);
  310.  
  311. if (!smb_en) {
  312. smb_en_status = smba_en_lo & 0x10;
  313. piix4_smba = smba_en_hi << 8;
  314. if (aux)
  315. piix4_smba |= 0x20;
  316. } else {
  317. smb_en_status = smba_en_lo & 0x01;
  318. piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
  319. }
  320.  
  321. if (!smb_en_status) {
  322. dev_err(&PIIX4_dev->dev,
  323. "SMBus Host Controller not enabled!\n");
  324. return -ENODEV;
  325. }
  326.  
  327. if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
  328. return -ENODEV;
  329.  
  330. if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
  331. dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
  332. piix4_smba);
  333. return -EBUSY;
  334. }
  335.  
  336. /* Aux SMBus does not support IRQ information */
  337. if (aux) {
  338. dev_info(&PIIX4_dev->dev,
  339. "Auxiliary SMBus Host Controller at 0x%x\n",
  340. piix4_smba);
  341. return piix4_smba;
  342. }
  343.  
  344. /* Request the SMBus I2C bus config region */
  345. if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
  346. dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
  347. "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
  348. release_region(piix4_smba, SMBIOSIZE);
  349. return -EBUSY;
  350. }
  351. i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
  352. release_region(piix4_smba + i2ccfg_offset, 1);
  353.  
  354. if (i2ccfg & 1)
  355. dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
  356. else
  357. dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
  358.  
  359. dev_info(&PIIX4_dev->dev,
  360. "SMBus Host Controller at 0x%x, revision %d\n",
  361. piix4_smba, i2ccfg >> 4);
  362.  
  363. /* Find which register is used for port selection */
  364. if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD) {
  365. switch (PIIX4_dev->device) {
  366. case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS:
  367. piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
  368. piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
  369. piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
  370. break;
  371. case PCI_DEVICE_ID_AMD_HUDSON2_SMBUS:
  372. default:
  373. piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
  374. piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
  375. piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
  376. break;
  377. }
  378. } else {
  379. if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2,
  380. "sb800_piix4_smb")) {
  381. release_region(piix4_smba, SMBIOSIZE);
  382. return -EBUSY;
  383. }
  384.  
  385. outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
  386. port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
  387. piix4_port_sel_sb800 = (port_sel & 0x01) ?
  388. SB800_PIIX4_PORT_IDX_ALT :
  389. SB800_PIIX4_PORT_IDX;
  390. piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
  391. piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
  392. release_region(SB800_PIIX4_SMB_IDX, 2);
  393. }
  394.  
  395. dev_info(&PIIX4_dev->dev,
  396. "Using register 0x%02x for SMBus port selection\n",
  397. (unsigned int)piix4_port_sel_sb800);
  398.  
  399. return piix4_smba;
  400. }
  401.  
  402. static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
  403. const struct pci_device_id *id,
  404. unsigned short base_reg_addr)
  405. {
  406. /* Set up auxiliary SMBus controllers found on some
  407. * AMD chipsets e.g. SP5100 (SB700 derivative) */
  408.  
  409. unsigned short piix4_smba;
  410.  
  411. /* Read address of auxiliary SMBus controller */
  412. pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
  413. if ((piix4_smba & 1) == 0) {
  414. dev_dbg(&PIIX4_dev->dev,
  415. "Auxiliary SMBus controller not enabled\n");
  416. return -ENODEV;
  417. }
  418.  
  419. piix4_smba &= 0xfff0;
  420. if (piix4_smba == 0) {
  421. dev_dbg(&PIIX4_dev->dev,
  422. "Auxiliary SMBus base address uninitialized\n");
  423. return -ENODEV;
  424. }
  425.  
  426. if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
  427. return -ENODEV;
  428.  
  429. if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
  430. dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
  431. "already in use!\n", piix4_smba);
  432. return -EBUSY;
  433. }
  434.  
  435. dev_info(&PIIX4_dev->dev,
  436. "Auxiliary SMBus Host Controller at 0x%x\n",
  437. piix4_smba);
  438.  
  439. return piix4_smba;
  440. }
  441.  
  442. static int piix4_transaction(struct i2c_adapter *piix4_adapter)
  443. {
  444. struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
  445. unsigned short piix4_smba = adapdata->smba;
  446. int temp;
  447. int result = 0;
  448. int timeout = 0;
  449.  
  450. dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
  451. "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
  452. inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
  453. inb_p(SMBHSTDAT1));
  454.  
  455. /* Make sure the SMBus host is ready to start transmitting */
  456. if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
  457. dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
  458. "Resetting...\n", temp);
  459. outb_p(temp, SMBHSTSTS);
  460. if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
  461. dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
  462. return -EBUSY;
  463. } else {
  464. dev_dbg(&piix4_adapter->dev, "Successful!\n");
  465. }
  466. }
  467.  
  468. /* start the transaction by setting bit 6 */
  469. outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
  470.  
  471. /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
  472. if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
  473. usleep_range(25, 50);
  474. else
  475. usleep_range(250, 500);
  476.  
  477. while ((++timeout < MAX_TIMEOUT) &&
  478. ((temp = inb_p(SMBHSTSTS)) & 0x01))
  479. usleep_range(25, 50);
  480.  
  481. /* If the SMBus is still busy, we give up */
  482. if (timeout == MAX_TIMEOUT) {
  483. dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
  484. result = -ETIMEDOUT;
  485. }
  486.  
  487. if (temp & 0x10) {
  488. result = -EIO;
  489. dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
  490. }
  491.  
  492. if (temp & 0x08) {
  493. result = -EIO;
  494. dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
  495. "locked until next hard reset. (sorry!)\n");
  496. /* Clock stops and slave is stuck in mid-transmission */
  497. }
  498.  
  499. if (temp & 0x04) {
  500. result = -ENXIO;
  501. dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
  502. }
  503.  
  504. if (inb_p(SMBHSTSTS) != 0x00)
  505. outb_p(inb(SMBHSTSTS), SMBHSTSTS);
  506.  
  507. if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
  508. dev_err(&piix4_adapter->dev, "Failed reset at end of "
  509. "transaction (%02x)\n", temp);
  510. }
  511. dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
  512. "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
  513. inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
  514. inb_p(SMBHSTDAT1));
  515. return result;
  516. }
  517.  
  518. /* Return negative errno on error. */
  519. static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
  520. unsigned short flags, char read_write,
  521. u8 command, int size, union i2c_smbus_data * data)
  522. {
  523. struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
  524. unsigned short piix4_smba = adapdata->smba;
  525. int i, len;
  526. int status;
  527.  
  528. switch (size) {
  529. case I2C_SMBUS_QUICK:
  530. outb_p((addr << 1) | read_write,
  531. SMBHSTADD);
  532. size = PIIX4_QUICK;
  533. break;
  534. case I2C_SMBUS_BYTE:
  535. outb_p((addr << 1) | read_write,
  536. SMBHSTADD);
  537. if (read_write == I2C_SMBUS_WRITE)
  538. outb_p(command, SMBHSTCMD);
  539. size = PIIX4_BYTE;
  540. break;
  541. case I2C_SMBUS_BYTE_DATA:
  542. outb_p((addr << 1) | read_write,
  543. SMBHSTADD);
  544. outb_p(command, SMBHSTCMD);
  545. if (read_write == I2C_SMBUS_WRITE)
  546. outb_p(data->byte, SMBHSTDAT0);
  547. size = PIIX4_BYTE_DATA;
  548. break;
  549. case I2C_SMBUS_WORD_DATA:
  550. outb_p((addr << 1) | read_write,
  551. SMBHSTADD);
  552. outb_p(command, SMBHSTCMD);
  553. if (read_write == I2C_SMBUS_WRITE) {
  554. outb_p(data->word & 0xff, SMBHSTDAT0);
  555. outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
  556. }
  557. size = PIIX4_WORD_DATA;
  558. break;
  559. case I2C_SMBUS_BLOCK_DATA:
  560. outb_p((addr << 1) | read_write,
  561. SMBHSTADD);
  562. outb_p(command, SMBHSTCMD);
  563. if (read_write == I2C_SMBUS_WRITE) {
  564. len = data->block[0];
  565. if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
  566. return -EINVAL;
  567. outb_p(len, SMBHSTDAT0);
  568. inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
  569. for (i = 1; i <= len; i++)
  570. outb_p(data->block[i], SMBBLKDAT);
  571. }
  572. size = PIIX4_BLOCK_DATA;
  573. break;
  574. default:
  575. dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
  576. return -EOPNOTSUPP;
  577. }
  578.  
  579. outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
  580.  
  581. status = piix4_transaction(adap);
  582. if (status)
  583. return status;
  584.  
  585. if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
  586. return 0;
  587.  
  588.  
  589. switch (size) {
  590. case PIIX4_BYTE:
  591. case PIIX4_BYTE_DATA:
  592. data->byte = inb_p(SMBHSTDAT0);
  593. break;
  594. case PIIX4_WORD_DATA:
  595. data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
  596. break;
  597. case PIIX4_BLOCK_DATA:
  598. data->block[0] = inb_p(SMBHSTDAT0);
  599. if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
  600. return -EPROTO;
  601. inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
  602. for (i = 1; i <= data->block[0]; i++)
  603. data->block[i] = inb_p(SMBBLKDAT);
  604. break;
  605. }
  606. return 0;
  607. }
  608.  
  609. static uint8_t piix4_imc_read(uint8_t idx)
  610. {
  611. outb_p(idx, KERNCZ_IMC_IDX);
  612. return inb_p(KERNCZ_IMC_DATA);
  613. }
  614.  
  615. static void piix4_imc_write(uint8_t idx, uint8_t value)
  616. {
  617. outb_p(idx, KERNCZ_IMC_IDX);
  618. outb_p(value, KERNCZ_IMC_DATA);
  619. }
  620.  
  621. static int piix4_imc_sleep(void)
  622. {
  623. int timeout = MAX_TIMEOUT;
  624.  
  625. if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
  626. return -EBUSY;
  627.  
  628. /* clear response register */
  629. piix4_imc_write(0x82, 0x00);
  630. /* request ownership flag */
  631. piix4_imc_write(0x83, 0xB4);
  632. /* kick off IMC Mailbox command 96 */
  633. piix4_imc_write(0x80, 0x96);
  634.  
  635. while (timeout--) {
  636. if (piix4_imc_read(0x82) == 0xfa) {
  637. release_region(KERNCZ_IMC_IDX, 2);
  638. return 0;
  639. }
  640. usleep_range(1000, 2000);
  641. }
  642.  
  643. release_region(KERNCZ_IMC_IDX, 2);
  644. return -ETIMEDOUT;
  645. }
  646.  
  647. static void piix4_imc_wakeup(void)
  648. {
  649. int timeout = MAX_TIMEOUT;
  650.  
  651. if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
  652. return;
  653.  
  654. /* clear response register */
  655. piix4_imc_write(0x82, 0x00);
  656. /* release ownership flag */
  657. piix4_imc_write(0x83, 0xB5);
  658. /* kick off IMC Mailbox command 96 */
  659. piix4_imc_write(0x80, 0x96);
  660.  
  661. while (timeout--) {
  662. if (piix4_imc_read(0x82) == 0xfa)
  663. break;
  664. usleep_range(1000, 2000);
  665. }
  666.  
  667. release_region(KERNCZ_IMC_IDX, 2);
  668. }
  669.  
  670. /*
  671. * Handles access to multiple SMBus ports on the SB800.
  672. * The port is selected by bits 2:1 of the smb_en register (0x2c).
  673. * Returns negative errno on error.
  674. *
  675. * Note: The selected port must be returned to the initial selection to avoid
  676. * problems on certain systems.
  677. */
  678. static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
  679. unsigned short flags, char read_write,
  680. u8 command, int size, union i2c_smbus_data *data)
  681. {
  682. struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
  683. unsigned short piix4_smba = adapdata->smba;
  684. int retries = MAX_TIMEOUT;
  685. int smbslvcnt;
  686. u8 smba_en_lo;
  687. u8 port;
  688. int retval;
  689.  
  690. if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb"))
  691. return -EBUSY;
  692.  
  693. /* Request the SMBUS semaphore, avoid conflicts with the IMC */
  694. smbslvcnt = inb_p(SMBSLVCNT);
  695. do {
  696. outb_p(smbslvcnt | 0x10, SMBSLVCNT);
  697.  
  698. /* Check the semaphore status */
  699. smbslvcnt = inb_p(SMBSLVCNT);
  700. if (smbslvcnt & 0x10)
  701. break;
  702.  
  703. usleep_range(1000, 2000);
  704. } while (--retries);
  705. /* SMBus is still owned by the IMC, we give up */
  706. if (!retries) {
  707. retval = -EBUSY;
  708. goto release;
  709. }
  710.  
  711. /*
  712. * Notify the IMC (Integrated Micro Controller) if required.
  713. * Among other responsibilities, the IMC is in charge of monitoring
  714. * the System fans and temperature sensors, and act accordingly.
  715. * All this is done through SMBus and can/will collide
  716. * with our transactions if they are long (BLOCK_DATA).
  717. * Therefore we need to request the ownership flag during those
  718. * transactions.
  719. */
  720. if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
  721. int ret;
  722.  
  723. ret = piix4_imc_sleep();
  724. switch (ret) {
  725. case -EBUSY:
  726. dev_warn(&adap->dev,
  727. "IMC base address index region 0x%x already in use.\n",
  728. KERNCZ_IMC_IDX);
  729. break;
  730. case -ETIMEDOUT:
  731. dev_warn(&adap->dev,
  732. "Failed to communicate with the IMC.\n");
  733. break;
  734. default:
  735. break;
  736. }
  737.  
  738. /* If IMC communication fails do not retry */
  739. if (ret) {
  740. dev_warn(&adap->dev,
  741. "Continuing without IMC notification.\n");
  742. adapdata->notify_imc = false;
  743. }
  744. }
  745.  
  746. outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
  747. smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
  748.  
  749. port = adapdata->port;
  750. if ((smba_en_lo & piix4_port_mask_sb800) != port)
  751. outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port,
  752. SB800_PIIX4_SMB_IDX + 1);
  753.  
  754. retval = piix4_access(adap, addr, flags, read_write,
  755. command, size, data);
  756.  
  757. outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1);
  758.  
  759. /* Release the semaphore */
  760. outb_p(smbslvcnt | 0x20, SMBSLVCNT);
  761.  
  762. if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
  763. piix4_imc_wakeup();
  764.  
  765. release:
  766. release_region(SB800_PIIX4_SMB_IDX, 2);
  767. return retval;
  768. }
  769.  
  770. static u32 piix4_func(struct i2c_adapter *adapter)
  771. {
  772. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  773. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  774. I2C_FUNC_SMBUS_BLOCK_DATA;
  775. }
  776.  
  777. static const struct i2c_algorithm smbus_algorithm = {
  778. .smbus_xfer = piix4_access,
  779. .functionality = piix4_func,
  780. };
  781.  
  782. static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
  783. .smbus_xfer = piix4_access_sb800,
  784. .functionality = piix4_func,
  785. };
  786.  
  787. static const struct pci_device_id piix4_ids[] = {
  788. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
  789. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
  790. { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
  791. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
  792. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
  793. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
  794. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
  795. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
  796. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
  797. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  798. PCI_DEVICE_ID_SERVERWORKS_OSB4) },
  799. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  800. PCI_DEVICE_ID_SERVERWORKS_CSB5) },
  801. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  802. PCI_DEVICE_ID_SERVERWORKS_CSB6) },
  803. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  804. PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
  805. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  806. PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
  807. { 0, }
  808. };
  809.  
  810. MODULE_DEVICE_TABLE (pci, piix4_ids);
  811.  
  812. static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
  813. static struct i2c_adapter *piix4_aux_adapter;
  814.  
  815. static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
  816. bool sb800_main, u8 port, bool notify_imc,
  817. const char *name, struct i2c_adapter **padap)
  818. {
  819. struct i2c_adapter *adap;
  820. struct i2c_piix4_adapdata *adapdata;
  821. int retval;
  822.  
  823. adap = kzalloc(sizeof(*adap), GFP_KERNEL);
  824. if (adap == NULL) {
  825. release_region(smba, SMBIOSIZE);
  826. return -ENOMEM;
  827. }
  828.  
  829. adap->owner = THIS_MODULE;
  830. adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  831. adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
  832. : &smbus_algorithm;
  833.  
  834. adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
  835. if (adapdata == NULL) {
  836. kfree(adap);
  837. release_region(smba, SMBIOSIZE);
  838. return -ENOMEM;
  839. }
  840.  
  841. adapdata->smba = smba;
  842. adapdata->sb800_main = sb800_main;
  843. adapdata->port = port << piix4_port_shift_sb800;
  844. adapdata->notify_imc = notify_imc;
  845.  
  846. /* set up the sysfs linkage to our parent device */
  847. adap->dev.parent = &dev->dev;
  848.  
  849. snprintf(adap->name, sizeof(adap->name),
  850. "SMBus PIIX4 adapter%s at %04x", name, smba);
  851.  
  852. i2c_set_adapdata(adap, adapdata);
  853.  
  854. retval = i2c_add_adapter(adap);
  855. if (retval) {
  856. kfree(adapdata);
  857. kfree(adap);
  858. release_region(smba, SMBIOSIZE);
  859. return retval;
  860. }
  861.  
  862. *padap = adap;
  863. return 0;
  864. }
  865.  
  866. static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
  867. bool notify_imc)
  868. {
  869. struct i2c_piix4_adapdata *adapdata;
  870. int port;
  871. int retval;
  872.  
  873. for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) {
  874. retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
  875. piix4_main_port_names_sb800[port],
  876. &piix4_main_adapters[port]);
  877. if (retval < 0)
  878. goto error;
  879. }
  880.  
  881. return retval;
  882.  
  883. error:
  884. dev_err(&dev->dev,
  885. "Error setting up SB800 adapters. Unregistering!\n");
  886. while (--port >= 0) {
  887. adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
  888. if (adapdata->smba) {
  889. i2c_del_adapter(piix4_main_adapters[port]);
  890. kfree(adapdata);
  891. kfree(piix4_main_adapters[port]);
  892. piix4_main_adapters[port] = NULL;
  893. }
  894. }
  895.  
  896. return retval;
  897. }
  898.  
  899. static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
  900. {
  901. int retval;
  902. bool is_sb800 = false;
  903.  
  904. if ((dev->vendor == PCI_VENDOR_ID_ATI &&
  905. dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
  906. dev->revision >= 0x40) ||
  907. dev->vendor == PCI_VENDOR_ID_AMD) {
  908. bool notify_imc = false;
  909. is_sb800 = true;
  910.  
  911. if (dev->vendor == PCI_VENDOR_ID_AMD &&
  912. dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
  913. u8 imc;
  914.  
  915. /*
  916. * Detect if IMC is active or not, this method is
  917. * described on coreboot's AMD IMC notes
  918. */
  919. pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
  920. 0x40, &imc);
  921. if (imc & 0x80)
  922. notify_imc = true;
  923. }
  924.  
  925. /* base address location etc changed in SB800 */
  926. retval = piix4_setup_sb800(dev, id, 0);
  927. if (retval < 0)
  928. return retval;
  929.  
  930. /*
  931. * Try to register multiplexed main SMBus adapter,
  932. * give up if we can't
  933. */
  934. retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
  935. if (retval < 0)
  936. return retval;
  937. } else {
  938. retval = piix4_setup(dev, id);
  939. if (retval < 0)
  940. return retval;
  941.  
  942. /* Try to register main SMBus adapter, give up if we can't */
  943. retval = piix4_add_adapter(dev, retval, false, 0, false, "",
  944. &piix4_main_adapters[0]);
  945. if (retval < 0)
  946. return retval;
  947. }
  948.  
  949. /* Check for auxiliary SMBus on some AMD chipsets */
  950. retval = -ENODEV;
  951.  
  952. if (dev->vendor == PCI_VENDOR_ID_ATI &&
  953. dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
  954. if (dev->revision < 0x40) {
  955. retval = piix4_setup_aux(dev, id, 0x58);
  956. } else {
  957. /* SB800 added aux bus too */
  958. retval = piix4_setup_sb800(dev, id, 1);
  959. }
  960. }
  961.  
  962. if (dev->vendor == PCI_VENDOR_ID_AMD &&
  963. dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) {
  964. retval = piix4_setup_sb800(dev, id, 1);
  965. }
  966.  
  967. if (dev->vendor == PCI_VENDOR_ID_AMD &&
  968. dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
  969. retval = piix4_setup_sb800(dev, id, 1);
  970. }
  971.  
  972. if (retval > 0) {
  973. /* Try to add the aux adapter if it exists,
  974. * piix4_add_adapter will clean up if this fails */
  975. piix4_add_adapter(dev, retval, false, 0, false,
  976. is_sb800 ? piix4_aux_port_name_sb800 : "",
  977. &piix4_aux_adapter);
  978. }
  979.  
  980. return 0;
  981. }
  982.  
  983. static void piix4_adap_remove(struct i2c_adapter *adap)
  984. {
  985. struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
  986.  
  987. if (adapdata->smba) {
  988. i2c_del_adapter(adap);
  989. if (adapdata->port == (0 << piix4_port_shift_sb800))
  990. release_region(adapdata->smba, SMBIOSIZE);
  991. kfree(adapdata);
  992. kfree(adap);
  993. }
  994. }
  995.  
  996. static void piix4_remove(struct pci_dev *dev)
  997. {
  998. int port = PIIX4_MAX_ADAPTERS;
  999.  
  1000. while (--port >= 0) {
  1001. if (piix4_main_adapters[port]) {
  1002. piix4_adap_remove(piix4_main_adapters[port]);
  1003. piix4_main_adapters[port] = NULL;
  1004. }
  1005. }
  1006.  
  1007. if (piix4_aux_adapter) {
  1008. piix4_adap_remove(piix4_aux_adapter);
  1009. piix4_aux_adapter = NULL;
  1010. }
  1011. }
  1012.  
  1013. static struct pci_driver piix4_driver = {
  1014. .name = "piix4_smbus",
  1015. .id_table = piix4_ids,
  1016. .probe = piix4_probe,
  1017. .remove = piix4_remove,
  1018. };
  1019.  
  1020. module_pci_driver(piix4_driver);
  1021.  
  1022. MODULE_AUTHOR("Frodo Looijaard <[email protected]> and "
  1023. "Philip Edelbrock <[email protected]>");
  1024. MODULE_DESCRIPTION("PIIX4 SMBus driver");
  1025. MODULE_LICENSE("GPL");
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