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- $ rm -rf build/sim; litex/litex/tools/litex_sim.py --cpu-type mor1kx
- INFO:SoC: __ _ __ _ __
- INFO:SoC: / / (_) /____ | |/_/
- INFO:SoC: / /__/ / __/ -_)> <
- INFO:SoC: /____/_/\__/\__/_/|_|
- INFO:SoC: Build your hardware, easily!
- INFO:SoC:--------------------------------------------------------------------------------
- INFO:SoC:Creating SoC... (2021-10-22 07:30:29)
- INFO:SoC:--------------------------------------------------------------------------------
- INFO:SoC:FPGA device : SIM.
- INFO:SoC:System clock: 1.000MHz.
- INFO:SoCBusHandler:Creating Bus Handler...
- INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
- INFO:SoCBusHandler:Adding reserved Bus Regions...
- INFO:SoCBusHandler:Bus Handler created.
- INFO:SoCCSRHandler:Creating CSR Handler...
- INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
- INFO:SoCCSRHandler:Adding reserved CSRs...
- INFO:SoCCSRHandler:CSR Handler created.
- INFO:SoCIRQHandler:Creating IRQ Handler...
- INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
- INFO:SoCIRQHandler:Adding reserved IRQs...
- INFO:SoCIRQHandler:IRQ Handler created.
- INFO:SoC:--------------------------------------------------------------------------------
- INFO:SoC:Initial SoC:
- INFO:SoC:--------------------------------------------------------------------------------
- INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
- INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
- INFO:SoC:IRQ Handler (up to 32 Locations).
- INFO:SoC:--------------------------------------------------------------------------------
- INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
- INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
- INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
- INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
- INFO:SoCBusHandler:rom added as Bus Slave.
- INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
- INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
- INFO:SoCBusHandler:sram added as Bus Slave.
- INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
- INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
- INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
- INFO:SoCBusHandler:csr Region added at Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
- INFO:SoCBusHandler:csr added as Bus Slave.
- INFO:SoCCSRHandler:bridge added as CSR Master.
- INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 3).
- INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
- INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
- INFO:SoCCSRHandler:timer0 CSR allocated at Location 2.
- INFO:SoCCSRHandler:uart CSR allocated at Location 3.
- INFO:SoC:--------------------------------------------------------------------------------
- INFO:SoC:Finalized SoC:
- INFO:SoC:--------------------------------------------------------------------------------
- INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
- IO Regions: (1)
- io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
- Bus Regions: (3)
- rom : Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False
- sram : Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
- csr : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
- Bus Masters: (2)
- - cpu_bus0
- - cpu_bus1
- Bus Slaves: (3)
- - rom
- - sram
- - csr
- INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
- CSR Locations: (4)
- - ctrl : 0
- - identifier_mem : 1
- - timer0 : 2
- - uart : 3
- INFO:SoC:IRQ Handler (up to 32 Locations).
- IRQ Locations: (2)
- - uart : 0
- - timer0 : 1
- INFO:SoC:--------------------------------------------------------------------------------
- Traceback (most recent call last):
- File "/home/somlo/LITEX/litex/litex/tools/litex_sim.py", line 477, in <module>
- main()
- File "/home/somlo/LITEX/litex/litex/tools/litex_sim.py", line 464, in main
- builder.build(
- File "/home/somlo/LITEX/litex/litex/soc/integration/builder.py", line 300, in build
- self._generate_includes(with_bios=with_bios)
- File "/home/somlo/LITEX/litex/litex/soc/integration/builder.py", line 169, in _generate_includes
- variables_contents = self._get_variables_contents()
- File "/home/somlo/LITEX/litex/litex/soc/integration/builder.py", line 139, in _get_variables_contents
- for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software):
- File "/home/somlo/LITEX/litex/litex/soc/integration/export.py", line 93, in get_cpu_mak
- ("TRIPLE", select_triple(triple)),
- File "/home/somlo/LITEX/litex/litex/soc/integration/export.py", line 88, in select_triple
- raise OSError(msg)
- OSError: Unable to find any of the cross compilation toolchains:
- - or1k-elf
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