Cover passes but assume fails

module test(
        input clock,
        input reset
);
`ifdef FORMAL
        wire x;
        initial f_past_valid = 1'b0;

        always @(posedge clock) begin
                f_past_valid <= 1'b1;
                if (reset) begin
                        f_past_valid <= 1'b0;
                end

                // works (comment out the assume)
                cover(f_past_valid && x == 1'b1);

                // doesn't work -- `Assumptions are unsatisfiable!`
                assume(f_past_valid && x == 1'b1);
        end
`endif
endmodule