`timescale 1ns/1ps

module AM(A, B, Sel, Out, Ovf);
input [3:0] A;
input [3:0] B;
input [3:0] Sel;
output reg [15:0] Out;
output reg Ovf;
wire [15:0] myout[15:0];
wire myovf[15:0];
priority m1(A, B, myout[0],myovf[0]);
myand m2(A,B,myout[1],myovf[1]);
myxor m3(A,B,myout[2],myovf[2]);
mymult m4(A,B,myout[3],myovf[3]);
ashiftr m5(A,B,myout[4],myovf[4]);
ashiftl m6(A,B,myout[5],myovf[5]);
lshiftr m7(A,B,myout[6],myovf[6]);
lshiftl m8(A,B,myout[7],myovf[7]);
twotofour m9(A,B,myout[8],myovf[8]);
fourtosixteen m10(A,B,myout[9],myovf[9]);
selectlarge m11(A,B,myout[10],myovf[10]);
selectsmall m12(A,B,myout[11],myovf[11]);
fulladder m13(A,B,myout[12],myovf[12]);
minus m14(A,B,myout[13],myovf[13]);
absolute m15(A,B,myout[14],myovf[14]);
bonus a1(A,B,myout[15],myovf[15]);
always@(*) begin
    case(Sel)
        0:begin
            Out=myout[0];
            Ovf=myovf[0];
        end
        1:begin
            Out=myout[1];
            Ovf=myovf[1];
        end

        2:begin
            Out=myout[2];
            Ovf=myovf[2];
        end

        3:begin
            Out=myout[3];
            Ovf=myovf[3];
        end

        4:begin
            Out=myout[4];
            Ovf=myovf[4];
        end

        5:begin
            Out=myout[5];
            Ovf=myovf[5];
        end

        6:begin
            Out=myout[6];
            Ovf=myovf[6];
        end

        7:begin
            Out=myout[7];
            Ovf=myovf[7];
        end

        8:begin
            Out=myout[8];
            Ovf=myovf[8];
        end

        9:begin
            Out=myout[9];
            Ovf=myovf[9];
        end

        10:begin
            Out=myout[10];
            Ovf=myovf[10];
        end

        11:begin
            Out=myout[11];
            Ovf=myovf[11];
        end

        12:begin
            Out=myout[12];
            Ovf=myovf[12];
        end

        13:begin
            Out=myout[13];
            Ovf=myovf[13];
        end

        14:begin
            Out=myout[14];
            Ovf=myovf[14];
        end
        15:begin
            Out=myout[15];
            Ovf=myovf[15];
        end


    endcase
end
//(your code)...

endmodule

module priority(a, b, out,ovf);
input [3:0] a;
input [3:0] b;
output reg [15:0] out;
output ovf;
assign ovf=0;
always@(*)begin
         out[15:3]=13'b0000000000000;
                case(a)
                     8,9,10,11,12,13,14,15:
                        out[2:0]=3'b111;
                     4,5,6,7:
                        out[2:0]=3'b110;
                     2,3:
                        out[2:0]=3'b101;
                     1:
                        out[2:0]=3'b100;

                default: begin
                case(b)
                     8,9,10,11,12,13,14,15:
                        out[2:0]=3'b011;
                     4,5,6,7:
                        out[2:0]=3'b010;
                     2,3:
                        out[2:0]=3'b001;
                     1:
                        out[2:0]=3'b000;
                    default:begin
                    end
                endcase
                end
                endcase
            end
endmodule

module myand(a,b,out,ovf);
input [3:0] a;
input [3:0] b;
output [15:0] out;
output ovf;
assign ovf=0;
    assign out[15:4]=12'b000000000000;
    and a1(out[3],a[3],b[3]);
    and a2(out[2],a[2],b[2]);
    and a3(out[1],a[1],b[1]);
    and a4(out[0],a[0],b[0]);
endmodule

module myxor(a,b,out,ovf);
input [3:0] a;
input [3:0] b;
output [15:0] out;
output ovf;
assign ovf=0;
    assign out[15:4]=12'b000000000000;
    xor a1(out[3],a[3],b[3]);
    xor a2(out[2],a[2],b[2]);
    xor a3(out[1],a[1],b[1]);
    xor a4(out[0],a[0],b[0]);

endmodule

module mymult(a,b,out,ovf);
    input signed [3:0] a;
    input signed [3:0] b;
    output signed [15:0] out;
    assign out=a*b;
    output ovf;
    assign ovf=0;
endmodule

module ashiftr(a,b,out,ovf);
    input signed [3:0] a;
    input signed [3:0] b;
    output signed [15:0] out;
    output ovf;
    assign ovf=0;
    assign out[15:4]=12'b000000000000;
    assign out[3]=a[3];
    assign out[2]=a[3];
    assign out[1]=a[2];
    assign out[0]=a[1];
endmodule

module ashiftl(a,b,out,ovf);
    input signed [3:0] a;
    input signed [3:0] b;
    output signed [15:0] out;
    output ovf;
    assign ovf=0;
    assign out[15:4]=12'b000000000000;
    assign out[3]=a[2];
    assign out[2]=a[1];
    assign out[1]=a[0];
    assign out[0]=0;
endmodule

module lshiftr(a,b,out,ovf);
    input signed [3:0] a;
    input signed [3:0] b;
    output signed [15:0] out;
    output ovf;
    assign ovf=0;
    assign out[15:4]=12'b000000000000;
    assign out[3]=0;
    assign out[2]=a[3];
    assign out[1]=a[2];
    assign out[0]=a[1];
endmodule

module lshiftl(a,b,out,ovf);
    input signed [3:0] a;
    input signed [3:0] b;
    output signed [15:0] out;
    output ovf;
    assign ovf=0;
    assign out[15:4]=12'b000000000000;
    assign out[3]=a[2];
    assign out[2]=a[1];
    assign out[1]=a[0];
    assign out[0]=0;
endmodule

module twotofour(a,b,out,ovf);
    input  [3:0] a;
    input  [3:0] b;
    output  [15:0] out;
    output ovf;
    wire nota,notb;
    buf b1(out[15],1'b0);
    buf b2(out[14],1'b0);
    buf b3(out[13],1'b0);
    buf b4(out[12],1'b0);
    buf b5(out[11],1'b0);
    buf b6(out[10],1'b0);
    buf b7(out[9],1'b0);
    buf b8(out[8],1'b0);
    buf b9(out[7],1'b0);
    buf b10(out[6],1'b0);
    buf b11(out[5],1'b0);
    buf b12(out[4],1'b0);
    buf b13(ovf,1'b0);
    not sadf(nota,a[3]);
    not dkek(notb,b[3]);
    and a1(out[3],a[3],b[3]);
    and a2(out[2],a[3],notb);
    and a3(out[1],nota,b[3]);
    and a4(out[0],notb,nota);

endmodule

module fourtosixteen(a,b,out,ovf);
    input  [3:0] a;
    input  [3:0] b;
    output  [15:0] out;
    output ovf;
    wire [15:0] temp1;
    wire [15:0] temp2;
    twotofour f1({a[3],3'b000},{a[2],3'b000},temp1,ovf);
    twotofour f2({b[3],3'b000},{b[2],3'b000},temp2,ovf);
    and a1(out[0],temp1[0],temp2[0]);
    and a2(out[1],temp1[0],temp2[1]);
    and a3(out[2],temp1[0],temp2[2]);
    and a4(out[3],temp1[0],temp2[3]);
    and a5(out[4],temp1[1],temp2[0]);
    and a6(out[5],temp1[1],temp2[1]);
    and a7(out[6],temp1[1],temp2[2]);
    and a8(out[7],temp1[1],temp2[3]);
    and a9(out[8],temp1[2],temp2[0]);
    and a10(out[9],temp1[2],temp2[1]);
    and a11(out[10],temp1[2],temp2[2]);
    and a12(out[11],temp1[2],temp2[3]);
    and a13(out[12],temp1[3],temp2[0]);
    and a14(out[13],temp1[3],temp2[1]);
    and a15(out[14],temp1[3],temp2[2]);
    and a16(out[15],temp1[3],temp2[3]);

endmodule

module bitslice(a,b,c,d,out);
    input  a;
    input  b;
    input c;
    input d;
    output [1:0]out;
    wire nota,notb,notc,notd;
    wire temp1,temp2,temp3,temp4;
    not n1(nota,a);
    not n2(notb,b);
    not n3(notc,c);
    not n4(notd,d);

    and a1(temp1,c,notd);
    and a2(temp2,a,notb,notd);
    and a3(temp3,notc,d);
    and a4(temp4,nota,b,notc);

    or o1(out[1],temp1,temp2);
    or o2(out[0],temp3,temp4);


endmodule

module selectlarge(a,b,out,ovf);
    input  [3:0] a;
    input  [3:0] b;
    output reg [15:0] out;
    output ovf;
    assign ovf=1'b0;
    wire [1:0] p1,p2,p3,p4;
    bitslice b1(a[3],b[3],1'b0,1'b0,p1);
    bitslice b2(a[2],b[2],p1[1],p1[0],p2);
    bitslice b3(a[1],b[1],p2[1],p2[0],p3);
    bitslice b4(a[0],b[0],p3[1],p3[0],p4);
    always@(*)begin
    out[15:4]=12'b000000000000;
        case(p4[1])
            1'b1:begin
                out[3]=a[3];
                out[2]=a[2];
                out[1]=a[1];
                out[0]=a[0];
            end
            1'b0:begin
                   case(p4[0])
           1'b1:begin
                out[3]=b[3];
                out[2]=b[2];
                out[1]=b[1];
                out[0]=b[0];
             end
           1'b0:begin
                out[3]=b[3];
                out[2]=b[2];
                out[1]=b[1];
                out[0]=b[0];
           end
       endcase

            end
       endcase
    end
endmodule

module selectsmall(a,b,out,ovf);
    input  [3:0] a;
    input  [3:0] b;
    output reg [15:0] out;
    output ovf;
    assign ovf=1'b0;
    wire [1:0] p1,p2,p3,p4;
    bitslice b1(a[3],b[3],1'b0,1'b0,p1);
    bitslice b2(a[2],b[2],p1[1],p1[0],p2);
    bitslice b3(a[1],b[1],p2[1],p2[0],p3);
    bitslice b4(a[0],b[0],p3[1],p3[0],p4);
    always@(*)begin
    out[15:4]=12'b000000000000;
        case(p4[1])
            1'b1:begin
                out[3]=b[3];
                out[2]=b[2];
                out[1]=b[1];
                out[0]=b[0];
            end
            1'b0:begin
                   case(p4[0])
           1'b1:begin
                out[3]=a[3];
                out[2]=a[2];
                out[1]=a[1];
                out[0]=a[0];
             end
           1'b0:begin
                out[3]=b[3];
                out[2]=b[2];
                out[1]=b[1];
                out[0]=b[0];
           end
       endcase

            end
       endcase
    end
endmodule

module myadder(a,b,c,cout,s);
    input  a;
    input  b;
    input c;
    output  cout,s;
    wire t1,t2,t3;
    xor x1(s,a,b,c);

    and a1(t1,a,b);
    and a2(t2,b,c);
    and a3(t3,a,c);

    or o1(cout,t1,t2,t3);
endmodule

module fulladder(a,b,out,ovf);
    input signed [3:0] a;
    input signed [3:0] b;
    output signed [15:0] out;
    output ovf;
    wire cout1,cout2,cout3,cout4;
    myadder m1(a[0],b[0],1'b0,cout1,out[0]);
    myadder m2(a[1],b[1],cout1,cout2,out[1]);
    myadder m3(a[2],b[2],cout2,cout3,out[2]);
    myadder m4(a[3],b[3],cout3,cout4,out[3]);
        buf b0(out[4],out[3]);
        buf b11(out[5],out[3]);
        buf b12(out[6],out[3]);
        buf b2(out[7],out[3]);
        buf b3(out[8],out[3]);
        buf b4(out[9],out[3]);
        buf b5(out[10],out[3]);
        buf b13(out[11],out[3]);
        buf b6(out[12],out[3]);
        buf b7(out[13],out[3]);
        buf b8(out[14],out[3]);
        buf b9(out[15],out[3]);
//assign out[15:4] = {12{out[3]}};
    xor x1(ovf,cout3,cout4);
endmodule

module minus(a,b,out,ovf);
    input signed [3:0] a;
    input signed [3:0] b;
    output signed [15:0] out;
    output ovf;
    wire b1,b2,b3,b0;
/*    assign b1=b[1];
    assign b2=b[2];
    assign b3=b[3];
    assign b4=b[0];*/
    xor x2(b3,b[3],1'b1);
    xor x3(b2,b[2],1'b1);
    xor x4(b1,b[1],1'b1);
    xor x5(b0,b[0],1'b1);

    wire cout1,cout2,cout3,cout4;
    myadder m1(a[0],b0,1'b1,cout1,out[0]);
    myadder m2(a[1],b1,cout1,cout2,out[1]);
    myadder m3(a[2],b2,cout2,cout3,out[2]);
    myadder m4(a[3],b3,cout3,cout4,out[3]);
    assign out[15:4] = {12{out[3]}};
    xor x1(ovf,cout3,cout4);
endmodule

module absolute(a,b,out,ovf);
    input [3:0] a;
    input [3:0] b;
    output [15:0] out;
    output ovf;
    wire b1,b2,b3,b0;
    xor x2(b3,b[3],1'b1);
    xor x3(b2,b[2],1'b1);
    xor x4(b1,b[1],1'b1);
    xor x5(b0,b[0],1'b1);
    wire out1,out2,out3,out0;
    wire cout1,cout2,cout3,cout4;
    myadder m1(a[0],b0,1'b1,cout1,out0);
    myadder m2(a[1],b1,cout1,cout2,out1);
    myadder m3(a[2],b2,cout2,cout3,out2);
    myadder m4(a[3],b3,cout3,cout4,out3);
    wire ovf1,ovf2;
    xor x1(ovf1,cout3,cout4);
    wire [3:0] temp;
    xor x6(temp[0],out0,out3);
    xor x7(temp[1],out1,out3);
    xor x8(temp[2],out2,out3);
    xor x9(temp[3],out3,out3);
    fulladder f1(temp,{3'b000, out3},out,ovf2);
    assign out[15:4] = {12{out[3]}};
    or o10(ovf,ovf1,ovf2);
endmodule

module bonus(a,b,out,ovf);
    input [3:0] a;
    input [3:0] b;
    output [15:0] out;
    output ovf;
    assign ovf=1'b0;
    wire temp[17:0];
    wire cout[15:0];
    wire s[15:0];
    and a1(out[0],a[0],b[0]);
    and a2(temp[0],a[1],b[0]);
    and a3(temp[1],a[2],b[0]);
    and a4(temp[2],a[3],b[0]);
    and a5(temp[3],a[0],b[1]);
    and a6(temp[4],a[1],b[1]);
    and a7(temp[5],a[2],b[1]);
    and a8(temp[6],a[3],b[1]);
    and a9(temp[7],a[0],b[2]);
    and a10(temp[8],a[1],b[2]);
    and a11(temp[9],a[2],b[2]);
    and a12(temp[10],a[3],b[2]);
    and a13(temp[11],a[0],b[3]);
    and a14(temp[12],a[1],b[3]);
    and a15(temp[13],a[2],b[3]);
    and a16(temp[14],a[3],b[3]);
    wire [3:0] t;
    wire [15:0] tt;
    xor x1(t[0],temp[11],b[3]);
    xor x2(t[1],temp[12],b[3]);
    xor x3(t[2],temp[13],b[3]);
    xor x4(t[3],temp[14],b[3]);
    wire gar;
    //fulladder f1(t,{3'b000, b[3]},tt,gar);
    myadder m1(temp[0],temp[3],1'b0,cout[0],out[1]);
    myadder m2(temp[1],temp[4],cout[0],cout[1],s[0]);
    myadder m3(temp[2],temp[5],cout[1],cout[2],s[1]);
    myadder m4(temp[2],temp[6],cout[2],cout[3],s[2]);
    myadder m5(temp[2],temp[6],cout[3],cout[4],s[3]);
    myadder m6(temp[2],temp[6],cout[4],cout[5],s[4]);

    myadder m7(s[0],temp[7],1'b0,cout[6],out[2]);
    myadder m8(s[1],temp[8],cout[6],cout[7],s[5]);
    myadder m9(s[2],temp[9],cout[7],cout[8],s[6]);
    myadder m10(s[3],temp[10],cout[8],cout[9],s[7]);
    myadder m11(s[4],temp[10],cout[9],cout[10],s[8]);

    myadder m12(s[5],t[0],b[3],cout[11],out[3]);
    myadder m13(s[6],t[1],cout[11],cout[12],out[4]);
    myadder m14(s[7],t[2],cout[12],cout[13],out[5]);
    myadder m15(s[8],t[3],cout[13],cout[14],out[6]);
    wire gar1,gar2,gar3;
    wire s1,s2,s3;
    myadder m16(temp[2],temp[6],cout[5],gar1,s1);
    myadder m17(temp[10],s1,cout[10],gar2,s2);
    myadder m18(t[3],s2,cout[14],gar3,out[7]);


    //myadder m16(cout[5],temp[10],cout[14],gar,out[7]);
    //buf bbb(out[7], out[6]);
   // assign out[15:8] = {8{out[7]}};
     // /*
        buf b2(out[8],out[7]);
        buf b3(out[9],out[7]);
        buf b4(out[10],out[7]);
        buf b5(out[11],out[7]);
        buf b6(out[12],out[7]);
        buf b7(out[13],out[7]);
        buf b8(out[14],out[7]);
        buf b9(out[15],out[7]);
        //*/





endmodule