thumb_disassm.cpp

//
// instruction format documentation from this source:
// http://bear.ces.cwru.edu/eecs_382/ARM7-TDMI-manual-pt3.pdf
//
#include <stdio.h>

// ----------------------------------------------------------------
//
//
// ----------------------------------------------------------------

//
#define thsint32   signed       int
#define thsint16   signed short int
#define thuint16 unsigned short int
#define thbyte   unsigned       char
#define thbool                  bool

//
#define FINLINE inline

// ----------------------------------------------------------------
// the following section defines the bit masks used in decoding the
// instruction formats. the use of namespaces is purely because I
// like fully qualified enums since it looks more readable.
// ----------------------------------------------------------------

//
namespace mask
{
    enum
    {
        //
        insdsc1    = 0xE000,    // 1110000000000000
        insdsc2    = 0x1C00,    // 0001110000000000
        insdsc3    = 0x0200,    // 0000001000000000
        insdsc4    = 0x1000,    // 0001000000000000
        insdsc5    = 0x1000,    // 0001000000000000
        insdsc6    = 0x0400,    // 0000010000000000
        insdsc7    = 0x1000,    // 0001000000000000
        insdsc8    = 0x1000,    // 0001000000000000

        //
        ins01opdsc = 0x1800,    // 0001100000000000
        ins02opdsc = 0x0200,    // 0000000100000000
        ins03opdsc = 0x1800,    // 0001100000000000
        ins04opdsc = 0x03C0,    // 0000001111000000
        ins05opdsc = 0x0300,    // 0000001100000000

        //
        ins16cond  = 0x0F00,    // 0000111100000000
    };
};

//
#define INSDSC1( x ) (x<<13)
namespace insdsc1
{
    enum
    {
        ins00   = INSDSC1( 0x0 ),
        ins03   = INSDSC1( 0x1 ),
        ins04   = INSDSC1( 0x2 ),
        ins09   = INSDSC1( 0x3 ),
        ins10   = INSDSC1( 0x4 ),
        ins12   = INSDSC1( 0x5 ),
        ins15   = INSDSC1( 0x6 ),
        ins18   = INSDSC1( 0x7 )
    };
};

//
#define INSDSC2( x ) (x<<10)
namespace insdsc2
{
    enum
    {
        ins4     = INSDSC2( 0x0 ),
        ins5     = INSDSC2( 0x1 ),
        ins6_a   = INSDSC2( 0x2 ),
        ins6_b   = INSDSC2( 0x3 ),
        dsc7_8_a = INSDSC2( 0x4 ),
        dsc7_8_b = INSDSC2( 0x5 ),
        dsc7_8_c = INSDSC2( 0x6 ),
        dsc7_8_d = INSDSC2( 0x7 ),
    };
};

//
#define INS01OP( x ) (x<<11)
namespace ins01op
{
    enum
    {
        lsl     = INS01OP( 0x0 ),
        lsr     = INS01OP( 0x1 ),
        asr     = INS01OP( 0x2 ),
        ins02op = INS01OP( 0x3 )
    };
};

//
#define INS02OP( x ) (x<<8)
namespace ins02op
{
    enum
    {
        add     = INS02OP( 0x0 ),
        sub     = INS02OP( 0x1 )
    };
};

//
#define INS03OP( x ) (x<<11)
namespace ins03op
{
    enum
    {
        mov     = INS03OP( 0x0 ),
        cmp     = INS03OP( 0x1 ),
        add     = INS03OP( 0x2 ),
        sub     = INS03OP( 0x3 )
    };
};

//
#define INS04OP( x ) (x<<6)
namespace ins4op
{
    enum
    {
        and     = INS04OP( 0x0 ),
        eor     = INS04OP( 0x1 ),
        lsl     = INS04OP( 0x2 ),
        lsr     = INS04OP( 0x3 ),
        asr     = INS04OP( 0x4 ),
        adc     = INS04OP( 0x5 ),
        sbc     = INS04OP( 0x6 ),
        ror     = INS04OP( 0x7 ),
        tst     = INS04OP( 0x8 ),
        neg     = INS04OP( 0x9 ),
        cmp     = INS04OP( 0xA ),
        cmn     = INS04OP( 0xB ),
        orr     = INS04OP( 0xC ),
        mul     = INS04OP( 0xD ),
        bic     = INS04OP( 0xE ),
        mvn     = INS04OP( 0xF ),
    };
};

//
#define INS05OP( x ) (x<<8)
namespace ins5op
{
    enum
    {
        add     = INS05OP( 0 ),
        cmp     = INS05OP( 1 ),
        mov     = INS05OP( 2 ),
        bx      = INS05OP( 3 ),
    };
};

//
#define INS16COND( x ) (x<<8)
namespace ins16cond
{
    enum
    {
        beq     = INS16COND( 0x0 ),
        bne     = INS16COND( 0x1 ),
        bcs     = INS16COND( 0x2 ),
        bcc     = INS16COND( 0x3 ),
        bmi     = INS16COND( 0x4 ),
        bpl     = INS16COND( 0x5 ),
        bvs     = INS16COND( 0x6 ),
        bvc     = INS16COND( 0x7 ),
        bhi     = INS16COND( 0x8 ),
        bls     = INS16COND( 0x9 ),
        bge     = INS16COND( 0xA ),
        blt     = INS16COND( 0xB ),
        bgt     = INS16COND( 0xC ),
        ble     = INS16COND( 0xD ),
        ins17op = INS16COND( 0xF ),
    };
};

// ----------------------------------------------------------------
// the following code is for the instruction format decoders. they
// are declared in reverse so as to avoid forward declarations.
// these should all be forced inline where possible since they are
// defined as a sepourate function only for clarity.
// ----------------------------------------------------------------

// decode format 19 instructions
static FINLINE
void decodeF19( thuint16 *stream )
{
    // decode operand
    thsint32 s11 = (*stream);           // 0000011111111111
    //
    if ( *stream & 0x0800 ) // H set
    {
//      s11 = (s11 << 19) >> 4;
        printf( "bl1 \t#%d\n", s11 );
    }
    else
    {
//      s11 = (s11 << 19) >> 15;
        printf( "bl2 \t#%d\n", s11 );
    }
}

// decode format 18 instructions
static FINLINE
void decodeF18( thuint16 *stream )
{
    // decode operand
    thsint16 s11 = (*stream<<5)>>4; // 0000011111111111 signed
    //
    printf( "b   \t#%d\n", s11 );
}

// decode format 17 instructions
static FINLINE
void decodeF17( thuint16 *stream )
{
    //
    thbyte u8 = *stream & 0x00FF;
    //
    printf( "swi \t#%d\n", u8 );
}

// decode format 16 instructions
static FINLINE
void decodeF16( thuint16 *stream )
{
    // sign extended shift
    thsint16 s8 = (*stream<<8)>>6;  // signed
    //
    switch ( *stream & mask::ins16cond )
    {
    case ( ins16cond::beq ):
        //
        printf( "beq \t%d\n", s8 );
        break;
    case ( ins16cond::bne ):
        //
        printf( "bne \t%d\n", s8 );
        break;
    case ( ins16cond::bcs ):
        //
        printf( "bcs \t%d\n", s8 );
        break;
    case ( ins16cond::bcc ):
        //
        printf( "bcc \t%d\n", s8 );
        break;
    case ( ins16cond::bmi ):
        //
        printf( "bmi \t%d\n", s8 );
        break;
    case ( ins16cond::bpl ):
        //
        printf( "bpl \t%d\n", s8 );
        break;
    case ( ins16cond::bvs ):
        //
        printf( "bvs \t%d\n", s8 );
        break;
    case ( ins16cond::bvc ):
        //
        printf( "bvc \t%d\n", s8 );
        break;
    case ( ins16cond::bhi ):
        //
        printf( "bhi \t%d\n", s8 );
        break;
    case ( ins16cond::bls ):
        //
        printf( "bls \t%d\n", s8 );
        break;
    case ( ins16cond::bge ):
        //
        printf( "bgt \t%d\n", s8 );
        break;
    case ( ins16cond::blt ):
        //
        printf( "blt \t%d\n", s8 );
        break;
    case ( ins16cond::bgt ):
        //
        printf( "bgt \t%d\n", s8 );
        break;
    case ( ins16cond::ble ):
        //
        printf( "ble \t%d\n", s8 );
        break;
    case ( ins16cond::ins17op ):
        // format 17 decode
        decodeF17( stream );
        break;
    }
}

// decode format 15 instructions
static FINLINE
void decodeF15( thuint16 *stream )
{
    thbyte rb = (*stream >> 8) & 0x07;  // 0000011100000000
    //
    if ( *stream & 0x0800 )
    {
        printf( "ldmia\tr%d!, { \n", rb );
        if ( *stream & 0x01 ) { printf( "r0 " ); }
        if ( *stream & 0x02 ) { printf( "r1 " ); }
        if ( *stream & 0x04 ) { printf( "r2 " ); }
        if ( *stream & 0x08 ) { printf( "r3 " ); }
        if ( *stream & 0x10 ) { printf( "r4 " ); }
        if ( *stream & 0x20 ) { printf( "r5 " ); }
        if ( *stream & 0x40 ) { printf( "r6 " ); }
        if ( *stream & 0x80 ) { printf( "r7 " ); }
        printf( "}\n" );
    }
    else
    {
        //
        printf( "stmia\tr%d!, { \n", rb );
        if ( *stream & 0x01 ) { printf( "r0 " ); }
        if ( *stream & 0x02 ) { printf( "r1 " ); }
        if ( *stream & 0x04 ) { printf( "r2 " ); }
        if ( *stream & 0x08 ) { printf( "r3 " ); }
        if ( *stream & 0x10 ) { printf( "r4 " ); }
        if ( *stream & 0x20 ) { printf( "r5 " ); }
        if ( *stream & 0x40 ) { printf( "r6 " ); }
        if ( *stream & 0x80 ) { printf( "r7 " ); }
        printf( "}\n" );
    }
}

// decode format 14 instructions
static FINLINE
void decodeF14( thuint16 *stream )
{
    // decode operands
    if (! (*stream & 0x0800) )  // L set
    {
        printf( "push \t{ " );
        if ( *stream & 0x01 ) { printf( "r0 " ); }
        if ( *stream & 0x02 ) { printf( "r1 " ); }
        if ( *stream & 0x04 ) { printf( "r2 " ); }
        if ( *stream & 0x08 ) { printf( "r3 " ); }
        if ( *stream & 0x10 ) { printf( "r4 " ); }
        if ( *stream & 0x20 ) { printf( "r5 " ); }
        if ( *stream & 0x40 ) { printf( "r6 " ); }
        if ( *stream & 0x80 ) { printf( "r7 " ); }
        //
        if ( *stream & 0x0100 ) // R set
        {
            printf( "lr " );
        }
        printf( "}\n" );
    }
    else
    {
        printf( "pop \t{ " );
        if ( *stream & 0x01 ) { printf( "r0 " ); }
        if ( *stream & 0x02 ) { printf( "r1 " ); }
        if ( *stream & 0x04 ) { printf( "r2 " ); }
        if ( *stream & 0x08 ) { printf( "r3 " ); }
        if ( *stream & 0x10 ) { printf( "r4 " ); }
        if ( *stream & 0x20 ) { printf( "r5 " ); }
        if ( *stream & 0x40 ) { printf( "r6 " ); }
        if ( *stream & 0x80 ) { printf( "r7 " ); }
        //
        if ( *stream & 0x0100 ) // R set
        {
            printf( "lr " );
        }
        printf( "}\n" );
    }
}

// decode format 13 instructions
static FINLINE
void decodeF13( thuint16 *stream )
{
    // decode register operands
    thuint16 u7 = (*stream << 2 ) & 0x01FC; // 0000000001111111 unsigned
    //
    if ( *stream & 0x0080 ) // S set
    {
        printf( "sub \tsp, #%d\n", u7 );
    }
    else
    {
        printf( "add \tsp, #%d\n", u7 );
    }
}

// decode format 12 instructions
static FINLINE
void decodeF12( thuint16 *stream )
{
    // decode register operands
    thuint16 u8 = (*stream << 2) & 0x03FC;  // 0000000011111111 unsigned
    thbyte   rd = (*stream >> 8) & 0x0007;  // 0000011100000000
    //
    if ( *stream & 0x0800 ) // SP set
    {
        printf( "add \tr%d, sp, #%d\n", rd, u8 );
    }
    else
    {
        printf( "add \tr%d, pc, #%d\n", rd, u8 );
    }
}

// decode format 11 instructions
static FINLINE
void decodeF11( thuint16 *stream )
{
    // decode register operands
    thuint16 u8 = (*stream << 2) & 0x03FC;  // 0000000011111111 unsigned
    thbyte   rd = (*stream >> 8) & 0x0007;  // 0000011100000000
    //
    if ( *stream & 0x0800 ) // L set
    {
        printf( "LDR \tr%d, [sp, #%d]\n", rd, u8 );
    }
    else
    {
        printf( "STR \tr%d, [sp, #%d]\n", rd, u8 );
    }
}

// decode format 10 instructions
static FINLINE
void decodeF10( thuint16 *stream )
{
    // decode register operands
    thbyte rd = (*stream     ) & 0x07;  // 0000000000000111
    thbyte rb = (*stream >> 3) & 0x07;  // 0000000000111000
    thbyte u5 = (*stream >> 5) & 0x3E;  // 0000011111000000 unsigned
    //
    if ( *stream & 0x0800 ) // L set
    {
        printf( "LDRH\tr%d, [r%d, #%d]\n", rd, rb, u5 );
    }
    else
    {
        printf( "STRH\tr%d, [r%d, #%d]\n", rd, rb, u5 );
    }
}

// decode format 9 instructions
static FINLINE
void decodeF09( thuint16 *stream )
{
    // decode register operands
    thbyte   rd = (*stream     ) & 0x07;    // 0000000000000111
    thbyte   rb = (*stream >> 3) & 0x07;    // 0000000000111000
    thuint16 u5 = (*stream >> 4) & 0x7C;    // 0000011111000000 unsigned
    //
    switch
    (
        (((*stream & 0x0800)!=0)<<1) +  // L set
         ((*stream & 0x1000)!=0)        // B set
    )
    {
    case ( 0 ):
        printf( "str \tr%d, [r%d, #%d]\n", rd, rb, u5 );
        break;
    case ( 1 ):
        printf( "strb\tr%d, [r%d, #%d]\n", rd, rb, u5 );
        break;
    case ( 2 ):
        printf( "ldr \tr%d, [r%d, #%d]\n", rd, rb, u5 );
        break;
    case ( 3 ):
        printf( "ldrb\tr%d, [r%d, #%d]\n", rd, rb, u5 );
        break;
    }
}

// decode format 8 instructions
static FINLINE
void decodeF08( thuint16 *stream )
{
    // decode register operands
    thbyte rd = (*stream     ) & 0x07;  // 0000000000000111
    thbyte rb = (*stream >> 3) & 0x07;  // 0000000000111000
    thbyte ro = (*stream >> 6) & 0x07;  // 0000000111000000
    //
    if ( *stream & 0x0800 ) // H set
    {

    }
    if ( *stream & 0x0400 ) // S set
    {
    }
    //
    printf( "[format 8]\n" );
}

// decode format 7 instructions
static FINLINE
void decodeF07( thuint16 *stream )
{
    // decode register operands
    thbyte rd = (*stream     ) & 0x07;  // 0000000000000111
    thbyte rb = (*stream >> 3) & 0x07;  // 0000000000111000
    thbyte ro = (*stream >> 6) & 0x07;  // 0000000111000000
    //
    switch
    (
        (((*stream & 0x0800)!=0)<<1) +  // L set
         ((*stream & 0x0400)!=0)        // B set
    )
    {
    case ( 0 ):
        printf( "str \tr%d, [r%d, r%d]\n", rd, rb, ro );
        break;
    case ( 1 ):
        printf( "strb\tr%d, [r%d, r%d]\n", rd, rb, ro );
        break;
    case ( 2 ):
        printf( "ldr \tr%d, [r%d, r%d]\n", rd, rb, ro );
        break;
    case ( 3 ):
        printf( "ldrb\tr%d, [r%d, r%d]\n", rd, rb, ro );
        break;
    }
}

// decode format 6 instructions
static FINLINE
void decodeF06( thuint16 *stream )
{
    // decode register operands
    thbyte   rd = (*stream >> 8) & 0x07;    // 0000011100000000
    thuint16 u8 = (*stream     ) & 0xFF;    // 0000000011111111 unsigned
             u8 = u8 << 2;
    //
    printf( "ldr \tr%d, [pc, #%d]\n", rd, u8 );
}

// decode format 5 instructions
static FINLINE
void decodeF05( thuint16 *stream )
{
    // decode register operands
    thbyte rd =  *stream       & 0x07;  // 0000000000000111
    thbyte rs = (*stream >> 3) & 0x07;  // 0000000000111000
    //
    if ( *stream & 0x80 ) // H1 Set
    {
    }
    if ( *stream & 0x40 ) // H2 Set
    {
    }
    //
    switch ( *stream & mask::ins05opdsc )
    {
    case ( ins5op::add ):
        printf( "add \t?r%d, ?r%d\n", rd, rs );
        //
        break;
    case ( ins5op::cmp ):
        printf( "cmp \t?r%d, ?r%d\n", rd, rs );
        //
        break;
    case ( ins5op::mov ):
        printf( "mov \t?r%d, ?r%d\n", rd, rs );
        //
        break;
    case ( ins5op::bx  ):
        printf( "bx  \t?r%d, ?r%d\n", rd, rs );
        //
        break;
    }
}

// decode format 4 instructions
static FINLINE
void decodeF04( thuint16 *stream )
{
    // decode register operands
    thbyte rd =  *stream       & 0x07;  // 0000000000000111
    thbyte rs = (*stream >> 3) & 0x07;  // 0000000000111000
    // branch based on opcode
    switch ( *stream & mask::ins04opdsc )
    {
    case ( ins4op::and ):
        // [rd = rd AND rs]
        printf( "and \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::eor ):
        // [rd = rd XOR rs]
        printf( "eor \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::lsl ):
        // [rd = rd << rs]
        printf( "lsl \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::lsr ):
        // [rd = rd >> rs]
        printf( "lsr \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::asr ):
        // [rd = rd AND rs]
        printf( "asr \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::adc ):
        // [rd = rd + rs + c-bit]
        printf( "adc \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::sbc ):
        // [rd = rd - rs - NOT c-bit]
        printf( "sbc \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::ror ):
        // [rd = rd ROR rs]
        printf( "ror \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::tst ):
        // set condition codes on [rd AND rs]
        printf( "tst \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::neg ):
        // [rd = -rs]
        printf( "neg \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::cmp ):
        // set condition codes on [rd - rs]
        printf( "cmp \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::cmn ):
        // set condition codes on [rd + rs]
        printf( "cmn \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::orr ):
        // [rd = rd OR rs]
        printf( "orr \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::mul ):
        // [rd = rd * rs]
        printf( "mul \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::bic ):
        // [rd = rd AND NOT rs]
        printf( "bic \tr%d, r%d\n", rd, rs );
        break;
    case ( ins4op::mvn ):
        // [rd = NOT rs]
        printf( "mvn \tr%d, r%d\n", rd, rs );
        break;
    }
}

// decode format 3 instructions
static FINLINE
void decodeF03( thuint16 *stream )
{
    // decode operands
    thbyte rd = (*stream >> 8 ) & 0x0007;   // 0000011100000000
    thbyte u8 =  *stream        & 0x00FF;   // 0000000011111111 unsigned
    // decode opcode
    switch ( *stream & mask::ins03opdsc )
    {
    case ( ins03op::mov ):
        // [rd = o8]
        printf( "mov \tr%d, #%d\n", rd, u8 );
        break;
    case ( ins03op::cmp ):
        // compare contentse of rd with o8
        printf( "cmp \tr%d, #%d\n", rd, u8 );
        break;
    case ( ins03op::add ):
        // [rd = rd + o8]
        printf( "add \tr%d, #%d\n", rd, u8 );
        break;
    case ( ins03op::sub ):
        // [rd = rd - o8]
        printf( "sub \tr%d, #%d\n", rd, u8 );
        break;
    }
}

// decode format 2 instructions
static FINLINE
void decodeF02( thuint16 *stream )
{
    // decode the operands
    thbyte rd =  *stream        & 0x07; // 0000000000000111
    thbyte rs = (*stream >> 3 ) & 0x07; // 0000000000111000
    thbyte u3 = (*stream >> 6 ) & 0x07; // 0000000111000000 unsigned
    // decode the I flag
    if ( *stream & 0x0200 )             // 0000010000000000
    {
        // index into rs
    }
    // decode the opcode
    switch ( *stream & mask::ins02opdsc )
    {
    case ( ins02op::add ):
        // [rd = rs + rn]
        printf( "add \tr%d, r%d, ?r%d\n", rd, rs, u3 );
        break;
    case ( ins02op::sub ):
        // [rd = rs - rn]
        printf( "sub \tr%d, r%d, ?r%d\n", rd, rs, u3 );
        break;
    };
}

// decode format 1 instructions
static FINLINE
void decodeF01( thuint16 *stream )
{
    // decode register operands
    thbyte rd =  *stream        & 0x0007;   // 0000000000000111
    thbyte rs = (*stream >> 3 ) & 0x0007;   // 0000000000111000
    thbyte u5 = (*stream >> 6 ) & 0x001F;   // 0000011111000000 unsigned
    // decode the opcode
    switch ( *stream & mask::ins01opdsc )
    {
    case ( ins01op::lsl ):
        // [rd = rs << o5] shift
        printf( "lsl \tr%d, r%d, #%d\n", rd, rs, u5 );
        break;
    case ( ins01op::lsr ):
        // [rd = rs >> o5] logical
        printf( "lsr \tr%d, r%d, #%d\n", rd, rs, u5 );
        break;
    case ( ins01op::asr ):
        // [rd = rs >> o5] arythmetic
        printf( "asr \tr%d, r%d, #%d\n", rd, rs, u5 );
        break;

    // this is format 2
    case ( ins01op::ins02op ):
        decodeF02( stream );
    }
}

// ----------------------------------------------------------------
//
//
// ----------------------------------------------------------------

//
static FINLINE
void decode( thuint16 *stream )
{
    //
    thuint16 ins = (*stream);
    // level 1 descriminator
    switch ( ins & mask::insdsc1 )
    {
    case ( insdsc1::ins00 ):
        // format 1 decode
        decodeF01( stream );
        break;
    case ( insdsc1::ins03 ):
        // format 3 decode
        decodeF03( stream );
        break;
    case ( insdsc1::ins04 ):
        // level 2 descriminator
        switch ( ins & mask::insdsc2 )
        {
        case ( insdsc2::ins4 ):
            // format 4 decode
            decodeF04( stream );
            break;
        case ( insdsc2::ins5 ):
            // format 5 decode
            decodeF05( stream );
            break;
        case ( insdsc2::ins6_a ):
        case ( insdsc2::ins6_b ):
            // format 6 decode
            decodeF06( stream );
            break;
        case ( insdsc2::dsc7_8_a ):
        case ( insdsc2::dsc7_8_b ):
        case ( insdsc2::dsc7_8_c ):
        case ( insdsc2::dsc7_8_d ):
            // stage 3 descriminator
            if (! (ins & mask::insdsc3) )
                // format 7
                decodeF07( stream );
            else
                // format 8
                decodeF08( stream );
            break;
        }
        break;
    case ( insdsc1::ins09 ):
        // format 9 decode
        decodeF09( stream );
        break;
    case ( insdsc1::ins10 ):
        // stage 4 descriminator
        if (! (ins & mask::insdsc4) )
            // format 10 decode
            decodeF10( stream );
        else
            // format 11 decode
            decodeF11( stream );
        break;
    case ( insdsc1::ins12 ):
        // stage 5 descriminator
        if (! (ins & mask::insdsc5) )
            // format 12 decode
            decodeF12( stream );
        else
        {
            // stage 6 descriminator
            if (! (ins & mask::insdsc6) )
                // format 13 decode
                decodeF13( stream );
            else
                // format 14 decode
                decodeF14( stream );
        }
        break;
    case ( insdsc1::ins15 ):
        // stage 7 descriminator
        if (! (ins & mask::insdsc7) )
            // format 15 decode
            decodeF15( stream );
        else
            // format 16 decode
            decodeF16( stream );
        break;
    case ( insdsc1::ins18 ):
        // stage 8 descriminator
        if (! (ins & mask::insdsc8) )
            // format 18 decode
            decodeF18( stream );
        else
            // format 19 decode
            decodeF19( stream );
        break;
    }

}

unsigned char data[] =
{
    0x80,0xB5,0x00,0xAF,0x02,0x23,0x18,0x1C,0xBD,0x46,0x80,0xBC,0x02,0xBC,0x08,0x47,
    0x80,0xB5,0x82,0xB0,0x00,0xAF,0x78,0x60,0x7B,0x68,0x5B,0x00,0x18,0x1C,0xBD,0x46,
    0x02,0xB0,0x80,0xBC,0x02,0xBC,0x08,0x47,0x80,0xB5,0x84,0xB0,0x00,0xAF,0x78,0x60,
    0x3B,0x1C,0x08,0x33,0x01,0x22,0x1A,0x60,0x3B,0x1C,0x08,0x33,0x00,0x22,0x5A,0x60,
    0x3B,0x1C,0x08,0x33,0x7A,0x68,0x92,0x00,0xD3,0x58,0x18,0x1C,0xBD,0x46,0x04,0xB0,
    0x80,0xBC,0x02,0xBC,0x08,0x47,0xC0,0x46,0x80,0xB5,0x82,0xB0,0x00,0xAF,0x00,0x23,
    0x7B,0x60,0x05,0xE0,0xFF,0xF7,0xCC,0xFF,0x03,0x1C,0x7A,0x68,0xD3,0x18,0x7B,0x60,
    0x7B,0x68,0x09,0x2B,0xF6,0xDD,0x7B,0x68,0x18,0x1C,0xBD,0x46,0x02,0xB0,0x80,0xBC,
    0x02,0xBC,0x08,0x47
};

//
int main( int argc, char** args )
{
    int i=0;
    thuint16 *ptr = (thuint16*) data;
    while ( ptr < (thuint16*)(data+sizeof(data)) )
    {
        printf( " %4X:  %04X    ", i, *ptr );
        decode( ptr );
        ptr++;
        i += 2;
    }
    getchar( );
    return 0;
}