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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    14:53:27 12/02/2019
  6. -- Design Name:
  7. -- Module Name:    modul - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity modul4 is
  33.     Port ( Y : out  STD_LOGIC;
  34.                 DNI : out  STD_LOGIC;
  35.                 WE : out  STD_LOGIC;
  36.               Q : out  STD_LOGIC_VECTOR (7 downto 0);
  37.            X : in  STD_LOGIC_VECTOR (7 downto 0);
  38.               F0 : in STD_LOGIC;
  39.            RST : in  STD_LOGIC;
  40.            CLK : in  STD_LOGIC;
  41.               D0_RDY : in STD_LOGIC);
  42. end modul4;
  43.  
  44. architecture Behavioral of modul4 is
  45.  
  46. --Insert the following in the architecture before the begin keyword
  47.    --Use descriptive names for the states, like st1_reset, st2_search
  48.    type state_type is (q0,q1,q2,q3,q4_a,q4);
  49.    signal state, next_state : state_type;
  50.    --Declare internal signals for all outputs of the state-machine
  51.    signal Y_i : std_logic;  -- example output signal
  52.    --other outputs
  53.    
  54. begin
  55.  
  56. SYNC_PROC: process (CLK)
  57.    begin
  58.       if (CLK'event and CLK = '1') then
  59.          if( Y_i = '1') then
  60.                 state <= next_state;
  61.             elsif (RST = '1') then
  62.             state <= q0;
  63.          elsif (D0_RDY ='1') then
  64.                 if (F0='0') then
  65.                     state <= next_state;
  66.                 end if;
  67.             --<output> <= <output>_i;
  68.          -- assign other outputs to internal signals
  69.          end if;        
  70.       end if;
  71.    end process;
  72.  
  73.    --MOORE State-Machine - Outputs based on state only
  74.    OUTPUT_DECODE: process (state)
  75.    begin
  76.       --insert statements to decode internal output signals
  77.       --below is simple example
  78.       if state = q4 then
  79.          Y <= '1';
  80.       else
  81.          Y <= '0';
  82.       end if;
  83.    end process;
  84.  
  85.    NEXT_STATE_DECODE: process (state, X)
  86.    begin
  87.       --declare default state for next_state to avoid latches
  88.       next_state <= state;  --default is to stay in current state
  89.       --insert statements to decode next_state
  90.       --below is a simple example
  91.       DNI <= '1';
  92.         Y_i <= '0';
  93.         case (state) is
  94.          when q0 =>
  95.                 Q <= "00000000";
  96.             if X = X"42" and F0='0'  then -- K
  97.                next_state <= q1;
  98.  
  99.                 else
  100.                     next_state <= q0;
  101.             end if;
  102.            
  103.          when q1 =>
  104.                 Q <= "00000001";
  105.             if X = X"2C" and F0='0' then --T
  106.                next_state <= q2;
  107.                 elsif X = X"42" and F0='0' then
  108.                     next_state <= q1;
  109.                 else
  110.                     next_state <= q0;
  111.             end if;
  112.                
  113.          when q2 =>
  114.                 Q <= "00000010";
  115.             if X = X"2C" and F0='0' then -- T
  116.                next_state <= q3;
  117.                 elsif X = X"42" and F0='0' then
  118.                     next_state <= q1;
  119.                 else
  120.                     next_state <= q0;
  121.             end if;
  122.                
  123.          when q3 =>
  124.                 Q <= "00000011";
  125.             if X = X"4D" and F0='0' then --P
  126.                next_state <= q4_a;
  127.                 elsif X = X"42" and F0='0' then
  128.                     next_state <= q1;
  129.                 else
  130.                     next_state <= q0;
  131.             end if;
  132.            
  133.            
  134.             when q4_a =>
  135.                 Q <= "00100100";
  136.             WE <= '1';
  137.                 Y_i <= '1';
  138.             next_state <= q4;
  139.                
  140.            
  141.          when q4 =>
  142.                 Y_i <= '0';
  143.                 WE <= '0';
  144.                 Q <= "00000000";
  145.             if X = X"42" and F0='0' then
  146.                next_state <= q1;
  147.                 else
  148.                     next_state <= q0;
  149.             end if;            
  150.  
  151.       end case;      
  152.    end process;
  153.  
  154. end Behavioral;
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