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-- Company:
-- Engineer:
--
-- Create Date:    14:53:27 12/02/2019
-- Design Name:
-- Module Name:    modul - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity modul4 is
    Port ( Y : out  STD_LOGIC;
				DNI : out  STD_LOGIC;
				WE : out  STD_LOGIC;
			  Q : out  STD_LOGIC_VECTOR (7 downto 0);
           X : in  STD_LOGIC_VECTOR (7 downto 0);
			  F0 : in STD_LOGIC;
           RST : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
			  D0_RDY : in STD_LOGIC);
end modul4;

architecture Behavioral of modul4 is

--Insert the following in the architecture before the begin keyword
   --Use descriptive names for the states, like st1_reset, st2_search
   type state_type is (q0,q1,q2,q3,q4_a,q4);
   signal state, next_state : state_type;
   --Declare internal signals for all outputs of the state-machine
   signal Y_i : std_logic;  -- example output signal
   --other outputs

begin

SYNC_PROC: process (CLK)
   begin
      if (CLK'event and CLK = '1') then
         if( Y_i = '1') then
				state <= next_state;
			elsif (RST = '1') then
            state <= q0;
         elsif (D0_RDY ='1') then
				if (F0='0') then
					state <= next_state;
				end if;
            --<output> <= <output>_i;
         -- assign other outputs to internal signals
         end if;
      end if;
   end process;

   --MOORE State-Machine - Outputs based on state only
   OUTPUT_DECODE: process (state)
   begin
      --insert statements to decode internal output signals
      --below is simple example
      if state = q4 then
         Y <= '1';
      else
         Y <= '0';
      end if;
   end process;

   NEXT_STATE_DECODE: process (state, X)
   begin
      --declare default state for next_state to avoid latches
      next_state <= state;  --default is to stay in current state
      --insert statements to decode next_state
      --below is a simple example
      DNI <= '1';
		Y_i <= '0';
		case (state) is
         when q0 =>
				Q <= "00000000";
            if X = X"42" and F0='0'  then -- K
               next_state <= q1;

				else
					next_state <= q0;
            end if;

         when q1 =>
				Q <= "00000001";
            if X = X"2C" and F0='0' then --T
               next_state <= q2;
				elsif X = X"42" and F0='0' then
					next_state <= q1;
				else
					next_state <= q0;
            end if;

         when q2 =>
				Q <= "00000010";
            if X = X"2C" and F0='0' then -- T
               next_state <= q3;
				elsif X = X"42" and F0='0' then
					next_state <= q1;
				else
					next_state <= q0;
            end if;

         when q3 =>
				Q <= "00000011";
            if X = X"4D" and F0='0' then --P
               next_state <= q4_a;
				elsif X = X"42" and F0='0' then
					next_state <= q1;
				else
					next_state <= q0;
            end if;


			when q4_a =>
				Q <= "00100100";
            WE <= '1';
				Y_i <= '1';
            next_state <= q4;


         when q4 =>
				Y_i <= '0';
				WE <= '0';
				Q <= "00000000";
            if X = X"42" and F0='0' then
               next_state <= q1;
				else
					next_state <= q0;
            end if;

      end case;
   end process;

end Behavioral;