module fact;

task factorial;
    input [3:0] n;
    output [31:0] outfact;
    integer count;
    begin
      outfact = 1;
      for(count =n; count > 0; count= count-1)
      outfact = outfact * count;
      end
endtask

initial
  begin: init1
    reg [3:0] n;
    reg [31:0] result;
    n = 4'b0101;
    factorial(n, result);
    $display("n=%d fact=%d", n, result);
  end
endmodule


((B or C) and (notA)) or (not(A or B))

module XOR(a, b, w1);

  input a, b;
  output reg w1;

  always @(a or b)
  begin
    w1 = a ^ b;
  end

endmodule

module AND(c, d, w2);

  input c, d;
  output reg w2;

  always @(c or d)
  begin
    w2 = c & d;
  end
endmodule

module OR(e, f, w3);

  input e, f;
  output reg w3;

  always @(e or f)
  begin
    w3 = e | f;
  end
endmodule

module NOR(h, i, w4);
    input h, i;
    output reg w4;

    always @(h or i)
    begin
      w4 = ~(h | i);
    end
endmodule

module something(a, b, c, out);

  input a, b, c;
  output out;
  wire w1, w2, w3;
  OR or1(b, c, w1);
  AND and1(w1, ~a, w2);
  NOR nor1(a, b, w3);
  OR or2(w2, w3, out);


endmodule

module Testbench;
  reg a, b, c;
  wire cout;

 something p(a, b, c, cout);
 initial
  begin
   a = 0;
    b = 0;
    c = 0;
    #1 $display("S=%b", cout);

   a = 1;
    b = 1;
    c = 1;
    #1 $display("S=%b ", cout);

end
 endmodule




Inmultire 2 numere 3 biti -> rezultat 4 biti

module XOR(a, b, w1);

  input a, b;
  output reg w1;

  always @(a or b)
  begin
    w1 = a ^ b;
  end

endmodule

module AND(c, d, w2);

  input c, d;
  output reg w2;

  always @(c or d)
  begin
    w2 = c & d;
  end
endmodule

module OR(e, f, w3);

  input e, f;
  output reg w3;

  always @(e or f)
  begin
    w3 = e | f;
  end
endmodule

module NOR(h, i, w4);
    input h, i;
    output reg w4;

    always @(h or i)
    begin
      w4 = ~(h | i);
    end
endmodule

module something(a0, a1, b0, b1, c0, c1, c2, c3);

  input a0, a1, b0, b1;
  output c0, c1, c2, c3;
  wire w1, w3, w4;
  AND and1(a0, b1, w1);
  AND and2(a0, b0, c0);
  AND and3(a1, b0, w3);
  AND and4(a1, b1, w4);
  XOR xor1(w1, w3, c1);
  AND and5(w1, w3, w5);
  XOR xor2(w5, w4, c2);
  AND And6(w4, w5, c3);

endmodule

module Testbench;
  reg a, a0, b0, b1;
  wire c0, c1, c2, c3;

 something p(a, a0, b0, b1, c0,c1,c2,c3);
 initial
  begin
   a  = 0;
   a0 = 1;
   b0 = 1;
   b1 = 1;
    #1 $display("S=%b, S=%b, S=%b, S=%b", c0, c1, c2, c3);

     a  = 1;
   a0 = 1;
   b0 = 1;
   b1 = 1;
    #1 $display("S=%b, S=%b, S=%b, S=%b", c0, c1, c2, c3);

end
 endmodule

module XOR(a, b, w1);

  input a, b;
  output reg w1;

  always @(a or b)
  begin
    w1 = a ^ b;
  end

endmodule

module AND(w1, cin,w2);

  input w1, cin;
  output reg w2;

  always @(w1 or cin)
  begin
    w2 = w1 & cin;
  end
endmodule

module OR(w2, w3, cout);

  input w2, w3;
  output reg cout;

  always @(w2 or w3)
  begin
    cout = w2 | w3;
  end
endmodule

module full_adder(a, b, cin, s, cout);

  input a, b, cin;
  output s, cout;

  XOR xor1(a, b, w1);
  XOR xor2(w1, cin, s);
  AND and1(w1, cin, w2);
  AND and2(a, b, w3);
  OR or1(w2, w3, cout);


endmodule

module Testbench;
  reg a, b, cin;
  wire s, cout;

  full_adder p(a, b, cin, s, cout);
 initial
  begin
   a = 0;
    b = 0;
    cin = 0;
    #1 $display("S=%b, C=%b\n", s, cout);

    a = 0;
    b = 1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=0;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a = 0;
    b = 0;
    cin = 1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a = 0;
    b = 1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=0;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=1;
    #1 $display("S=%b, C=%b\n", s, cout);
end
 endmodule




FULL ADDER CU NAND-URI


module NAND(a, b, w);

  input a, b;
  output reg w;

  always @(a or b)
  begin
    w = a ~& b;
  end
endmodule

module full_adder(a, b, cin, s, cout);

  input a, b, cin;
  output s, cout;

  NAND nand1(b, cin, w3);
  NAND nand2(b, w3, w4);
  NAND nand3(w3, cin, w5);
  NAND nand4(w4, w5, w6);
  NAND nand5(a, w6, w7);
  NAND nand6(a, w7, w1);
  NAND nand7(w7, w6, w8);
  NAND nand8(w7, w3, cout);
  NAND nand9(w1, w8, s);

endmodule

module Testbench;
  reg a, b, cin;
  wire s, cout;

  full_adder p(a, b, cin, s, cout);
 initial
  begin
   a = 0;
    b = 0;
    cin = 0;
    #1 $display("S=%b, C=%b\n", s, cout);

    a = 0;
    b = 1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=0;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a = 0;
    b = 0;
    cin = 1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a = 0;
    b = 1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=0;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=1;
    #1 $display("S=%b, C=%b\n", s, cout);
end
 endmodule


FULL ADDER 4 BIT


module NAND(a, b, w);

  input a, b;
  output reg w;

  always @(a or b)
  begin
    w = a ~& b;
  end
endmodule

module full_adder(a, b, cin, s, cout);

  input a, b, cin;
  output s, cout;

  NAND nand1(b, cin, w3);
  NAND nand2(b, w3, w4);
  NAND nand3(w3, cin, w5);
  NAND nand4(w4, w5, w6);
  NAND nand5(a, w6, w7);
  NAND nand6(a, w7, w1);
  NAND nand7(w7, w6, w8);
  NAND nand8(w7, w3, cout);
  NAND nand9(w1, w8, s);

endmodule

module bit4_full_adder(cin, a0, a1, a2, a3, b0, b1, b2, b3, s0, s1, s2, s3, cout);

  input cin, a0, a1, a2, a3, b0, b1, b2, b3;
  output s0, s1, s2, s3, cout;

  full_adder(a0, b0, cin

endmodule

module Testbench;
  reg a, b, cin;
  wire s, cout;

  full_adder p(a, b, cin, s, cout);

 initial
  begin
   a = 0;
    b = 0;
    cin = 0;
    #1 $display("S=%b, C=%b\n", s, cout);

    a = 0;
    b = 1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=0;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a = 0;
    b = 0;
    cin = 1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a = 0;
    b = 1;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=0;
    #1 $display("S=%b, C=%b\n", s, cout);

    a=1;
    b=1;
    #1 $display("S=%b, C=%b\n", s, cout);
end
 endmodule

module NAND(in1, in2, out);

input in1, in2;
output out;

assign out = ~(in1 & in2);

endmodule

module AND(in1, in2, out);

input in1, in2;
output out;
wire w1;

NAND NAND1(in1, in2, w1);
NAND NAND2(w1, w1, out);

endmodule

module Testbench;
reg a,b;

wire out1, out2;
initial begin
      a=0; b=0;
      #1 a=1 ;
      #1 b=1 ;
      #1 a=0 ;
end

initial begin

$monitor( "Time=%0d a=%b b=%b out1=%b out2=%b", $time, a, b, out1, out2);
end

AND and_gate(a,b,out1);
NAND nand_gate(a,b,out2);
endmodule




ADUNARE

module Adder(A,B,Result);

  input [3:0] A;
  input [3:0] B;
  output [3:0] Result;
  reg [3:0] Result;

  always @(A or B)
  begin
    Result <= A+B;
  end

endmodule

module Testbench;

  reg [3:0] A_t;
  reg [3:0] B_t;
  wire [3:0] Result_t;

  Adder Adder_1(A_t, B_t, Result_t);

  initial
  begin
    //case 0
    A_t <= 0; B_t <=0;
    #1 $display("Result_t=%b", Result_t);

    //case 1

    A_t <= 0; B_t <= 1;
    #1 $display("Result_t=%b", Result_t);

    //case 2
    A_t <=  1; B_t <= 0;
    #1 $display("Result_t=%b", Result_t);

    //case 3

    A_t <= 10; B_t <= 10;
    #1 $display("Result_t=%b", Result_t);
    end

   endmodule


DECODER 2X4


module Decoder(A, B, D);

  input A, B;
  output [3:0] D;
  reg [3:0] D;

  always @(A or B)

  begin
    if( A == 0 && B == 0)
      D <= 4'b0001;

    else if ( A == 0 && B == 1 )
      D <= 4'b0010;

    else if ( A == 1 && B == 0 )
      D <= 4'b0100;

    else if ( A == 1 && B == 1)
      D <= 4'b1000;   //nr binar realizat pe 4 biti
    end
endmodule

module Testbench;

reg A_t;
  reg B_t;
  wire [3:0] D_t;

  Decoder Decoder_1(A_t, B_t, D_t);

  initial
  begin
    //case 0
    A_t <= 0; B_t <=0;
    #1 $display("D_t=%b", D_t);

    //case 1

    A_t <= 0; B_t <= 1;
    #1 $display("D_t=%b", D_t);

    //case 2
    A_t <=  1; B_t <= 0;
    #1 $display("D_t=%b", D_t);

    //case 3

    A_t <= 1; B_t <= 1;
    #1 $display("D_t=%b", D_t);
    end

   endmodule



HALF ADDER


module XOR(A,B,S);
    input A, B;
    output reg S;

    always @(A or B)
    begin
      S = A^B;
    end
    endmodule

    module AND(A,B,S);
    input A,B;
    output reg S;

    always @(A or B)
    begin
        S = A&B;
    end
endmodule

module half_adder;

      reg A,B;
      output S,C;

      XOR myXOR(A,B,S);
      AND myAND(A,B,C);

      initial
      begin
    A = 0;
    B = 0;
    #1 $display("S=%b, C=%b\n", S, C);

    A = 0;
    B = 1;
    #1 $display("S=%b, C=%b\n", S, C);

    A=1;
    B=0;
    #1 $display("S=%b, C=%b\n", S, C);

    A=1;
    B=1;
    #1 $display("S=%b, C=%b\n", S, C);

end
endmodule