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- DDR Version 1.19 20190305
- In
- channel 0
- CS = 0
- MR0=0x19
- MR4=0x3
- MR5=0x6
- MR8=0x8
- MR12=0x72
- MR14=0x72
- MR18=0x0
- MR19=0x0
- MR24=0x8
- MR25=0xFF
- CS = 1
- MR0=0x19
- MR4=0x3
- MR5=0x6
- MR8=0x8
- MR12=0x72
- MR14=0x72
- MR18=0x0
- MR19=0x0
- MR24=0x8
- MR25=0xFF
- channel 1
- CS = 0
- MR0=0x19
- MR4=0x3
- MR5=0x6
- MR8=0x8
- MR12=0x72
- MR14=0x72
- MR18=0x0
- MR19=0x0
- MR24=0x8
- MR25=0xFF
- CS = 1
- MR0=0x19
- MR4=0x3
- MR5=0x6
- MR8=0x8
- MR12=0x72
- MR14=0x72
- MR18=0x0
- MR19=0x0
- MR24=0x8
- MR25=0xFF
- channel 0 training pass!
- channel 1 training pass!
- change freq to 400MHz 0,1
- channel 0
- CS = 0
- MR0=0x19
- MR4=0x3
- MR5=0x6
- MR8=0x8
- MR12=0x72
- MR14=0x72
- MR18=0x0
- MR19=0x0
- MR24=0x8
- MR25=0xFF
- CS = 1
- MR0=0x19
- MR4=0x3
- MR5=0x6
- MR8=0x8
- MR12=0x72
- MR14=0x72
- MR18=0x0
- MR19=0x0
- MR24=0x8
- MR25=0xFF
- channel 1
- CS = 0
- MR0=0x19
- MR4=0x3
- MR5=0x6
- MR8=0x8
- MR12=0x72
- MR14=0x72
- MR18=0x0
- MR19=0x0
- MR24=0x8
- MR25=0xFF
- CS = 1
- MR0=0x19
- MR4=0x3
- MR5=0x6
- MR8=0x8
- MR12=0x72
- MR14=0x72
- MR18=0x0
- MR19=0x0
- MR24=0x8
- MR25=0xFF
- channel 0 training pass!
- channel 1 training pass!
- change freq to 800MHz 1,0
- Channel 0: LPDDR4,800MHz
- Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
- Channel 1: LPDDR4,800MHz
- Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
- 256B stride
- ch 0 ddrconfig = 0x101, ddrsize = 0x2020
- ch 1 ddrconfig = 0x101, ddrsize = 0x2020
- pmugrf_os_reg[2] = 0x3AA1FAA1, stride = 0xD
- OUT
- Boot1: 2019-03-14, version: 1.19
- CPUId = 0x0
- ChipType = 0x10, 239
- SdmmcInit=2 0
- BootCapSize=100000
- UserCapSize=29820MB
- FwPartOffset=2000 , 100000
- mmc0:cmd8,20
- mmc0:cmd5,20
- mmc0:cmd55,20
- mmc0:cmd1,20
- mmc0:cmd8,20
- mmc0:cmd5,20
- mmc0:cmd55,20
- mmc0:cmd1,20
- mmc0:cmd8,20
- mmc0:cmd5,20
- mmc0:cmd55,20
- mmc0:cmd1,20
- SdmmcInit=0 1
- StorageInit ok = 67829
- SecureMode = 0
- SecureInit read PBA: 0x4
- SecureInit read PBA: 0x404
- SecureInit read PBA: 0x804
- SecureInit read PBA: 0xc04
- SecureInit read PBA: 0x1004
- SecureInit read PBA: 0x1404
- SecureInit read PBA: 0x1804
- SecureInit read PBA: 0x1c04
- SecureInit ret = 0, SecureMode = 0
- atags_set_bootdev: ret:(0)
- GPT part: 0, name: loader1, start:0x40, size:0x1f80
- GPT part: 1, name: uboot, start:0x4000, size:0x2000
- GPT part: 2, name: trust, start:0x6000, size:0x2000
- GPT part: 3, name: misc, start:0x8000, size:0x2000
- GPT part: 4, name: resource, start:0xa000, size:0x8000
- GPT part: 5, name: kernel, start:0x12000, size:0x2e000
- GPT part: 6, name: rootfs, start:0x40000, size:0x39fdfdf
- find part:uboot OK. first_lba:0x4000.
- find part:trust OK. first_lba:0x6000.
- LoadTrust Addr:0x6000
- No find bl30.bin
- Load uboot, ReadLba = 4000
- Load OK, addr=0x200000, size=0xf27c4
- RunBL31 0x10000
- NOTICE: BL31: v1.3(debug):370ab80
- NOTICE: BL31: Built : 09:23:41, Mar 4 2019
- NOTICE: BL31: Rockchip release version: v1.1
- INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
- INFO: Using opteed sec cpu_context!
- INFO: boot cpu mask: 0
- INFO: plat_rockchip_pmu_init(1181): pd status 3e
- INFO: BL31: Initializing runtime services
- INFO: BL31: Initializing BL32
- INF [0x0] TEE-CORE:init_primary_helper:337: Initializing (1.1.0-195-g8f090d20 #6 Fri Dec 7 06:11:20 UTC 2018 aarch64)
- INF [0x0] TEE-CORE:init_primary_helper:338: Release version: 1.2
- INF [0x0] TEE-CORE:init_teecore:83: teecore inits done
- INFO: BL31: Preparing for EL3 exit to normal world
- INFO: Entry point address = 0x200000
- INFO: SPSR = 0x3c9
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