module labK;
reg a, b, c, flag, catch;
wire notOutput, lowerInput, ac, bc, z;

not my_not(notOutput, c);
and my_and(ac, a, lowerInput);
assign lowerInput = notOutput;
and my_and2(bc, b, c);
or my_or(z, ac, bc);

initial
begin
    catch = 1;
    flag = $value$plusargs("a=%b", a); // if found in cmd line, flag = 1 else 0
    catch = catch & flag;
    flag = $value$plusargs("b=%b", b);
    catch = catch & flag;
    flag = $value$plusargs("c=%b", c);
    catch = catch & flag;
    #1;
    if (catch == 0)
    $display("One or more inputs missing");
    else
    $display("a=%b b=%b c=%b z=%b", a, b, c, z);
    $finish;
end

endmodule