uart tx

module transmitter(clk,reset,enable,parallel_in,serial_out,busy);
  input clk,reset,enable;
  input [7:0] parallel_in;
  output [7:0] serial_out;
  output busy;

  reg [7:0] data_reg=8'b0;
  reg [9:0] cycle_counter=4'b0;
  reg [3:0] bit_counter=4'b0;
  reg txd =1'b1;

  reg [2:0] state=0;
  reg [2:0] next_state=0;
  localparam CYCLES_PER_BIT=2;

  localparam IDLE = 0;
  localparam START= 1;
  localparam SEND = 2;
  localparam STOP = 3;

  wire next_bit = cycle_counter == CYCLES_PER_BIT;


  always@(posedge clk)begin

    state<=next_state;

    if (state == IDLE)
      begin
        txd<=1'b1;
      end
    else if (state == START)
      begin
        txd=1'b0;
        if(next_bit)
          cycle_counter<=4'b0000;
        else
          cycle_counter<=cycle_counter+1;
      end


    end
  always@(*)begin
    case(state)
      IDLE :next_state = enable ? START : IDLE;
      START:next_state = next_bit? SEND : START;


    endcase


  end
endmodule

module tb();
  reg clk,reset,enable;
  reg [7:0] parallel_in;
  wire [7:0] serial_out;
  wire busy;

  transmitter DUT(.clk(clk),.reset(reset),.enable(enable),.parallel_in(parallel_in),.serial_out(serial_out),.busy(busy));

  always#5 clk=~clk;

  initial begin
    $dumpfile("file.vcd");
    $dumpvars(0,tb);

    clk=1'b0;
    enable=1'b0;

    #10 enable=1'b1;


    #100 $finish;
  end
endmodule