20141002_KUAS_Verilog_HalfAdder(GateLevel)

/******************************************/
/** 20141002 Half Adder (Use Gate Level) **/
/** Maker  : Yan                         **/
/** E-Mail : [email protected]       **/
/** Date   : 2014/10/02 pm.10:00         **/
/******************************************/

module HalfAdder(input1, input2, sum, carry);
    input   input1, input2;
    output  sum, carry;

    xor (sum, input1, input2);
    and (carry, input1, input2);
endmodule