Advertisement
Guest User

Current ROM Progress

a guest
May 19th, 2018
161
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. ;----------------------------------------------------------------
  2. ; DEFINES
  3. ;----------------------------------------------------------------
  4. PPU_CTRL                = $2000
  5. PPU_MASK                = $2001
  6. PPU_STATUS              = $2002
  7. PPU_OAM_ADDR            = $2003
  8. PPU_OAM_DATA            = $2004
  9. PPU_SCROLL              = $2005
  10. PPU_ADDRESS             = $2006
  11. PPU_DATA                = $2007
  12. DMC_REG_1               = $4010
  13. PPU_OAM_DMA             = $4014
  14. CONTROLLER_1            = $4016
  15. CONTROLLER_2            = $4017
  16. ;----------------------------------------------------------------
  17. ; constants
  18. ;----------------------------------------------------------------
  19.  
  20. frameCounter            = $0900
  21. playerSpeed             = $0500
  22.  
  23. PRG_COUNT               = 1 ;1 = 16KB, 2 = 32KB
  24. MIRRORING               = %0001 ;%0000 = horizontal, %0001 = vertical, %1000 = four-screen
  25.  
  26. ;----------------------------------------------------------------
  27. ; variables
  28. ;----------------------------------------------------------------
  29.  
  30.    .enum $0000
  31.  
  32.    ;NOTE: declare variables using the DSB and DSW directives, like this:
  33.  
  34.    ;MyVariable0 .dsb 1
  35.    ;MyVariable1 .dsb 3
  36.  
  37.    .ende
  38.  
  39.    ;NOTE: you can also split the variable declarations into individual pages, like this:
  40.  
  41.    ;.enum $0100
  42.    ;.ende
  43.  
  44.    ;.enum $0200
  45.    ;.ende
  46.  
  47.    
  48. ;----------------------------------------------------------------
  49. ; iNES header
  50. ;----------------------------------------------------------------
  51.  
  52.    .db "NES", $1a ;identification of the iNES header
  53.    .db PRG_COUNT ;number of 16KB PRG-ROM pages
  54.    .db $01 ;number of 8KB CHR-ROM pages
  55.    .db $00|MIRRORING ;mapper 0 and mirroring
  56.    .dsb 9, $00 ;clear the remaining bytes
  57.  
  58. ;----------------------------------------------------------------
  59. ; program bank(s)
  60. ;----------------------------------------------------------------
  61.  
  62.    .base $10000-(PRG_COUNT*$4000)
  63.    
  64. palettes:
  65.     .db $0f,$00,$10,$30,$0f,$01,$12,$38,$0f,$04,$15,$26,$0f,$0f,$2d,$3d
  66.     .db $0f,$00,$10,$30,$0f,$01,$12,$38,$0f,$04,$15,$26,$0f,$0f,$2d,$3d
  67.  
  68.     ;  VERT-TILE-ATTR-HORIZ
  69. player_mSPRITE:
  70.     .db $80, $00, $00, $80
  71.     .db $80, $01, $00, $88
  72.     .db $80, $02, $00, $90
  73.     .db $88, $10, $00, $80
  74.     .db $88, $11, $00, $88
  75.     .db $88, $12, $00, $90
  76.    
  77. Reset:
  78.     SEI             ;Disable IRQs
  79.     CLD             ;Disable Decimal mode
  80.    
  81.     LDX #$40        ;Hex for binary flag 0100 0000 which inhibits and clears the frame interrupt flag
  82.     STX $4017       ;Disable Audio Processor frame IRQ
  83.    
  84.     LDX #$FF        ;Load 255 to stack
  85.     TXS             ;-----------------
  86.     INX             ;Overflow X to 0
  87.     STX PPU_CTRL    ;Set PPU CTRL flags to 0
  88.     STX PPU_MASK    ;Set PPU Mask flags to 0
  89.     STX DMC_REG_1       ;Set DMC flags to 0
  90.    ;NOTE: initialization code goes here
  91.  
  92. VBlankWait1:
  93.     BIT PPU_STATUS
  94.     BPL VBlankWait1
  95.    
  96. ClearMemory:
  97.     LDA #$00
  98.     STA $0000, x    ;Basically this clears out every RAM register by loading in 0
  99.     STA $0100, x
  100.     STA $0300, x
  101.     STA $0400, x
  102.     STA $0500, x
  103.     STA $0600, x
  104.     STA $0700, x
  105.     LDA #$FE
  106.     STA $0200, x
  107.     INX
  108.     BNE ClearMemory
  109.  
  110. VBlankWait2:
  111.     BIT PPU_STATUS
  112.     BPL VBlankWait2
  113.  
  114. ;This code tells the PPU to start accepting Background Palette data.
  115.  
  116.  
  117. InitPalettes:
  118.     LDA PPU_STATUS  ;Reads the PPU Status to reset the high/low latch
  119.    
  120.     LDA #$3F        ;Write the high byte of the PPU address
  121.     STA PPU_ADDRESS
  122.    
  123.     LDA #$00        ;Write the low byte of the PPU address
  124.     STA PPU_ADDRESS
  125.    
  126.     LDX #$00
  127.    
  128. LoadPalettes:
  129.     LDA palettes, x ;Load the current index of the palette using X as the index number;
  130.     STA PPU_DATA    ;Write the current index to the PPU Memory;
  131.     INX             ;Increment the index
  132.     CPX #$20        ;Compare the index against hex value 20(decimal: 32)
  133.     BNE LoadPalettes;Continue the loop until the index until the index hits hex 20(decimal: 32)
  134.  
  135. InitSprites:
  136.     LDX #$00
  137.  
  138. LoadSprites:
  139.     LDA player_mSPRITE, x   ;Same deal as the palette, but this time for the metasprite
  140.     STA $0200, x            ;Increment through each bit of RAM
  141.     INX
  142.     CPX #$18
  143.     BNE LoadSprites
  144.  
  145. PPUStart:
  146.     LDA #%10000000
  147.     STA PPU_CTRL
  148.    
  149.     LDA #%00010000
  150.     STA PPU_MASK
  151.    
  152.     LDX #$00
  153.  
  154. Update:
  155.     JMP Update
  156.    
  157. NMI:
  158.     LDA #$00        ;OAM low read write address value
  159.     STA PPU_OAM_ADDR;Set the low byte (00) of the RAM address
  160.    
  161.     LDA #$02        ;OAM high address value
  162.     STA PPU_OAM_DMA ;Set the high byte (02) of the RAM address, start the transfer
  163.    
  164.     INC frameCounter
  165.    
  166.    ;NOTE: NMI code goes here
  167.  
  168. LatchController:
  169.     LDA #$01
  170.     STA CONTROLLER_1
  171.     LDA #$00
  172.     STA CONTROLLER_1
  173.  
  174. ;==================================
  175. ;READ A BUTTON
  176. ;==================================
  177. ReadContA:
  178.     LDA CONTROLLER_1
  179.     AND #%00000001
  180.     BEQ ReadContADone
  181.  
  182. ReadContADone:
  183.  
  184. ;==================================
  185. ;READ B BUTTON
  186. ;==================================
  187. ReadContB:
  188.     LDA CONTROLLER_1
  189.     AND #%00000001
  190.     BEQ ReadContBDone
  191.    
  192. ReadContBDone:
  193.  
  194. ;==================================
  195. ;READ SELECT BUTTON
  196. ;==================================
  197. ReadContSelect:
  198.     LDA CONTROLLER_1
  199.     AND #%00000001
  200.     BEQ ReadContSelectDone
  201.  
  202. ReadContSelectDone:
  203.  
  204. ;==================================
  205. ;READ START BUTTON
  206. ;==================================
  207.  
  208. ReadContStart:
  209.     LDA CONTROLLER_1
  210.     AND #%00000001
  211.     BEQ ReadContStartDone
  212.    
  213. ReadContStartDone:
  214.  
  215. ;==================================
  216. ;READ UP BUTTON
  217. ;==================================
  218. ReadContUp:
  219.     LDA CONTROLLER_1
  220.     AND #%00000001
  221.     BEQ ReadContUpDone
  222.  
  223. ReadContUpDone:
  224.  
  225. ;==================================
  226. ;READ DOWN BUTTON
  227. ;==================================
  228.  
  229. ReadContDown:
  230.     LDA CONTROLLER_1
  231.     AND #%00000001
  232.     BEQ ReadContDownDone
  233.    
  234. ReadContDownDone:
  235.    
  236. ;==================================
  237. ;READ LEFT BUTTON
  238. ;==================================
  239.  
  240. ReadContLeft:
  241.     LDA CONTROLLER_1
  242.     AND #%00000001
  243.     BEQ ReadContLeftDone
  244.    
  245.     LDA $0203
  246.     SEC
  247.     SBC #$01
  248.     STA $0203
  249.    
  250.     LDA $0207
  251.     SEC
  252.     SBC #$01
  253.     STA $0207
  254.    
  255.     LDA $020B
  256.     SEC
  257.     SBC #$01
  258.     STA $020B
  259.    
  260.     LDA $020F
  261.     SEC
  262.     SBC #$01
  263.     STA $020F
  264.    
  265. ReadContLeftDone:
  266.  
  267. ;==================================
  268. ;READ RIGHT BUTTON
  269. ;==================================
  270.  
  271. ReadContRight:
  272.     LDA CONTROLLER_1
  273.     AND #%00000001
  274.     BEQ ReadContRightDone
  275.    
  276.     LDA $0203
  277.     CLC
  278.     ADC #$01
  279.     STA $0203
  280.    
  281.     LDA $0207
  282.     CLC
  283.     ADC #$01
  284.     STA $0207
  285.    
  286.     LDA $020B
  287.     CLC
  288.     ADC #$01
  289.     STA $020B
  290.    
  291.     LDA $020F
  292.     CLC
  293.     ADC #$01
  294.     STA $020F
  295.  
  296.    
  297. ReadContRightDone:     
  298.  
  299.    
  300. IRQ:
  301.    ;NOTE: IRQ code goes here
  302.    
  303. ;----------------------------------------------------------------
  304. ; interrupt vectors
  305. ;----------------------------------------------------------------
  306.  
  307.    .org $fffa
  308.  
  309.    .dw NMI
  310.    .dw Reset
  311.    .dw IRQ
  312.  
  313.    
  314. ;----------------------------------------------------------------
  315. ; CHR-ROM bank
  316. ;----------------------------------------------------------------
  317.  
  318.     .incbin "tiles.chr"
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement