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  1. ===================================================================
  2.  
  3. ..MT7621 stage1 code done
  4.  
  5. ..CPU=50000000 HZ BUS=12500000 HZ
  6.  
  7. ===================================================================
  8.  
  9.  
  10.  
  11. U-Boot 1.1.3 (Jul 14 2017 - 15:16:26)
  12.  
  13. Board: Ralink APSoC DRAM: 256 MB
  14. Power on memory test. Memory size= 256 MB...OK!
  15. relocate_code Pointer at: 8ffac000
  16.  
  17. Config XHCI 40M PLL
  18. ******************************
  19. Software System Reset Occurred
  20. ******************************
  21. Allocate 16 byte aligned buffer: 8ffdff50
  22. Enable NFI Clock
  23. # MTK NAND # : Use HW ECC
  24. NAND ID [C8 D1 80 95 40]
  25. Device not found, ID: c8d1
  26. Not Support this Device!
  27.  
  28. chip_mode=00000001
  29. Support this Device in MTK table! c8d1
  30.  
  31. select_chip
  32. [NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
  33. Signature matched and data read!
  34. load_fact_bbt success 1023
  35. load fact bbt success
  36. [mtk_nand] probe successfully!
  37. mtd->writesize=2048 mtd->oobsize=64,.mtd->erasesize=131072 devinfo.iowidth=8
  38. ..============================================
  39. Ralink UBoot Version: 5.0.0.0
  40. --------------------------------------------
  41. ASIC MT7621A DualCore (MAC to MT7530 Mode)
  42. DRAM_CONF_FROM: Auto-Detection
  43. DRAM_TYPE: DDR3
  44. DRAM bus: 16 bit
  45. Xtal Mode=5 OCP Ratio=1/4
  46. Flash component: NAND Flash
  47. Date:Jul 14 2017 Time:15:16:26
  48. ============================================
  49. icache: sets:256, ways:4, linesz:32 ,total:32768
  50. dcache: sets:256, ways:4, linesz:32 ,total:32768
  51.  
  52. ##### The CPU freq = 880 MHZ ####
  53. estimate memory size =256 Mbytes
  54. #Reset_MT7530
  55. set LAN/WAN LWLLL
  56.  
  57. Please choose the operation:
  58. 1: Load system code to SDRAM via TFTP.
  59. 2: Load system code then write to Flash via TFTP.
  60. 3: Boot system code via Flash (default).
  61. 4: Entr boot command line interface.
  62. 7: Load Boot Loader code then write to Flash via Serial.
  63. 9: Load Boot Loader code then write to Flash via TFTP.
  64.  
  65. Boot failure detected on both systems
  66. Verifying kernel1 uImage CRC, addr: 0xbc200000
  67. Bad Magic Number,FFFFFFFF
  68. Verifying kernel2 uImage CRC, addr: 0xbc600000
  69. Bad Magic Number,FFFFFFFF
  70. Booting System 2
  71. ..ranand_erase: start:80000, len:20000
  72. ..Done!
  73. done
  74.  
  75. 3: System Boot system code via Flash.
  76. ## Booting image at bc600000 ...
  77. Bad Magic Number,FFFFFFFF, try to reboot
  78. ..ranand_erase: start:80000, len:20000
  79. ..Done!
  80. done
  81.  
  82. ===================================================================
  83.  
  84. ..MT7621 stage1 code 10:33:11 (ASIC)
  85.  
  86. ..CPU=50000000 HZ BUS=12500000 HZ
  87.  
  88. ==================================================================
  89.  
  90. Change MPLL source from XTAL to CR...
  91.  
  92. do MEMPLL setting..
  93.  
  94. MEMPLL Config : 0x11100000
  95.  
  96. 3PLL mode + External loopback
  97.  
  98. === XTAL-40Mhz === DDR-1200Mhz ===
  99.  
  100. PLL4 FB_DL: 0xf, 1/0 = 682/342 3D000000
  101.  
  102. PLL3 FB_DL: 0x12, 1/0 = 665/359 49000000
  103.  
  104. PLL2 FB_DL: 0x17, 1/0 = 605/419 5D000000
  105.  
  106. do DDR setting..[00320381]
  107.  
  108. Apply DDR3 Setting...(use customer AC)
  109.  
  110. 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
  111.  
  112. --------------------------------------------------------------------------------
  113.  
  114. 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  115.  
  116. 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  117.  
  118. 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  119.  
  120. 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  121.  
  122. 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  123.  
  124. 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  125.  
  126. 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  127.  
  128. 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  129.  
  130. 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  131.  
  132. 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  133.  
  134. 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  135.  
  136. 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  137.  
  138. 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  139.  
  140. 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
  141.  
  142. 000E:| 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
  143.  
  144. 000F:| 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0
  145.  
  146. 0010:| 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
  147.  
  148. 0011:| 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
  149.  
  150. 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  151.  
  152. 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  153.  
  154. 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  155.  
  156. 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  157.  
  158. 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  159.  
  160. 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  161.  
  162. 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  163.  
  164. 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  165.  
  166. 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  167.  
  168. 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  169.  
  170. 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  171.  
  172. 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  173.  
  174. 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  175.  
  176. 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  177.  
  178. rank 0 coarse = 15
  179.  
  180. rank 0 fine = 72
  181.  
  182. B:| 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0
  183.  
  184. opt_dle value:11
  185.  
  186. DRAMC_R0DELDLY[018]=00001E20
  187.  
  188. ==================================================================
  189.  
  190. ..RX.DQS perbit delay software calibration
  191.  
  192. ==================================================================
  193.  
  194. 1.0-15 bit dq delay value
  195.  
  196. ==================================================================
  197.  
  198. bit| 0 1 2 3 4 5 6 7 8 9
  199.  
  200. --------------------------------------
  201.  
  202. 0 | 9 7 8 9 6 7 7 7 3 5
  203.  
  204. 10 | 5 7 7 7 5 6
  205.  
  206. --------------------------------------
  207.  
  208.  
  209.  
  210. ==================================================================
  211.  
  212. 2.dqs window
  213.  
  214. x=pass dqs delay value (min~max)center
  215.  
  216. y=0-7bit DQ of every group
  217.  
  218. input delay:DQS0 =32 DQS1 = 30
  219.  
  220. ==================================================================
  221.  
  222. bit.DQS0. bit DQS1
  223.  
  224. 0 (1~58)29 8 (1~57)29
  225.  
  226. 1 (1~57)29 9 (1~56)28
  227.  
  228. 2 (1~57)29 10 (0~56)28
  229.  
  230. 3 (1~58)29 11 (2~57)29
  231.  
  232. 4 (0~61)30 12 (1~60)30
  233.  
  234. 5 (1~60)30 13 (1~57)29
  235.  
  236. 6 (1~60)30 14 (1~58)29
  237.  
  238. 7 (1~64)32 15 (1~58)29
  239.  
  240. ==================================================================
  241.  
  242. 3.dq delay value last
  243.  
  244. ==================================================================
  245.  
  246. bit| 0 1 2 3 4 5 6 7 8 9
  247.  
  248. --------------------------------------
  249.  
  250. 0 | 12 10 11 12 8 9 9 7 4 7
  251.  
  252. 10 | 7 8 7 8 6 7
  253.  
  254. ==================================================================
  255.  
  256. ==================================================================
  257.  
  258. TX perbyte calibration
  259.  
  260. ==================================================================
  261.  
  262. DQS loop = 15, cmp_err_1 = ffff0000
  263.  
  264. dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
  265.  
  266. dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
  267.  
  268. DQ loop=15, cmp_err_1 = ffff00a0
  269.  
  270. dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=1
  271.  
  272. DQ loop=14, cmp_err_1 = ffff0000
  273.  
  274. dqs_perbyte_dly.last_dqdly_pass[0]=14, finish count=2
  275.  
  276. byte:0, (DQS,DQ)=(8,8)
  277.  
  278. byte:1, (DQS,DQ)=(8,8)
  279.  
  280. 20,data:88
  281.  
  282. [EMI] DRAMC calibration passed
  283.  
  284.  
  285.  
  286.  
  287. ===================================================================
  288.  
  289. ..MT7621 stage1 code done
  290.  
  291. ..CPU=50000000 HZ BUS=12500000 HZ
  292.  
  293. ===================================================================
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