module half_adder(
    input a,
    input b,
    output sum,
    output Cout
    );

    assign sum = a ^ b;
    assign Cout = a & b;

endmodule

module full_adder(
    input Cin,
    input a,
    input b,
    output sum,
    output Cout
    );

    wire sum1_w;
    wire Cout1_w;
    wire Cout2_w;

    //Half adder 1

    half_adder half_add1 (.a(a), .b(b), .sum(sum1_w), .Cout(Cout1_w));

    //Half adder 2

    half_adder half_add2 (.a(Cin), .b(sum1_w), .sum(sum), .Cout(Cout2_w));

    //Resulting OR gate

    or or_cout (Cout, Cout1_w, Cout2_w);

endmodule

module adder(
    input [31:0] a,
    input [31:0] b,
    output [31:0] c
    );

    wire [31:0] carry;
    genvar i;
    for (i = 0; i < 32; i = i + 1) begin
        if(i==0)
        half_adder half_add (.a(a[0]), .b(b[0]), .sum(c[0]), .Cout(carry[0]));

        else
        full_adder full_add (.Cin(carry[i-1]), .a(a[i]), .b(b[i]), .sum(c[i]), .Cout(carry[i]));

    end

endmodule

module counter(
    input clk,
    input reset,
    input enable,
    output [3:0] count
    );

    reg [0:31] a;
    reg [0:31] b = 32'b00000000000000000000000000000001;
    // b starts as 1, a as 0

always @(posedge clk) begin

    if (enable == 1'b1 && reset == 1'b0) begin

        adder adder_count(.a(a), .b(b), .c(count));

        // every step:  a + 1 = c
        // a becomes c
        // repeat
    end


     if (reset == 1'b1) begin
         //reset

     end
end

endmodule

always @(posedge clock) begin
  if (reset) begin
    count <= 0;
  end else begin
    count <= count + 1;
  end
end

always @(posedge clock) count <= reset ? 0 : count + 1;