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  1. module half_adder(
  2.     input a,
  3.     input b,
  4.     output sum,
  5.     output Cout
  6.     );
  7.  
  8.     assign sum = a ^ b;
  9.     assign Cout = a & b;
  10.  
  11. endmodule
  12.  
  13. module full_adder(
  14.     input Cin,
  15.     input a,
  16.     input b,
  17.     output sum,
  18.     output Cout
  19.     );
  20.  
  21.     wire sum1_w;
  22.     wire Cout1_w;
  23.     wire Cout2_w;
  24.  
  25.     //Half adder 1
  26.  
  27.     half_adder half_add1 (.a(a), .b(b), .sum(sum1_w), .Cout(Cout1_w));
  28.  
  29.     //Half adder 2
  30.  
  31.     half_adder half_add2 (.a(Cin), .b(sum1_w), .sum(sum), .Cout(Cout2_w));  
  32.  
  33.     //Resulting OR gate
  34.  
  35.     or or_cout (Cout, Cout1_w, Cout2_w);
  36.  
  37. endmodule
  38.  
  39. module adder(
  40.     input [31:0] a,
  41.     input [31:0] b,
  42.     output [31:0] c
  43.     );
  44.  
  45.     wire [31:0] carry;
  46.     genvar i;
  47.     for (i = 0; i < 32; i = i + 1) begin
  48.         if(i==0)
  49.         half_adder half_add (.a(a[0]), .b(b[0]), .sum(c[0]), .Cout(carry[0]));
  50.  
  51.         else
  52.         full_adder full_add (.Cin(carry[i-1]), .a(a[i]), .b(b[i]), .sum(c[i]), .Cout(carry[i]));
  53.  
  54.     end
  55.  
  56. endmodule
  57.  
  58. module counter(
  59.     input clk,
  60.     input reset,
  61.     input enable,
  62.     output [3:0] count
  63.     );
  64.  
  65.     reg [0:31] a;
  66.     reg [0:31] b = 32'b00000000000000000000000000000001;
  67.     // b starts as 1, a as 0
  68.  
  69. always @(posedge clk) begin
  70.  
  71.     if (enable == 1'b1 && reset == 1'b0) begin
  72.  
  73.         adder adder_count(.a(a), .b(b), .c(count));
  74.  
  75.         // every step:  a + 1 = c
  76.         // a becomes c
  77.         // repeat
  78.     end
  79.  
  80.  
  81.      if (reset == 1'b1) begin
  82.          //reset
  83.  
  84.      end
  85. end
  86.  
  87. endmodule
  88.      
  89. always @(posedge clock) begin
  90.   if (reset) begin
  91.     count <= 0;
  92.   end else begin
  93.     count <= count + 1;
  94.   end
  95. end
  96.      
  97. always @(posedge clock) count <= reset ? 0 : count + 1;
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