// File: vga_timing.v
// This is the vga timing design for EE178 Lab #4.

// The `timescale directive specifies what the
// simulation time units are (1 ns here) and what
// the simulator time step should be (1 ps here).

//https://timetoexplore.net/blog/video-timings-vga-720p-1080p
//https://learn.digilentinc.com/Documents/269
//https://timetoexplore.net/blog/arty-fpga-vga-verilog-01

`timescale 1 ns / 1 ps

// Declare the module and its ports. This is
// using Verilog-2001 syntax.

module vga_timing (
  output reg [10:0] vcount,
  output reg vsync,
  output reg vblnk,
  output reg [10:0] hcount,
  output reg hsync,
  output reg hblnk,
  input wire pclk,
  input wire rst
  );

// Describe the actual circuit for the assignment.
// Video timing controller set for 800x600@60fps
// using a 40 MHz pixel clock per VESA spec.

//Time in horizontal lines
    parameter HorTimeWidth = 10'd128;
    parameter HorFrontPorch = 10'd40;
    parameter HorBackPorch = 10'd88;
    parameter HorTimeToDisplay = 10'd800;
    parameter HorTotalTime = 12'd1056;
    parameter HorSyncStart = 10'd840;

//Time in Vertincal lines
    parameter VerTimeWidth = 10'd4;
    parameter VerFrontPorch = 10'd1;
    parameter VerBackPorch = 10'd23;
    parameter VerTimeToDisplay = 10'd600;
    parameter VerTotalTime = 10'd628;
    parameter VerSyncStart = 10'd601;

    parameter initial_borders = 10'b0;

//Horizontal counter
always @(posedge pclk or posedge rst)
    if (rst)
        hcount <= initial_borders;
    else
        begin
            if (hcount == HorTotalTime)
                hcount <= initial_borders;
            else
                hcount <= hcount + 1;
        end

//Vertical counter
always @(posedge pclk or posedge rst)
    if (rst)
        vcount <= initial_borders;
    else begin
        if (hcount == HorTotalTime)
            begin
                if (vcount == VerTotalTime)
                    vcount <= initial_borders;
                else
                    vcount <= vcount +1;
            end
    end

always @* begin

    if (hcount >= HorSyncStart && hcount <= (HorSyncStart + HorTimeWidth)) begin
        hsync = 1;
    end
    else begin
        hsync = 0;
    end

    if (vcount >= VerSyncStart && vcount <= (VerSyncStart + VerTimeWidth)) begin
        vsync = 1;
    end
    else begin
        vsync = 0;
    end

    if (hcount >= HorTimeToDisplay) begin
        hblnk = 1;
    end
    else begin
        hblnk = 0;
    end

    if (vcount >= VerTimeToDisplay) begin
        vblnk = 1;
    end
    else begin
        vblnk = 0;
    end

end
endmodule