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  1. #cpudef "CPU_65C02_NS"
  2. {
  3. #bits 8
  4.  
  5. ;------------------------------------------------------------------------------ (++ means new Instruction, +* means new Addressing Mode)
  6. ; () <- Absolute Address
  7. ; [] <- Zeropage Address
  8. ;
  9. ; example:
  10. ; LD A, [0x76,X]
  11. ; This loads into Register A, from a Zeropage location pointed by 0x76 + Register X
  12. ;------------------------------------------------------------------------------
  13. ; Add with Carry
  14. ADD {src} -> 0x69[7:0] @ src[7:0]
  15. ADD [{src}] -> 0x65[7:0] @ src[7:0]
  16. ADD [{src},X] -> 0x75[7:0] @ src[7:0]
  17. ADD ({src}) -> 0x6D[7:0] @ src[7:0] @ src[15:8]
  18. ADD ({src},X) -> 0x7D[7:0] @ src[7:0] @ src[15:8]
  19. ADD ({src},Y) -> 0x79[7:0] @ src[7:0] @ src[15:8]
  20. ADD ([{src},X]) -> 0x61[7:0] @ src[7:0]
  21. ADD ([{src}],Y) -> 0x71[7:0] @ src[7:0]
  22. ADD ([{src}]) -> 0x72[7:0] @ src[7:0] ; +*
  23.  
  24. ;------------------------------------------------------------------------------
  25. ; Logic AND
  26. AND {src} -> 0x29[7:0] @ src[7:0]
  27. AND [{src}] -> 0x25[7:0] @ src[7:0]
  28. AND [{src},X] -> 0x35[7:0] @ src[7:0]
  29. AND ({src}) -> 0x2D[7:0] @ src[7:0] @ src[15:8]
  30. AND ({src},X) -> 0x3D[7:0] @ src[7:0] @ src[15:8]
  31. AND ({src},Y) -> 0x39[7:0] @ src[7:0] @ src[15:8]
  32. AND ([{src},X]) -> 0x21[7:0] @ src[7:0]
  33. AND ([{src}],Y) -> 0x31[7:0] @ src[7:0]
  34. AND ([{src}]) -> 0x32[7:0] @ src[7:0] ; +*
  35.  
  36. ;------------------------------------------------------------------------------
  37. ; Arithmetic Shift Left
  38. SFL A -> 0x0A[7:0]
  39. SFL [{src}] -> 0x07[7:0] @ src[7:0]
  40. SFL [{src},X] -> 0x16[7:0] @ src[7:0]
  41. SFL ({src}) -> 0x0E[7:0] @ src[7:0] @ src[15:8]
  42. SFL ({src},X) -> 0x1E[7:0] @ src[7:0] @ src[15:8]
  43.  
  44. ;------------------------------------------------------------------------------
  45. ; Branch Always ++
  46. JR {src} -> 0x80[7:0] @ (src - (pc - 2))[7:0]
  47.  
  48. ;------------------------------------------------------------------------------
  49. ; Branch on Bit Clear/Reset ++
  50. JR NB0 {src},{src1} -> 0x0F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  51. JR NB1 {src},{src1} -> 0x1F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  52. JR NB2 {src},{src1} -> 0x2F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  53. JR NB3 {src},{src1} -> 0x3F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  54. JR NB4 {src},{src1} -> 0x4F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  55. JR NB5 {src},{src1} -> 0x5F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  56. JR NB6 {src},{src1} -> 0x6F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  57. JR NB7 {src},{src1} -> 0x7F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  58.  
  59. ;------------------------------------------------------------------------------
  60. ; Branch on Bit Set ++
  61. JR B0 {src},{src1} -> 0x8F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  62. JR B1 {src},{src1} -> 0x9F[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  63. JR B2 {src},{src1} -> 0xAF[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  64. JR B3 {src},{src1} -> 0xBF[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  65. JR B4 {src},{src1} -> 0xCF[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  66. JR B5 {src},{src1} -> 0xDF[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  67. JR B6 {src},{src1} -> 0xEF[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  68. JR B7 {src},{src1} -> 0xFF[7:0] @ src[7:0] @ (src1 - (pc - 2))[7:0]
  69.  
  70. ;------------------------------------------------------------------------------
  71. ; Branch on Carry Clear
  72. JR NC {src} -> 0x90[7:0] @ (src - (pc - 2))[7:0]
  73.  
  74. ;------------------------------------------------------------------------------
  75. ; Branch on Carry Set
  76. JR C {src} -> 0xB0[7:0] @ (src - (pc - 2))[7:0]
  77.  
  78. ;------------------------------------------------------------------------------
  79. ; Branch on Equal (Zero Set)
  80. JR Z {src} -> 0xF0[7:0] @ (src - (pc - 2))[7:0]
  81.  
  82. ;------------------------------------------------------------------------------
  83. ; Bit Test
  84. BIT {src} -> 0x89[7:0] @ src[7:0] ; +*
  85. BIT [{src}] -> 0x24[7:0] @ src[7:0]
  86. BIT [{src},X] -> 0x34[7:0] @ src[7:0] ; +*
  87. BIT ({src}) -> 0x2C[7:0] @ src[7:0] @ src[15:8]
  88. BIT ({src},X) -> 0x3C[7:0] @ src[7:0] @ src[15:8] ; +*
  89.  
  90. ;------------------------------------------------------------------------------
  91. ; Branch on Minus (Negative Set)
  92. JR N {src} -> 0x30[7:0] @ (src - (pc - 2))[7:0]
  93.  
  94. ;------------------------------------------------------------------------------
  95. ; Branch on Not Equal (Zero Clear)
  96. JR NZ {src} -> 0xD0[7:0] @ (src - (pc - 2))[7:0]
  97.  
  98. ;------------------------------------------------------------------------------
  99. ; Branch on Plus (Negative Clear)
  100. JR NN {src} -> 0x10[7:0] @ (src - (pc - 2))[7:0]
  101.  
  102. ;------------------------------------------------------------------------------
  103. ; Break (Interrupt)
  104. BRK -> 0x00[7:0]
  105. INT -> 0x00[7:0]
  106.  
  107. ;------------------------------------------------------------------------------
  108. ; Branch on Overflow Clear
  109. JR NV {src} -> 0x50[7:0] @ (src - (pc - 2))[7:0]
  110.  
  111. ;------------------------------------------------------------------------------
  112. ; Branch on Overflow Set
  113. JR V {src} -> 0x70[7:0] @ (src - (pc - 2))[7:0]
  114.  
  115. ;------------------------------------------------------------------------------
  116. ; Clear Carry
  117. CLR C -> 0x18[7:0]
  118.  
  119. ;------------------------------------------------------------------------------
  120. ; Clear Decimal
  121. CLR D -> 0xD8[7:0]
  122.  
  123. ;------------------------------------------------------------------------------
  124. ; Clear Interrupt Disable
  125. CLR I -> 0x58[7:0]
  126.  
  127. ;------------------------------------------------------------------------------
  128. ; Clear Overflow
  129. CLR V -> 0xB8[7:0]
  130.  
  131. ;------------------------------------------------------------------------------
  132. ; Compare with Accumulator
  133. CMP {src} -> 0xC9[7:0] @ src[7:0]
  134. CMP [{src} -> 0xC5[7:0] @ src[7:0]
  135. CMP [{src},X -> 0xD5[7:0] @ src[7:0]
  136. CMP ({src}) -> 0xCD[7:0] @ src[7:0] @ src[15:8]
  137. CMP ({src},X) -> 0xDD[7:0] @ src[7:0] @ src[15:8]
  138. CMP ({src},Y) -> 0xD9[7:0] @ src[7:0] @ src[15:8]
  139. CMP ([{src},X]) -> 0xC1[7:0] @ src[7:0]
  140. CMP ([{src}],Y) -> 0xD1[7:0] @ src[7:0]
  141. CMP ([{src}]) -> 0xD2[7:0] @ src[7:0] ; +*
  142.  
  143. ;------------------------------------------------------------------------------
  144. ; Compare with X
  145. CPX {src} -> 0xE0[7:0] @ src[7:0]
  146. CPX [{src}] -> 0xE4[7:0] @ src[7:0]
  147. CPX ({src}) -> 0xEC[7:0] @ src[7:0] @ src[15:8]
  148.  
  149. ;------------------------------------------------------------------------------
  150. ; Compare with Y
  151. CPY {src} -> 0xC0[7:0] @ src[7:0]
  152. CPY [{src}] -> 0xC4[7:0] @ src[7:0]
  153. CPY ({src}) -> 0xCC[7:0] @ src[7:0] @ src[15:8]
  154.  
  155. ;------------------------------------------------------------------------------
  156. ; Decrement
  157. DEC A -> 0x1A[7:0] ; +*
  158. DEC [{src}] -> 0xC6[7:0] @ src[7:0]
  159. DEC [{src},X] -> 0xD6[7:0] @ src[7:0]
  160. DEC ({src}) -> 0xCE[7:0] @ src[7:0] @ src[15:8]
  161. DEC ({src},X) -> 0xDE[7:0] @ src[7:0] @ src[15:8]
  162.  
  163. ;------------------------------------------------------------------------------
  164. ; Decrement X
  165. DEC X -> 0xCA[7:0]
  166.  
  167. ;------------------------------------------------------------------------------
  168. ; Decrement Y
  169. DEC Y -> 0x88[7:0]
  170.  
  171. ;------------------------------------------------------------------------------
  172. ; Logic XOR
  173. XOR {src} -> 0x49[7:0] @ src[7:0]
  174. XOR [{src}] -> 0x45[7:0] @ src[7:0]
  175. XOR [{src},X] -> 0x55[7:0] @ src[7:0]
  176. XOR ({src}) -> 0x4D[7:0] @ src[7:0] @ src[15:8]
  177. XOR ({src},X) -> 0x5D[7:0] @ src[7:0] @ src[15:8]
  178. XOR ({src},Y) -> 0x59[7:0] @ src[7:0] @ src[15:8]
  179. XOR ({src},X) -> 0x41[7:0] @ src[7:0]
  180. XOR ({src},Y) -> 0x51[7:0] @ src[7:0]
  181. XOR ({src}) -> 0x52[7:0] @ src[7:0] ; +*
  182.  
  183. ;------------------------------------------------------------------------------
  184. ; Increment
  185. INC A -> 0x3A[7:0] ; +*
  186. INC [{src}] -> 0xE6[7:0] @ src[7:0]
  187. INC [{src},X] -> 0xF6[7:0] @ src[7:0]
  188. INC ({src}) -> 0xEE[7:0] @ src[7:0] @ src[15:8]
  189. INC ({src},X) -> 0xFE[7:0] @ src[7:0] @ src[15:8]
  190.  
  191. ;------------------------------------------------------------------------------
  192. ; Increment X
  193. INC X -> 0xE8[7:0]
  194.  
  195. ;------------------------------------------------------------------------------
  196. ; Increment Y
  197. INC Y -> 0xC8[7:0]
  198.  
  199. ;------------------------------------------------------------------------------
  200. ; Jump
  201. JMP {src} -> 0x4C[7:0] @ src[7:0] @ src[15:8]
  202. JMP ({src}) -> 0x6C[7:0] @ src[7:0] @ src[15:8]
  203. JMP ({src},X) -> 0x7C[7:0] @ src[7:0] @ src[15:8]
  204.  
  205. ;------------------------------------------------------------------------------
  206. ; Jump Subroutine
  207. CALL {src} -> 0x20[7:0] @ src[7:0] @ src[15:8]
  208.  
  209. ;------------------------------------------------------------------------------
  210. ; Load Accumulator
  211. LD A, {src} -> 0xA9[7:0] @ src[7:0]
  212. LD A, [{src}] -> 0xA5[7:0] @ src[7:0]
  213. LD A, [{src},X] -> 0xB5[7:0] @ src[7:0]
  214. LD A, ({src}) -> 0xAD[7:0] @ src[7:0] @ src[15:8]
  215. LD A, ({src},X) -> 0xBD[7:0] @ src[7:0] @ src[15:8]
  216. LD A, ({src},Y) -> 0xB9[7:0] @ src[7:0] @ src[15:8]
  217. LD A, ([{src},X]) -> 0xA1[7:0] @ src[7:0]
  218. LD A, ([{src}],Y) -> 0xB1[7:0] @ src[7:0]
  219. LD A, ([{src}]) -> 0xB2[7:0] @ src[7:0] ; +*
  220.  
  221. ;------------------------------------------------------------------------------
  222. ; Load X
  223. LD X, {src} -> 0xA2[7:0] @ src[7:0]
  224. LD X, [{src}] -> 0xA6[7:0] @ src[7:0]
  225. LD X, [{src},Y] -> 0xB6[7:0] @ src[7:0]
  226. LD X, ({src}) -> 0xAE[7:0] @ src[7:0] @ src[15:8]
  227. LD X, ({src},Y) -> 0xBE[7:0] @ src[7:0] @ src[15:8]
  228.  
  229. ;------------------------------------------------------------------------------
  230. ; Load Y
  231. LD Y, {src} -> 0xA0[7:0] @ src[7:0]
  232. LD Y, [{src}] -> {assert({src} <= 0xFF), 0xA4[7:0] @ src[7:0]}
  233. LD Y, [{src},X] -> {assert({src} <= 0xFF), 0xB4[7:0] @ src[7:0]}
  234. LD Y, ({src}) -> {assert({src} > 0xFF), 0xAC[7:0] @ src[7:0] @ src[15:8]}
  235. LD Y, ({src},X) -> {assert({src} > 0xFF), 0xBE[7:0] @ src[7:0] @ src[15:8]}
  236.  
  237. ;------------------------------------------------------------------------------
  238. ; Logical Shift Right
  239. SFR A -> 0x4A[7:0]
  240. SFR [{src}] -> 0x46[7:0] @ src[7:0]
  241. SFR [{src},X] -> 0x56[7:0] @ src[7:0]
  242. SFR ({src}) -> 0x4E[7:0] @ src[7:0] @ src[15:8]
  243. SFR ({src},X) -> 0x5E[7:0] @ src[7:0] @ src[15:8]
  244.  
  245. ;------------------------------------------------------------------------------
  246. ; No Operation
  247. NOP -> 0xEA[7:0]
  248.  
  249. ;------------------------------------------------------------------------------
  250. ; Logic OR
  251. OR {src} -> 0x09[7:0] @ src[7:0]
  252. OR [{src}] -> 0x06[7:0] @ src[7:0]
  253. OR [{src},X] -> 0x15[7:0] @ src[7:0]
  254. OR ({src}) -> 0x0D[7:0] @ src[7:0] @ src[15:8]
  255. OR ({src},X) -> 0x1D[7:0] @ src[7:0] @ src[15:8]
  256. OR ({src},Y) -> 0x19[7:0] @ src[7:0] @ src[15:8]
  257. OR ([{src},X]) -> 0x01[7:0] @ src[7:0]
  258. OR ([{src}],Y) -> 0x11[7:0] @ src[7:0]
  259. OR ([{src}]) -> 0x12[7:0] @ src[7:0] ; +*
  260.  
  261. ;------------------------------------------------------------------------------
  262. ; Push Accumulator
  263. PUSH A -> 0x48[7:0]
  264.  
  265. ;------------------------------------------------------------------------------
  266. ; Push Processor Status
  267. PUSH SR -> 0x08[7:0]
  268.  
  269. ;------------------------------------------------------------------------------
  270. ; Push X Register ++
  271. PUSH X -> 0xDA[7:0]
  272.  
  273. ;------------------------------------------------------------------------------
  274. ; Push Y Register ++
  275. PUSH Y -> 0x5A[7:0]
  276.  
  277. ;------------------------------------------------------------------------------
  278. ; Pull Accumulator
  279. POP A -> 0x68[7:0]
  280.  
  281. ;------------------------------------------------------------------------------
  282. ; Pull Processor Status
  283. POP SR -> 0x28[7:0]
  284.  
  285. ;------------------------------------------------------------------------------
  286. ; Pull X Register ++
  287. POP X -> 0xFA[7:0]
  288.  
  289. ;------------------------------------------------------------------------------
  290. ; Pull Y Register ++
  291. POP Y -> 0x7A[7:0]
  292.  
  293. ;------------------------------------------------------------------------------
  294. ; Reset Memory Bit ++
  295. CLR B0, [{src}] -> 0x07[7:0] @ src[7:0]
  296. CLR B1, [{src}] -> 0x17[7:0] @ src[7:0]
  297. CLR B2, [{src}] -> 0x27[7:0] @ src[7:0]
  298. CLR B3, [{src}] -> 0x37[7:0] @ src[7:0]
  299. CLR B4, [{src}] -> 0x47[7:0] @ src[7:0]
  300. CLR B5, [{src}] -> 0x57[7:0] @ src[7:0]
  301. CLR B6, [{src}] -> 0x67[7:0] @ src[7:0]
  302. CLR B7, [{src}] -> 0x77[7:0] @ src[7:0]
  303.  
  304. ;------------------------------------------------------------------------------
  305. ; Rotate Left
  306. ROL A -> 0x2A[7:0]
  307. ROL [{src}] -> 0x26[7:0] @ src[7:0]
  308. ROL [{src},X] -> 0x36[7:0] @ src[7:0]
  309. ROL ({src}) -> 0x2E[7:0] @ src[7:0] @ src[15:8]
  310. ROL ({src},X) -> 0x3E[7:0] @ src[7:0] @ src[15:8]
  311.  
  312. ;------------------------------------------------------------------------------
  313. ; Rotate Right
  314. ROR A -> 0x6A[7:0]
  315. ROR [{src}] -> 0x66[7:0] @ src[7:0]
  316. ROR [{src},X] -> 0x76[7:0] @ src[7:0]
  317. ROR ({src}) -> 0x6E[7:0] @ src[7:0] @ src[15:8]
  318. ROR ({src},X) -> 0x7E[7:0] @ src[7:0] @ src[15:8]
  319.  
  320. ;------------------------------------------------------------------------------
  321. ; Return from Interrupt
  322. RETI -> 0x40[7:0]
  323.  
  324. ;------------------------------------------------------------------------------
  325. ; Return from Subroutine
  326. RET -> 0x60[7:0]
  327.  
  328. ;------------------------------------------------------------------------------
  329. ; Subtract with Carry
  330. SUB {src} -> 0xE9[7:0] @ src[7:0]
  331. SUB [{src}] -> 0xE5[7:0] @ src[7:0]
  332. SUB [{src},X] -> 0xF5[7:0] @ src[7:0]
  333. SUB ({src}) -> 0xED[7:0] @ src[7:0] @ src[15:8]
  334. SUB ({src},X) -> 0xFD[7:0] @ src[7:0] @ src[15:8]
  335. SUB ({src},Y) -> 0xF9[7:0] @ src[7:0] @ src[15:8]
  336. SUB ([{src},X]) -> 0xE1[7:0] @ src[7:0]
  337. SUB ([{src}],Y) -> 0xF1[7:0] @ src[7:0]
  338. SUB ([{src}]) -> 0xF2[7:0] @ src[7:0] ; +*
  339.  
  340. ;------------------------------------------------------------------------------
  341. ; Set Carry
  342. SET C -> 0x38[7:0]
  343.  
  344. ;------------------------------------------------------------------------------
  345. ; Set Decimal
  346. SET D -> 0xF8[7:0]
  347.  
  348. ;------------------------------------------------------------------------------
  349. ; Set Interrupt Disable
  350. SET I -> 0x78[7:0]
  351.  
  352. ;------------------------------------------------------------------------------
  353. ; Set Memory Bit ++
  354. SET B0, [{src}] -> 0x87[7:0] @ src[7:0]
  355. SET B1, [{src}] -> 0x97[7:0] @ src[7:0]
  356. SET B2, [{src}] -> 0xA7[7:0] @ src[7:0]
  357. SET B3, [{src}] -> 0xB7[7:0] @ src[7:0]
  358. SET B4, [{src}] -> 0xC7[7:0] @ src[7:0]
  359. SET B5, [{src}] -> 0xD7[7:0] @ src[7:0]
  360. SET B6, [{src}] -> 0xE7[7:0] @ src[7:0]
  361. SET B7, [{src}] -> 0xF7[7:0] @ src[7:0]
  362.  
  363. ;------------------------------------------------------------------------------
  364. ; Store Accumulator
  365. LD [{src}], A -> 0x85[7:0] @ src[7:0]
  366. LD [{src},X], A -> 0x95[7:0] @ src[7:0]
  367. LD ({src}), A -> 0x8D[7:0] @ src[7:0] @ src[15:8]
  368. LD ({src},X), A -> 0x9D[7:0] @ src[7:0] @ src[15:8]
  369. LD ({src},Y), A -> 0x99[7:0] @ src[7:0] @ src[15:8]
  370. LD ([{src},X]), A -> 0x81[7:0] @ src[7:0]
  371. LD ([{src}],Y), A -> 0x91[7:0] @ src[7:0]
  372. LD ([{src}]), A -> 0x92[7:0] @ src[7:0] ; +*
  373.  
  374. ;------------------------------------------------------------------------------
  375. ; Stop Processor (Halt) ++
  376. HALT -> 0xDB[7:0]
  377.  
  378. ;------------------------------------------------------------------------------
  379. ; Store X
  380. LD [{src}], X -> 0x86[7:0] @ src[7:0]
  381. LD [{src},Y], X -> 0x96[7:0] @ src[7:0]
  382. LD ({src}), X -> 0x8E[7:0] @ src[7:0] @ src[15:8]
  383.  
  384. ;------------------------------------------------------------------------------
  385. ; Store Y
  386. LD [{src}], Y -> 0x84[7:0] @ src[7:0]
  387. LD [{src},X], Y -> 0x94[7:0] @ src[7:0]
  388. LD ({src}), Y -> 0x8C[7:0] @ src[7:0] @ src[15:8]
  389.  
  390. ;------------------------------------------------------------------------------
  391. ; Store Zero in Memory ++
  392. LD [{src}], NUL -> 0x64[7:0] @ src[7:0]
  393. LD [{src},X], NUL -> 0x74[7:0] @ src[7:0]
  394. LD ({src}), NUL -> 0x9C[7:0] @ src[7:0] @ src[15:8]
  395. LD ({src},X), NUL -> 0x9E[7:0] @ src[7:0] @ src[15:8]
  396.  
  397. LD [{src}], 0 -> 0x64[7:0] @ src[7:0]
  398. LD [{src},X], 0 -> 0x74[7:0] @ src[7:0]
  399. LD ({src}), 0 -> 0x9C[7:0] @ src[7:0] @ src[15:8]
  400. LD ({src},X), 0 -> 0x9E[7:0] @ src[7:0] @ src[15:8]
  401.  
  402. ;------------------------------------------------------------------------------
  403. ; Transfer Accumulator to X
  404. LD X, A -> 0xAA[7:0]
  405.  
  406. ;------------------------------------------------------------------------------
  407. ; Transfer Accumulator to Y
  408. LD Y, A -> 0xA8[7:0]
  409.  
  410. ;------------------------------------------------------------------------------
  411. ; Test and Reset memory Bit ++
  412. TRB [{src}] -> 0x14[7:0] @ src[7:0]
  413. TRB ({src}) -> 0x1C[7:0] @ src[7:0] @ src[15:8]
  414.  
  415. ;------------------------------------------------------------------------------
  416. ; Test and Set memory Bit ++
  417. TSB [{src}] -> 0x04[7:0] @ src[7:0]
  418. TSB ({src}) -> 0x0C[7:0] @ src[7:0] @ src[15:8]
  419.  
  420. ;------------------------------------------------------------------------------
  421. ; Transfer Stack Pointer to X
  422. LD X, SP -> 0xBA[7:0]
  423.  
  424. ;------------------------------------------------------------------------------
  425. ; Transfer X to Accumulator
  426. LD A, X -> 0x8A[7:0]
  427.  
  428. ;------------------------------------------------------------------------------
  429. ; Transfer X to Stack Pointer
  430. LD SP, X -> 0x9A[7:0]
  431.  
  432. ;------------------------------------------------------------------------------
  433. ; Transfer Y to Accumulator
  434. LD A, Y -> 0x98[7:0]
  435. ;------------------------------------------------------------------------------
  436. ; Wait for Interrupt ++
  437. WAIT -> 0xCB[7:0]
  438.  
  439. }
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