posedge jk flip flop

`timescale 1ns / 1ps

module jk(J,K,clk,Q);
    output Q;
    input J;
    input K;
    input clk;
    reg Q;
    initial
    begin
        Q = 0;
    end
    always @(posedge clk)
    begin
        case({J,K})
            2'b00 : Q <= Q;
            2'b01 : Q <= 1'b0;
            2'b10 : Q <= 1'b1;
            2'b11 : Q <= ~Q;
        endcase
    end
endmodule