module bin_cnt
(
input logic clk, resetn,
input logic [2:0] MAX,
input logic [2:0] MIN,
output logic [2:0] count
);

logic direction;

always_ff @ (posedge clk or negedge resetn)
begin
if (!resetn)
    begin
    //prev_mode <= mode;
    count <= 0;
    direction <= 1;
    end
else if (count>=MAX)
    begin
    direction <= 0;
    count <= count - 1;
    end
else if (count<=MIN)
    begin
    //prev_mode <= mode;
    direction <= 1;
    count <= count + 1;
    end
else
    begin
    if(direction)
        begin
        count <= count + 1;
        end
    else
        begin
        count <= count - 1;
        end
end
end

endmodule



`timescale 1ns/1ps
module counter_test;
integer i;
logic clk, resetn;
logic [2:0] cnt;
logic [2:0] MAX;
logic [2:0] MIN;

initial begin
clk=0;
MIN= 3'b010;
MAX= 3'b110;
forever #10 clk = ~clk;
end

initial
begin
resetn=0;
#10 resetn=1;

#400 $stop;
end
bin_cnt uut_inst(clk, resetn, MAX, MIN, cnt);
endmodule