module div (
    input signed [31:0] A,
    input signed [31:0] B,
    input clk,
    input reset,
    input DivCon,
    output reg signed [31:0] hi,
    output reg signed [31:0] lo,
    output reg exc

);

reg signed [63:0] remainder;
reg signed [63:0] Divisor;
reg signed [31:0] quo;
reg signed [63:0] aux;
reg t;
reg signed [31:0]A1;
reg signed [31:0]B1;


integer i;
initial begin
    i = 34;
    exc = 0;
end
always @ (posedge clk) begin
    if (reset == 1) begin
        remainder = 64'b0;
        Divisor = 64'b0;
        quo = 32'b0;
        aux = 64'b0;
        t = 0;
        A1 = 32'b0;
        B1 = 32'b0;
        exc = 0;
    end
    if (DivCon == 1) begin
        if (i > 33) begin
            if (B == 0) begin
                exc = 1;
            end
            else begin

                if (A < 0 && B < 0) begin
                    A1 = ~A + 1;
                    B1 = ~B + 1;
                    remainder = {32'b0, A1};
                    Divisor[63:32] = B1;
                    t = 0;
                end
                else if (A < 0) begin
                    A1 = ~A + 1;
                    remainder = {32'b0, A1};
                    Divisor[63:32] = B;
                    t = 1;
                end
                else if (B < 0) begin
                    B1 = ~B + 1;
                    remainder = {32'b0, A};
                    Divisor[63:32] = B1;
                    t = 1;
                end
                else begin
                    remainder = {32'b0, A};
                    Divisor[63:32] = B;
                    t = 0;
                end
                Divisor = Divisor <<< 1;
                Divisor[31:0] = 32'b0;
                quo = 32'b0;
                i = 0;
            end
        end
    end
    if (i < 34) begin
        aux = ~Divisor + 1;
        aux = remainder + aux;

        case (aux[63])
            1'b1: begin
                quo = quo <<< 1;
                Divisor = Divisor >>> 1;
            end
            1'b0: begin
                quo = quo <<< 1;
                Divisor = Divisor >>> 1;
                quo = quo + 1;
                remainder = aux;
            end
        endcase
        i = i + 1;
        if (i == 34) begin
            if (t == 1) begin
                A1 = ~quo + 1;
                hi = A1;
            end
            else begin
                hi = quo;
            end
            lo = remainder;
        end
    end
end

endmodule //