[wip:20200101] add F1C100s support for sunxi_timer.c

Index: sunxi_timer.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/sunxi/sunxi_timer.c,v
retrieving revision 1.7
diff -u -p -r1.7 sunxi_timer.c
--- sunxi_timer.c	14 Jun 2019 21:48:43 -0000	1.7
+++ sunxi_timer.c	1 Jan 2020 10:23:22 -0000
@@ -91,9 +91,11 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_timer.
 #define  LOSC_CTRL_OSC32K_AUTO_SWT_EN	__BIT(14)
 #define	 LOSC_CTRL_OSC32K_SEL	__BIT(0)

-static const char * const compatible[] = {
-	"allwinner,sun4i-a10-timer",
-	NULL
+static const struct of_compat_data compat_data[] = {
+	{ "allwinner,sun4i-a10-timer",		6 },
+	{ "allwinner,sun8i-v3s-timer",		3 },
+	{ "allwinner,suniv-f1c100s-timer",	3 },
+	{ NULL }
 };

 struct sunxi_timer_softc {
@@ -103,6 +105,8 @@ struct sunxi_timer_softc {
 	int sc_phandle;
 	struct clk *sc_clk;

+	int sc_ntimers;
+
 	struct timecounter sc_tc;
 	struct timecounter sc_tc_losc;
 };
@@ -178,7 +182,7 @@ sunxi_timer_match(device_t parent, cfdat
 {
 	struct fdt_attach_args * const faa = aux;

-	return of_match_compatible(faa->faa_phandle, compatible);
+	return of_match_compat_data(faa->faa_phandle, compat_data);
 }

 static void
@@ -211,6 +215,7 @@ sunxi_timer_attach(device_t parent, devi
 		aprint_error(": couldn't map registers\n");
 		return;
 	}
+	sc->sc_ntimers = of_search_compatible(phandle, compat_data)->data;

 	aprint_naive("\n");
 	aprint_normal(": Timer\n");
@@ -230,9 +235,6 @@ sunxi_timer_attach(device_t parent, devi
 	TIMER_WRITE(sc, TMR2_CTRL_REG,
 	    __SHIFTIN(TMR2_CTRL_CLK_SRC_OSC24M, TMR2_CTRL_CLK_SRC) |
 	    TMR2_CTRL_RELOAD | TMR2_CTRL_EN);
-	/* Enable Timer 4 (timecounter for LOSC) */
-	TIMER_WRITE(sc, TMR4_INTV_VALUE_REG, ~0u);
-	TIMER_WRITE(sc, TMR4_CTRL_REG, TMR4_CTRL_RELOAD | TMR4_CTRL_EN);

 	/* Timecounter setup */
 	tc->tc_get_timecount = sunxi_timer_get_timecount;
@@ -242,26 +244,31 @@ sunxi_timer_attach(device_t parent, devi
 	tc->tc_quality = 200;
 	tc->tc_priv = sc;
 	tc_init(tc);
-	tc_losc->tc_get_timecount = sunxi_timer_get_timecount_losc;
-	tc_losc->tc_counter_mask = ~0u;
-	tc_losc->tc_frequency = 32768;
-	tc_losc->tc_name = "LOSC";
-	tc_losc->tc_quality = 150;
-	tc_losc->tc_priv = sc;
-	/*
-	 * LOSC is optional to implement in hardware.
-	 * Make sure it ticks before registering it.
-	 */
-	reg = __SHIFTIN(LOSC_CTRL_KEY_FIELD_V, LOSC_CTRL_KEY_FIELD) |
-	    LOSC_CTRL_OSC32K_AUTO_SWT_EN |
-	    LOSC_CTRL_OSC32K_SEL;
-	TIMER_WRITE(sc, LOSC_CTRL_REG, reg);
-	ticks = sunxi_timer_get_timecount_losc(tc_losc);
-	delay(100);
-	if (ticks != sunxi_timer_get_timecount_losc(tc_losc))
-		tc_init(tc_losc);
-	else
-		TIMER_WRITE(sc, LOSC_CTRL_REG, reg & ~LOSC_CTRL_OSC32K_SEL);
+
+	/* Timer 4 (timecounter for LOSC) is optional */
+	if (sc->sc_ntimers > 3) {
+		tc_losc->tc_get_timecount = sunxi_timer_get_timecount_losc;
+		tc_losc->tc_counter_mask = ~0u;
+		tc_losc->tc_frequency = 32768;
+		tc_losc->tc_name = "LOSC";
+		tc_losc->tc_quality = 150;
+		tc_losc->tc_priv = sc;
+
+		/* Make sure it ticks before registering it. */
+		TIMER_WRITE(sc, TMR4_INTV_VALUE_REG, ~0u);
+		TIMER_WRITE(sc, TMR4_CTRL_REG, TMR4_CTRL_RELOAD | TMR4_CTRL_EN);
+		reg = __SHIFTIN(LOSC_CTRL_KEY_FIELD_V, LOSC_CTRL_KEY_FIELD) |
+		    LOSC_CTRL_OSC32K_AUTO_SWT_EN |
+		    LOSC_CTRL_OSC32K_SEL;
+		TIMER_WRITE(sc, LOSC_CTRL_REG, reg);
+		ticks = sunxi_timer_get_timecount_losc(tc_losc);
+		delay(100);
+		if (ticks != sunxi_timer_get_timecount_losc(tc_losc))
+			tc_init(tc_losc);
+		else
+			TIMER_WRITE(sc, LOSC_CTRL_REG,
+				    reg & ~LOSC_CTRL_OSC32K_SEL);
+	}

 	/* Use this as the OS timer in UP configurations */
 	if (!arm_has_mpext_p) {