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flash_memory.v
kekellner
Nov 15th, 2024
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SystemVerilog
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module
flash_memory
(
input
[
6
:
0
]
address
,
output
[
15
:
0
]
data
)
;
reg
[
15
:
0
]
mem
[
128
]
;
assign
data
=
mem
[
address
]
;
initial
$readmemh
(
"instrucciones.hex"
,
mem
)
;
endmodule
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